JP2003532935A - Synchronization method for RFID systems including tags with different memory sizes - Google Patents

Abstract

SUMMARY OF THE INVENTION A method of synchronizing an RFID system (10) that includes tags (40-1 through 40-n) having different memory sizes includes a method of synchronizing a synchronization word and a synchronization bit in a tag memory (407) with data bits. The reader (30) can easily identify the sync word on the RF signal (408) stored in between and transmitted by the tag (40-1) and serially modulated by repetition of the contents of the tag memory (407). And adopt the rules. After identifying the sync word, the RFID reader (30) reads the data bits following the identified sync word and ignores the sync bits scattered between the data bits until the next sync word is received.

Description

Detailed Description of the Invention

(Citation Regarding Previous Preliminary Application) The present applicant is the same inventor as the present application, filed on March 13, 1998, Ki
Claim priority of prior preliminary application number 60 / 077,987 by rk B. Bierach et al. The disclosure content of the preceding preliminary application can be used literally in the present application, and as if the disclosure content was completely specified in the present application,
It shall have the same effect. FIELD OF THE INVENTION The present invention relates generally to RFID systems, and more particularly to RFID systems that include tags having different memory sizes. BACKGROUND OF THE INVENTION Radio frequency identification (RFID) systems are known and find numerous applications. For example, RFID systems are used in access control applications, where an employee uses an RFID "proximity" card or tag to authorize authorized areas.
ea) get permission to enter. Alternatively, the tags can be fastened to the undercarriage of haul trucks and other types of vehicles to allow entry into the facility. As an example, RFID systems are used in animal identification applications where individualized tags are placed on the ears of a livestock to identify each animal.
In yet another example, RFID systems are used in container tracking applications, where individualized tags can be secured to reusable containers to facilitate accurate recording of their use.

In these and other applications, RFID tags (also called “transponders” or “labels”) typically send multiple blocks of data to an RFID reader. However, the number and size of data blocks to send is
There may be differences between tags due to different requirements for each application or differences in the memory structure for storing such data in the tags. The difference in memory or data structure occurs because of the different number of data blocks or the different number of bits within each data block being transmitted. Different manufacturers of the tag or the memory used for the tag are also one of the reasons for the different memory structures used for the tag. Advances in manufacturing technology are another cause.

However, in the conventional RFID system, data is generally communicated in a fixed amount defined by each system. This is because the system lacks the ability to read tags that send blocks of data of any size or number. Therefore, such systems are constrained to be incompatible between current and future commercially available tags, and the resulting inability to operate between systems increases the overall cost of using such systems. Will be invited. Industry standardization will help resolve these issues.

Thus, there is a need for a “method of synchronizing RFID systems that include tags having different memory sizes”. SUMMARY OF THE INVENTION One of the objects of the present invention is to be able to read data transmitted from tags with different memory sizes due to the difference in the size and number of data blocks between the tags. Is to provide.

Another object is to provide a synchronization method and means for facilitating transmission and reading of data from RFID tags having different memory sizes.

These and other objects are met by the various aspects of the present invention. Briefly, one aspect of the present invention is an RFI that includes tags having different memory sizes.
A method of synchronizing a D system, the method comprising storing a sync word in a first area of the tag memory, and a second area of the tag memory so that the sync word cannot appear in the data bit and the sync bit. Storing the data bits and the sync bits.

In another aspect, a method of synchronizing an RFID system that includes tags having different memory sizes includes transmitting a serially modulated synchronization word on an RF signal,
Transmitting the serially modulated data and sync bits on the RF signal such that the sync word cannot appear in the data and sync bits.

In another aspect, a method of synchronizing an RFID system that includes tags having different memory sizes includes a sync word, a data bit, and a sync bit, the sync word appearing within the data bit and the sync bit. Receiving an RF signal serially modulated by repeatedly storing the contents of a tag memory that cannot be stored, and identifying one iteration of a serially modulated sync word on the RF signal. Reading the data bits following one repetition of the serially modulated sync word on the RF signal until receiving the next one repetition of the serially modulated sync word on the RF signal. .

In yet another aspect, an RFID tag in an RFID system that includes tags having different memory sizes comprises tag memory, control circuitry, and modulation circuitry. The tag memory has a sync word stored at one end of the tag memory and data bits and sync bits stored in the rest of the tag memory, the sync word being stored in the rest of the tag memory. Cannot appear. The control circuit provides an address signal and a control signal to the tag memory and reads the contents of the tag memory. The modulator circuit produces an RF signal that is serially modulated by the contents of the tag memory.

In yet another aspect, an RFID reader of an RFID system that includes tags having different memory sizes consists of a receiver circuit and a processor. The receiving circuit is coupled to the RF signal modulated by the repetition of sync words, data bits, and sync bits, organized so that the sync words cannot appear in the data bits and sync bits. The processor is coupled to the receiving circuit. The processor includes a memory containing a program that causes the processor to identify one iteration of the sync word and read the data bits following one iteration of the sync word until the next iteration of the sync word is received. Including.

In yet another aspect, an RFID including tags having different memory sizes
The system consists of multiple tags and an RFID reader. Multiple tags are tags
A memory, a control circuit and a modulation circuit are individually included. The tag memory has a sync word stored at one end of the tag memory and data bits and sync bits stored in the rest of the tag memory. Cannot appear. The control circuit provides an address signal and a control signal to the tag memory and reads the contents of the tag memory. The modulator circuit produces a serially modulated RF signal by repeating the contents of the tag memory. On the other hand, RF
The ID reader includes a receiving circuit and a processor. The receiver circuit is coupled to the RF signal and the processor. The processor causes the processor to identify one iteration of the sync word and until it receives the next one of the iterations of the sync word.
It includes a memory that stores a program that causes the data bits that follow one iteration of the sync word to be read.

Further objects, features and advantages of various aspects of the present invention will become apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings. DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a block diagram of an RFID system 10 that includes tags having different memory sizes. Included in RFID system 10 is a host computer 20, an RFID reader 30, and multiple RFs having different memory sizes.
ID tags 40-1 to 40-n. RFID tag 40-1 is representative of RFID tags 40-1 through 40-n, and for the purposes of the following discussion, RFID tag 40-1 is in proximity to RFID reader 30 and may include one or more of Assume that antenna element 401 receives an excitation signal 301 transmitted via one or more corresponding antenna elements 302 of RFID reader 30. RFID
The excitation circuit 303 of the reader 30 generates the excitation signal 301.

The power supply circuit 402 on the RFID tag 40-1 rectifies the received excitation signal 301 and generates an internal power supply voltage Vdd for another circuit on the RFID tag 40-1. When the command or data is superimposed or modulated on the carrier signal of the excitation signal 301, the power supply circuit 402 passes the excitation signal 301 to the decoding circuit 403. The decoding circuit 403 demodulates the excitation signal 301, performs analog / digital conversion, generates a command or data in digital form, and supplies this to the control circuit 404. The power supply circuit 402 also passes the excitation signal 301 to the clock generation circuit 405.

The clock generation circuit 405 generates two clock signals. One clock signal has the same frequency as the excitation carrier signal and is supplied to the control circuit 404. The other clock signal has a different frequency than the excitation carrier signal, and the modulation circuit 406
And functions as a tag carrier signal of the RF signal 408 transmitted from the RFID tag 40-1. In the preferred embodiment, the frequency of the tag carrier signal is approximately half the frequency of the excited carrier signal to distinguish between the two carrier signals.

The control circuit 404 includes an address counter (not shown), and the tag memory 4
The address to 07 is incremented. In response to the excitation signal 301, the control circuit 404
Generates an appropriate control signal to repeatedly read information from the tag memory 407 serially at the rate of the excitation carrier signal. Next, the information is supplied to the modulation circuit 406. Modulation circuit 406 superimposes or modulates this information on the tag carrier signal,
RF signal 408 serially modulated by repeating the contents of tag memory 407
To occur. In the preferred embodiment, RF signal 408 is a sync word, organized such that no sync word can appear between the data bits and sync bits.
It is modulated serially by repeating data bits and sync bits. The transmit antenna 409 coupled to the modulation circuit 406 transmits the RF signal 408 to the receive antenna 304 on the RFID reader 30.

Receiving circuit 305 is coupled to RF signal 408 via receiving antenna 304,
The RF signal 408 is received and amplified. Also, the receiver circuit 305 preferably converts the frequency of the RF signal 408 to an intermediate frequency for subsequent amplification and bandpass filtering and then supplies it to the detector circuit 306. The detection circuit 306 detects the information that is modulated in series on the RF signal 408 and provides the information to the processor 307. Processor 307 produces output in a format usable by host computer 20. The processor 307 includes a memory (not shown) that stores a program executed by the processor 307. The host computer 20 processes the passed information by the processor 307.

Tag memory 407 may be of different sizes by being organized into various memories or data structures having different numbers of blocks and / or different numbers of bits per block. For example, FIG. 2 shows the data structure of the tag memory 407 having seven blocks of 32 bits each, FIG. 6 shows the data structure having seven blocks of 16 bits each, and FIG. A data structure is shown having three blocks of five hexadecimal characters (ie, 20 bits each, because each hexadecimal character is 4 bits).

Since the contents of the tag memory 407 are repeatedly read and modulated in series on the RF signal 408, the RFID reader 30 does not have to know the data structure in advance, and thus the repeating pattern (that is, the tag memory 407 Determining the content can be difficult or impossible. For example, in FIG. 8, the pattern “012345678
9ABCDE "is stored in the first example of prior art tag memory organization,
In the figure, the pattern "56789ABCDE01234" is stored in the second example of the prior art tag memory organization, and in FIG. 10, the pattern "ABCDE012" is stored.
3456789 "is stored in the third example of the prior art tag memory organization. More problematic is when starting from the top left corner of the tag memory 407, reading information from the tag memory 407, reading to the right along each block, reading the blocks from top to bottom, and ending at the bottom right corner. , These patterns each generate the same repeating or recursive pattern shown in FIG. As another example,
For certain repeating patterns, such as all 1's or 0's, or alternating 1's and 0's, RFID reader 30 is virtually impossible to determine the length of the recursive pattern without prior knowledge of the data structure. .

Accordingly, aspects of the present invention allow RFID reader 30 to include a sync word that begins at the start address of tag memory 407 or ends at the end address of tag memory 407, thereby causing RFID reader 30 to generate RF signals. The purpose is to enable the contents of the tag memory 407 to be properly read from 408. To ensure that the sync word is inadvertently repeated elsewhere in the recursive pattern, the sync bits are interspersed at appropriate bit positions in the recursive pattern. The RFID reader 30 then finds the sync word first, and then until the sync word appears next.
The recursive pattern can be determined by reading the data following the sync word and ignoring, hiding or deleting the sync bit during that time.

Referring briefly to FIG. 6, sync word 52 is shown as “1000000000000001” starting at the starting address of tag memory 407:
Like the sync bit set 54 in the seventh block of the memory structure, a "0
The sync bit set of "1" is the data bit "x" such as data bit 56.
, The sync word cannot appear in the data and sync bits. The sync word and sync bit are also referred to as "system bits", and the data bits are also referred to as "user data bits". Consecutive data bits between sync words and sync bit sets, or between sync bit sets, are referred to as "data words", such as data word 58 in the second block of tag memory 407. FIG. 7 shows another example data structure in which the sync word ends at the ending address of the tag memory 407.

In order to easily identify the sync word, the sync word is already defined as a bit pattern. In this bit pattern, the maximum number of 0's is sandwiched between two 1's in the content of the data structure. To ensure that the sync word contains the maximum number of 0's sandwiched between two 1's, a sync bit set of "01" is periodically inserted between the data bits, and adjacent sync bits are • Ensure that the number of data bits between sets is less than the number of bits in the sync word by 4 bits or less. Alternatively, a single sync bit of "1" could be used instead of sync bit pair "01". In this case, the data
The number of bits will be less than or equal to 3 bits in the sync word.

The number of data bits between adjacent sync bit sets “01” can be less than 4 bits less than the number of bits in the sync word, but the maximum number of bits in the data structure of the data bits is In order to be able to use, the number of data bits between adjacent sets of sync bits is preferably set equal to 4 bits less than the number of bits in the sync word. Also, by following this rule,
After the RFID reader 30 identifies the sync word, the position of the sync bit can be easily determined, and the RFID reader 30 reads the serially modulated data bits on the RF signal 408 while hiding or sync bits. It will be easier to delete.

Further, as shown in FIG. 2, the data structure of the tag memory 407 is also the RFID reader 30 by obeying the rule that the sync word includes the entire first data block.
Can be easily determined by. However, this rule may not be practical for data structures that contain a relatively small number of blocks. Moreover, a short sync word, such as that shown in FIG. 3, may make more data bits available in tag memory 407 than a sync word that exhausts the entire first block. However, this is not generally the case, as shown in FIGS. 4 and 5.

Thus, in summary, by storing the sync word and sync bits in memory 407 according to known rules, the RFID reader 30 is provided with the content or repetitive pattern stored therein, the received RF signal. It can be easily determined from the information modulated on 408. Implementation of RFID reader 30 is straightforward and within the knowledge of one of ordinary skill in the art.

FIG. 12 shows a flow diagram of a method of synchronizing RFID system 10 including tags 40-1 through 40-n having different memory sizes. The first step 1201 consists of storing the sync word in the first area of the tag memory. The first area is preferably a continuous bit position starting from the starting address of the tag memory, as shown in FIG. In this case, the step of storing the sync word comprises the step of storing the sync word in consecutive bit positions starting at the starting address of the tag memory. Alternatively, the first area may be a continuous bit position ending at the ending address of the tag memory, as shown in FIG. In such cases,
The step of storing the sync word comprises the step of storing the sync word in successive bit positions ending at the ending address of the tag memory. Since the sync word is preferably already defined in the content of the data structure of the tag memory as a bit pattern with a maximum number of 0's between two 1's, the step of storing the sync word Comprises storing one bit of the first binary state, storing a plurality of bits of the second binary state, and storing one bit of the first binary state. The storage of the sync word is preferably done by programming the tag memory after manufacture by conventional methods and means. However, alternatively, the storage of the sync word by conventional methods and means during the tag memory or tag manufacturing process may provide similar advantages.

A second step 1202 stores a data bit and a sync bit in a second area in the tag memory and disables the sync word from appearing in the data bit and the sync bit. It consists of steps. The second area is the rest of the tag memory after storing the sync word in the tag memory. In general terms, interspersing sync bits between the data bits makes it impossible for the sync word to appear in the rest of the tag memory.
More particularly, the step of storing the data bits and the sync bits comprises organizing the data bits into data words each having a number of data bits which is at least 4 bits less than the number of bits in the sync word. And the first
Arranging sync bits into a sync bit set each having at least one bit in a binary state, and interleaving the sync bit set with the data word to provide the data word and the sync bit・
Storing the set in the tag memory. The storage of data bits and sync bits is preferably done by programming the tag memory after manufacture by conventional methods and means. However, alternatively, storage of the data bits and sync bits by conventional methods and means during the tag memory or tag manufacturing process may provide similar advantages.

The third step 1203 consists of transmitting the serially modulated sync word on the RF signal. Preferably, the step of sending the synchronization word comprises:
It comprises the steps of transmitting one bit in the first binary state, transmitting a plurality of bits in the second binary state, and transmitting one bit in the first binary state. The control circuit 404 in the tag memory 407 is used to perform such steps.
Generates an appropriate control signal, repeatedly reads information from the tag memory 407 in series, and supplies it to the modulation circuit 406. Modulation circuit 406 generates an RF signal 408 that is serially modulated by the contents of tag memory 407. A transmit antenna 409 coupled to the modulation circuit 406 transmits the RF signal 408.

A fourth step 1204 is to transmit serially modulated data and sync bits on the RF signal such that the sync word cannot appear in the data and sync bits. Consists of. Preferably, the step of transmitting data bits and sync bits comprises the data bits organized into data words each having a number of data bits that is at least four less than the number of bits in the sync bits, and At least one of the first binary states
Transmitting sync bits organized into a sync bit set having individual bits and interleaving the sync bit set with the data word. In order to perform such steps, the control circuit 40 in the tag memory 407
4 generates an appropriate control signal to repeatedly read information from the tag memory 407 in series, and supplies the information to the modulation circuit 406. The modulation circuit 406 is a tag memory 407.
Generates an RF signal 408 which is serially modulated with the contents of A transmit antenna 409 coupled to the modulation circuit 406 transmits the RF signal 408.

A fifth step 1205 is to serially modulate the RF signal by repeating the sync word, the data bits, and the contents of the tag memory storing the sync bits.
Receiving the sync word such that it cannot appear in the data bits and the sync bits. To perform such steps, receiver 305 is coupled to receive antenna 304 and receives and amplifies RF signal 408, as described with reference to FIG.

A sixth step 1206 consists of identifying one repetition of the sync word serially modulated on the RF signal. Preferably, the step of identifying one repetition of the sync word comprises finding the serially modulated longest bit sequence in the second binary state on the RF signal. The sync word comprises one bit in a first binary state, a plurality of bits in a second binary state, and the first bit.
Organized as one bit in the binary state, this involves finding the longest bit sequence in the second binary state that is serially modulated onto the RF signal. To perform such steps, the processor 307 causes the processor 307 to identify one repetition of the sync word by finding the maximum number of consecutive bits in the second binary state using conventional programming methods. It includes a memory (not shown) storing a program.

A seventh step 1207 is to repeat the repetition of the sync word serially modulated on the RF signal until the next repetition of the sync word modulated on the RF signal is received. The step of reading the data bit following the one time. Preferably, said step of reading data bits is (a) reading a number of consecutive data bits, said number being 4 bits less than the number of bits of said sync word, and (b) Reading the next bit following the number of consecutive data bits, (c) the next bit being the first bit.
Stopping in the binary state, or ignoring the bit following the next bit and returning to step (a) if the next bit is in the second binary state. . To perform such steps, processor 307 includes a memory (not shown) storing a program that causes processor 307 to perform such steps using conventional programming methods.

One of the advantages of the present invention is that the RFID system can read data transmitted from tags with different memory sizes, allowing compatibility between current and future commercially available tags. That is. Another advantage is that RFID systems can read data transmitted from tags with different memory sizes, allow intersystem operation, and provide overall cost savings for such systems.

While particular embodiments of the present invention have been described above in detail, it will be appreciated that various modifications may be made to the preferred embodiments without departing from the scope of the invention. Therefore, the above description is not meant to limit the invention which is defined by the appended claims.

[Brief description of drawings]

FIG. 1 is a block diagram of an RFID system that includes tags having different sizes, utilizing aspects of the present invention.

FIG. 2 is a diagram illustrating an example of a tag memory organization including a 32-bit sync word that utilizes aspects of the present invention.

FIG. 3 is a diagram of an example tag memory organization including a 24-bit sync word utilizing aspects of the present invention.

FIG. 4 is a diagram of an example tag memory organization including a 16-bit sync word utilizing aspects of the present invention.

FIG. 5 is a diagram of an example tag memory organization including a 9-bit sync word utilizing aspects of the present invention.

FIG. 6 starts 16 at the start address of the tag memory utilizing aspects of the present invention.
FIG. 6 is an example of a tag memory organization including bit sync words.

FIG. 7 terminates at the ending address of the tag memory 16 utilizing aspects of the present invention.
FIG. 6 is an example of a tag memory organization including bit sync words.

[Figure 8]   FIG. 1 is a diagram of a first example of prior art tag memory organization.

[Figure 9]   FIG. 5 is a diagram of a second example of prior art tag memory organization.

[Figure 10]   FIG. 5 is a diagram of a third example of prior art tag memory organization.

FIG. 11 is a diagram of an example of repeating the contents of any one of the first, second, or third examples of prior art tag memory organization.

FIG. 12 is an RFID including tags having different memory sizes utilizing aspects of the present invention.
FIG. 6 is a flowchart of a system synchronization method.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, SD, SL, SZ, UG, ZW), E A (AM, AZ, BY, KG, KZ, MD, RU, TJ , TM), AL, AM, AT, AU, AZ, BA, BB , BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GD, GE, G H, GM, HR, HU, ID, IL, IN, IS, JP , KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, M W, MX, NO, NZ, PL, PT, RO, RU, SD , SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZW (72) Inventor Mark Daniel Fitzpatrick             Santa, California, United States             Clara, Cabrillo Avenue 1497 F-term (reference) 5B001 AA13 AB00 AC05 AD07 AE02                 5B035 AA00 BB09 BC00 CA11 CA23                 5B058 CA17 CA23 KA02 KA04 KA08                       YA20

Claims (9)

[Claims] 1. An RFID tag of an RFID system including tags having different memory sizes: a sync word stored at one end of the tag memory and the rest of the tag memory. A tag tag having a data bit and a sync bit, making it impossible for the sync word to appear in the rest of the tag memory.
A memory; a control circuit for supplying an address signal and a control signal to the tag memory to read the contents of the tag memory; and a modulation circuit for generating an RF signal serially modulated by the contents of the tag memory. An RFID tag characterized in that. 2. The synchronization word comprises one bit in a first binary state, a plurality of bits in a second binary state, and one bit in the first binary state. R of 1
FID tag. 3. The RFID of claim 2, wherein the sync bits are interspersed between the data bits so that the sync word cannot appear in the remaining portion of the tag memory. tag. 4. The data bits are organized into data words each having a number of data bits that is four bits less than the number of bits in the sync word, the sync bits being at least in the first binary state. An RFID tag as claimed in claim 3, characterized in that it is organized into a set of sync bits comprising one bit, said set of sync bits being interleaved with said data words. 5. An RFID reader of an RFID system including tags having different memory sizes, wherein a sync word is arranged such that a sync word cannot appear in the data bit and the sync bit, and the data. A bit and a receiver circuit coupled to the RF signal that is serially modulated by the repetition of the synchronization bit; and a processor coupled to the receiver circuit, wherein the processor is provided with one repetition of the synchronization word. A processor comprising a memory storing a program for identifying and reading a data bit following the one iteration of the sync word until the next iteration of the sync word is received; . 6. Each of the sync words comprises one bit in a first binary state, a plurality of bits in a second binary state, and one bit in the first binary state. The RFID reader according to claim 5. 7. The data bits are organized into data words each having a number of data bits that is less than the number of bits of the sync word by 4 bits, the sync bits being at least in the first binary state. 7. An RFID reader as claimed in claim 6, characterized in that it is organized into a sync bit set comprising one bit, said sync bit set being interleaved with said data words. 8. The program of claim 7, wherein the program causes the processor to identify one iteration of the sync word by finding the longest bit sequence in the second binary state. RFID reader. 9. An RFID system including tags having different memory sizes: a plurality of tags each including a tag memory and a control circuit and a modulation circuit, the tag memory comprising a synchronization word. So that they cannot appear in the data and sync bits, the sync word stored at one end of the tag memory and the data bit stored in the rest of the tag memory; The synchronization circuit, the control circuit provides an address signal and a control signal to the tag memory, reads the contents of the tag memory, and the modulation circuit repeats the contents of the tag memory. A tag for producing a serially modulated RF signal; and an RFID reader including a receiving circuit and a processor, the receiving circuit comprising: Coupled to the RF signal, the processor, to the processor, the synchronization word 1
A processor comprising a memory storing a program for identifying a single iteration and reading a data bit following the single iteration of the sync word until a next iteration of the sync word is received on the RF signal. An RFID system comprising: