KR20010046895A - Decoder - Google Patents

Abstract

PURPOSE: A decoder is provided to work at a high speed and consume low power and to be used to make a simple thermometer code decoder, decoding N input signals into M(2¬N) bit output signals. CONSTITUTION: The decoder circuit(10) includes a converter of thermometer code for high level signal(12), a converter of thermometer code for low level signal(14) and a logic circuit(16). The converter of thermometer code for high level signal(12) receives and converts the three high level signals(IN5,IN4,In3) of the six input signals into thermometer code of seven bit signals(MSB1-MSB7). The converter of thermometer code for low level signal(14) receives and converts the three low level signals(IN2,IN1,IN0) into thermometer code of seven bit signals(LSB1-LSB7). The logic circuit(16) receives and combines the signals(MSB1-MSB7,LSB1-LSB7) from the first and second converters of thermometer code(12,14) and produces 64 bit decoded signals(OUT0-OUT63).

Description

Decoder {DECODER}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a circuit for decoding a signal input from the outside into a thermometer code.

The N bit binary code may represent different 2 ^N element information. A decoder is a combination circuit that converts binary information coded with N bits into up to 2 ^N different outputs. A decoder having ^N inputs and M (M = 2 ^N ) outputs is called an NXM decoder.

1 is a block diagram showing a typical 6 X 64 decoder. The decoder 1 has six inputs IN0 to IN5 and 64 outputs OUT0 to OUT63. Conventional decoders have a disadvantage in that the operating speed is slowed down and the current consumption increases as the number of input bits increases.

Accordingly, it is an object of the present invention to provide a decoder that not only operates at high speed but also consumes low power.

1 is a block diagram showing a typical 6X64 decoder;

2 is a table showing a binary number that can be represented by six input signals input to a decoder;

3 is a block diagram showing a circuit configuration of a decoder according to a preferred embodiment of the present invention;

4 is a detailed circuit diagram of a first thermometer code converter shown in FIG. 3;

5 is a detailed circuit diagram of a second thermometer code converter shown in FIG. 3;

6 illustrates a method of generating decoded signals by combining signals output from the first and second thermometer code converters; And

FIG. 7 is a detailed circuit diagram of the decoding unit illustrated in FIG. 3 based on FIG. 6.

* Description of the symbols for the main parts of the drawings *

10: decoder 12: first thermometer code converter

14 second thermometer code conversion unit 16 logic circuit

According to a feature of the present invention for achieving the object of the present invention as described above, a decoder that accepts ^N input signals and decodes them into M (M = 2 ^N ) bit output signals: First thermometer code conversion means for receiving a group of input signals and converting the same into a thermometer code; Second thermometer code converting means for receiving another group of input signals among the N input signals and converting the same into a thermometer code; And a logic circuit which receives and combines the thermometer codes converted by the first and second thermometer code conversion means and outputs the result as the M-bit output signal.

(Action)

By such a circuit, a thermometer code decoder with a simple circuit configuration can be implemented. Moreover, the operating speed of the decoder is improved and the current consumption is reduced.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 8. In the following description, the same or similar reference numerals and signs in the drawings represent the same or similar components as much as possible.

2 is a table showing binary numbers that can be represented by six input signals input to a decoder.

Referring to FIG. 2, 64 binary numbers that can be represented by six input signals IN0, IN1, IN2, IN3, IN4, and IN5 are all 64 from (00000) to (111111). When the input signals are divided into the upper three input signals IN5, IN4 and IN3 and the lower three input signals IN2, IN1 and IN0, the lower signals IN2, IN1 and IN0 represent (000). Except seven, it appears repeatedly. Meanwhile, the upper signals IN5, IN4, and IN3 have the same value every seven.

Therefore, the six input signals are separated into upper signals IN5, IN4, and IN3 and lower signals IN3, IN2 and IN1, and each of them is decoded into a predetermined code, and the decoded codes are recombined so that the six input signals are combined. You can get the same result as if you decode it. Detailed description thereof will be continued later.

3 is a block diagram showing a circuit configuration of a decoder according to a preferred embodiment of the present invention. Referring to FIG. 3, the decoder 10 includes an upper signal thermometer code converter 12, a lower signal thermometer code converter 14, and a logic circuit 16. Since the thermometer code is well known in the art, a detailed description thereof will be omitted.

The first thermometer code converter 12 receives the upper three input signals IN5, IN4, and IN3 among the six input signals and converts 7-bit signals MSB1 to MSB7 converted into thermometer codes. Output The second thermometer code converter 14 receives the lower three input signals IN2, IN1, and IN0 among the six input signals and converts the 7-bit signals LSB1 to LSB7 converted into thermometer codes. Output

The logic circuit 16 receives and combines the signals MSB1 to MSB7 and LSB1 to LSB7 input from the first and second thermometer code converters 12 and 14, and decodes the result of 64-bit decoding. Outputs the signals OUT0 to OUT63.

FIG. 4 is a detailed circuit diagram of the first thermometer code converter illustrated in FIG. 3.

Referring to FIG. 4, the first thermometer code converter 12 includes end gates 121, 122, 124, and 125 and ora gates 123, 126, 127, and 128. The AND gate 121 receives and performs the upper input signals IN5, IN4, and IN3, and outputs the result MSB7. The AND gate 121 outputs '1' when the input signals are all logic '1'.

The AND gate 122 receives and inputs the input signals IN5 and IN4, and outputs the result MSB6. The AND gate 122 outputs '1' when all of the input signals IN5 and IN4 are '1' regardless of the input signal IN3.

The OR gate 123 receives and inputs the input signals IN4 and IN3, and the AND gate 124 receives and outputs the output signal of the OR gate 123 and the input signal IN5. And outputs the result (MSB5). The signal MSB5 output from the AND gate 124 becomes '1' when the input signal IN5 is '1' and one of the input signals IN4 and IN3 is '1'.

The input signal IN5 is output as it is as the signal MSB4.

The AND gate 124 receives and operates the input signals IN4 and IN3, and the OR gate 126 receives and calculates an output signal of the AND gate 124 and the input signal IN5. The result (MSB3) is output. The signal MSB3 output from the OR gate 126 becomes '1' when all of the input signals IN4 and IN3 are '1' or when the input signal IN5 is '1'.

The OR gate 127 receives and operates the input signals IN5 and IN4, and outputs the result MSB2. The signal MSB2 becomes '1' when at least one of the input signals IN5 and IN4 is '1'.

The OR gate 128 receives and operates the input signals IN5, IN4, and IN3, and outputs the result MSB1. The signal MSB1 becomes '1' when at least one of the input signals IN5, IN5, and IN3 is '1'.

The first thermometer code converter 12 having the configuration as described above outputs the signals MSB [7: 1] shown in Table 1 according to the upper input signals IN5, IN4, and IN3. .

TABLE 1

FIG. 5 is a detailed circuit diagram of the second thermometer code converter shown in FIG. 3, and has the same configuration as the first thermometer code converter shown in FIG. 4. Therefore, redundant description is omitted.

The second thermometer code converter 14 outputs the signals LSB [7: 1] shown in Table 2 according to the lower input signals IN2, IN1, and IN0.

TABLE 2

FIG. 6 is a diagram illustrating a method of generating the decoded signals 0UT1 to OUT63 by combining signals output from the first and second thermometer code converters.

The first output signal OUT1 becomes '1' when at least one of the signals IN5 to IN0 input from the outside is a logic '1'. Therefore, the first output signal OUT1 is the logic OR of the signal MSB1 output from the first thermometer code converter 12 and the signal LSB1 output from the second thermometer code converter 14. Same as the result of the calculation.

The second output signal OUT2 may be at least one of the upper input signals IN5, IN4, and IN3 input from the outside, or the input signal IN3 among the lower input signal signals IN2, IN1, and IN0. ) Or (IN1) is logical '1', resulting in '1'. Therefore, the second output signal OUT2 is the logic OR of the signal MSB1 output from the first thermometer code converter 12 and the signal LSB2 output from the second thermometer code converter 14. Same as the result of the calculation.

The third to seventh output signals OUT3 to OUT7 may be obtained by the same method as the first and second output signals OUT1 and OUT2.

The eighth output signal OUT8 becomes '1' if at least one of the upper input signals IN5, IN4, IN3 is logic '1', regardless of the lower input signals IN2, IN1, IN0. Therefore, the eighth output signal OUT8 is the same as the signal MSB1 output from the first thermometer code converter 12.

At least one of the ninth output signals OUT9 is logic '1' among the upper input signals IN5, IN4, and IN3, and at least one of the lower input signals IN2, IN1 and IN0 is logic '. 1 'means' 1'. Accordingly, the ninth output signal OUT9 receives the signal MSB1 output from the first thermometer code converter 12 and the signal LSB1 output from the second thermometer code converter 14. Same as the result of the calculation.

According to the method as described above, a combination of the signals MSB1 to MSB7 and LSB1 to LSB7 output from the first thermometer code converter 12 and the second thermometer code converter 14 is shown in FIG. 6. As shown in FIG. 2, the remaining output signals OUT10 to OUT63 may be obtained.

FIG. 7 is a detailed circuit diagram of the logic circuit shown in FIG. 3 based on FIG. 6.

Referring to FIG. 7, the logic circuit 16 includes OR gates 171 to 177 and AND gates 161 to 168. The OR gate 177 performs a calculation on the signal MSB1 output from the first thermometer code converter 12 and the signal LSB1 output from the second thermometer code converter 14, and as a result, Is output as the first output signal OUT1.

The AND gate 161 performs an AND operation on the signal MSB7 output from the first thermometer code converter 12 and the signal MS7 output from the second thermometer code converter 14. The result is output as the 63rd output signal OUT63.

Operation of the OR gates 171 to 176 and the AND gates 161 to 168 will be omitted.

FIG. 8 is a diagram illustrating a result of simulating the operation of the decoder illustrated in FIG. 3.

As described above, the decoder of the present invention divides six input signals into upper signals and lower signals, converts each into a thermometer code, and then combines the converted signals to output a decoded signal. Therefore, even if the number of bits of the input signal increases, the circuit configuration of the decoder does not increase exponentially. Furthermore, by implementing pass transistor logic (PTL) of the AND gates and the OR gates used in the preferred embodiment of the present invention, the decoder not only operates at high speed but also reduces power consumption.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, it is possible to implement a thermometer code decoder with a simple circuit configuration. Moreover, the operating speed of the decoder is improved and the current consumption is reduced.

Claims (2)

A decoder that accepts N input signals and decodes them into M (where M = 2 ^N ) bits of output signal: First thermometer code converting means for receiving a group of input signals among the N input signals and converting the same into a thermometer code; Second thermometer code converting means for receiving another group of input signals among the N input signals and converting the received input signals into the thermometer code; And And a logic circuit for accepting and combining the thermometer codes converted in the first and second thermometer code conversion means and outputting the result as the M-bit output signal. The method of claim 1, And the output signal of the M bits is a thermometer code.