JPS5921235B2 - encoding device - Google Patents

encoding device

Info

Publication number
JPS5921235B2
JPS5921235B2 JP52015858A JP1585877A JPS5921235B2 JP S5921235 B2 JPS5921235 B2 JP S5921235B2 JP 52015858 A JP52015858 A JP 52015858A JP 1585877 A JP1585877 A JP 1585877A JP S5921235 B2 JPS5921235 B2 JP S5921235B2
Authority
JP
Japan
Prior art keywords
symbols
code word
symbol
dominant
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52015858A
Other languages
Japanese (ja)
Other versions
JPS53100713A (en
Inventor
文孝 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP52015858A priority Critical patent/JPS5921235B2/en
Publication of JPS53100713A publication Critical patent/JPS53100713A/en
Publication of JPS5921235B2 publication Critical patent/JPS5921235B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes

Description

【発明の詳細な説明】 本発明は二値シンボルの出現確率が近接する情報源の出
力シンボルを符号化する符号化装置に関するものである
00従来、二値シンボルの出現確率が近接する情報源に
対して、これを有効に符号化する実用的な符号としては
、第1図に示すものが知られている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an encoding device that encodes output symbols of an information source in which the probabilities of appearance of binary symbols are close to each other. On the other hand, as a practical code for effectively encoding this, the one shown in FIG. 1 is known.

しかるに、対象情報源が無記憶情報源の場合を考えると
、発生頻度の高い優勢シンボルの出現確率が約0.62
以下では、圧縮が行なえないという難点があつた。本発
明は、かかる点に鑑みてなされたもので。
However, when considering the case where the target information source is a memoryless information source, the probability of appearance of a dominant symbol with a high occurrence frequency is approximately 0.62.
The problem with the following is that compression cannot be performed. The present invention has been made in view of this point.

n+1優勢シンボルの発生確率をPとするとき、P>(
1−P)nを満たすnを選び、情報源からの出力シンボ
ルを、合計(n+1)個の優勢シンボルを含むパターン
及び合計n個の劣勢シンボルを含むパターンに区切り、
該区切られたパターンが、優勢シンボルのみからなる時
はこれにnビットの符号語を、劣勢シンボルのみからな
る時はこれに(n+1)ビットの符号語を、それ以外の
時は該パターン中の二値シンボル数と同じビット数の符
号語を与えることにより、優勢シンボルの出現確率がど
んなに0.5に近くとも、その出現過程が無記憶過程に
従う限り必ず符号化圧縮が行なえる符号化装置を提供す
ることを目的としている。
When the probability of occurrence of n+1 dominant symbols is P, P>(
1-P) select n that satisfies n, and divide the output symbols from the information source into a pattern including a total of (n+1) dominant symbols and a pattern including a total of n inferior symbols;
When the delimited pattern consists only of dominant symbols, an n-bit code word is added to it, when it consists only of inferior symbols, an (n+1) bit code word is added to it, and in other cases, an n-bit code word is added to it. By providing a code word with the same number of bits as the number of binary symbols, we have developed an encoding device that can always perform encoding compression, no matter how close the probability of appearance of a dominant symbol is to 0.5, as long as the appearance process follows a memoryless process. is intended to provide.

以下、本発明の実施例を図について説明する。第5図は
本発明の一実施例による符号化装置の概略構成図であり
、100は被符号化シンボル中の優勢シンボル″0”を
計数する″o’’シンボルカウンタ、101は劣勢シン
ボル゛1’’を計数する゛1’’シンボルカウンタであ
り、上記゛o’’シンボルカウンタ100はその計数値
が(n+1)になる毎に、又上記゛l”シンボルカウン
タ101はその計数値がnになる毎に信号を出力するも
のである。ここで上記nは、以下のようにして選はれる
ものである。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 5 is a schematic configuration diagram of an encoding apparatus according to an embodiment of the present invention, in which 100 is an "o" symbol counter that counts the dominant symbols "0" among the symbols to be encoded, and 101 is an "o" symbol counter that counts the dominant symbols "0" among symbols to be encoded; '', the ``o'' symbol counter 100 counts each time its counted value reaches (n+1), and the ``l'' symbol counter 101 counts each time its counted value reaches n. It outputs a signal every time the signal changes. Here, the above n is selected as follows.

即ちnは、対象情報源が無記憶過程に従つてシンボルを
出力するとき、゛0”シンボルの出現確率をP(>1/
2)、″1’’シンボルの出現確率を(1−P)として
、pnf1>(1−P)nを満たすものである。また、
102は符号器であり、該符号器102は上記゛o”シ
ンボルカウンタ100、又ば1’’シンボルカウンタ1
01から信号が出力される毎にシンボル系列を区切り、
該区切られたパターンの内容が゛o”シンボルのみであ
れは、これを1″がnビツト連続する符号語に、。
That is, when the target information source outputs symbols according to the memoryless process, n is the probability of appearance of the "0" symbol as P(>1/
2), where the probability of appearance of the "1" symbol is (1-P), pnf1>(1-P)n is satisfied.
102 is an encoder, and the encoder 102 is the above-mentioned ゛o'' symbol counter 100, or 1'' symbol counter 1.
Separate the symbol sequence every time a signal is output from 01,
If the content of the delimited pattern is only the "o" symbol, convert it into a code word with n consecutive 1" bits.

r゛シンボルのみであれは″0″が(n+1)ビツト連
続する符号語に、”0”ど1゛とが混在していればこれ
をそれと同じパターンの符号語に変換して出力するもの
である。第2図は、本発明において、n=2とした場合
の符号形式例であり、第3図A,b,cは、二値シンボ
ル系列と符号化シンボル系列と符号列との対応を示すも
のである。
If it is only the r゛ symbol, it is a code word with (n+1) consecutive bits of ``0'', but if there is a mixture of ``0'' and 1'', this is converted into a code word with the same pattern and output. be. Fig. 2 shows an example of a code format when n=2 in the present invention, and Fig. 3 A, b, and c show correspondences between a binary symbol sequence, a coded symbol sequence, and a code string. It is.

次にこの第2図、第3図により動作を説明する。Next, the operation will be explained with reference to FIGS. 2 and 3.

今、n=2であるから、第3図aの二値出力シンボル系
列はシンボル60″が3個出現するか、シンボル“1゛
が2個出現するかで区切られ、第3図bのシンボル系列
が得られる。これに第2図の符号語を割当てると、第3
図cの符号系列が得られる。第2図の符号語例では、3
(n+1)個の゛0”シンボルのみからなるパターンに
は、″F゛シンボル2(n)個を符号語とし、2個の″
1″シンボルのみからなるパターンには″O″シンボル
3個を符号語とし、その他のパターンについては、原シ
ンボル系列そのままを符号語としている。
Now, since n=2, the binary output symbol sequence in Figure 3a is divided by whether the symbol 60'' appears three times or the symbol ``1'' appears two times, and the symbol in Figure 3b A series is obtained. Assigning the code word in Figure 2 to this, the third
The code sequence shown in figure c is obtained. In the example code word in Figure 2, 3
For a pattern consisting only of (n+1) "0" symbols, 2(n) "F" symbols are used as codewords, and two "F" symbols are used as code words.
For patterns consisting only of 1'' symbols, three ``O'' symbols are used as code words, and for other patterns, the original symbol sequence is used as a code word.

またこのような構成により、符号器102の構成は、極
めて容易となる。一方、受信側では、やはり、゛0”シ
ンボルの合計が3(o+l)個、または、゛1゛シンボ
ルの合計が2(n)個となつた時点で区切りを入れ、゛
O”シンボル3個のみからなるパターンは、“1″シン
ボル2個に、″F゛シンボル2個のみからなるパターン
ばO”シンボル3個に変換し、他のパターンは、符号そ
のままを復号信号としている。
Moreover, such a configuration makes the configuration of the encoder 102 extremely easy. On the other hand, on the receiving side, a break is placed when the total number of "0" symbols reaches 3(o+l) or the total number of "1" symbols reaches 2(n), and three "O" symbols are added. A pattern consisting of only two "F" symbols is converted into two "1" symbols, a pattern consisting of only two "F" symbols is converted into three O" symbols, and the other patterns are converted into decoded signals with their codes as they are.

従つて、この受信側においても容易に復号できる。なお
第4図は、無記憶情報源に対し、その符号化効率を示す
ものであり、斜線部は、符号化圧縮ができない部分であ
る。以上のように、本発明によれば、優勢シンボルの発
生確率をPとするとき、PO+1〉(1−P)1を満た
すnを選び、情報源からの出力シンボルを、合計(n+
1)個の優勢シンボルを含むパターン及び合計n個の劣
勢シンボルを含むパターンに区切り、該区切られたパタ
ーンが、優勢シンボルのみからなる時はこれにnビツト
の符号語を、劣勢シンボルのみからなる時はこれに(n
+1)ビツトの符号語を、それ以外の時は該パターン中
の二値シンボル数と同じビツト数の符号語を与えるよう
にしたので、二値シンボルの出現確率が近接する情報源
を極めて効率よく符号化できる効果がある。
Therefore, it can be easily decoded on the receiving side as well. Note that FIG. 4 shows the encoding efficiency for a memoryless information source, and the shaded area is the portion that cannot be encoded and compressed. As described above, according to the present invention, when the probability of occurrence of a dominant symbol is P, n is selected that satisfies PO+1>(1-P)1, and the output symbols from the information source are summed (n+
1) Divide into a pattern containing a total of n dominant symbols and a pattern containing a total of n recessive symbols, and when the divided pattern consists of only dominant symbols, add an n-bit code word to it and consist of only recessive symbols. Time is like this (n
+1) Since the bit code word is given as the same number of bits as the number of binary symbols in the pattern at other times, it is possible to extremely efficiently identify information sources with probabilities of appearance of binary symbols that are close to each other. It has the effect of being encoded.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の符号形式を示す図、第2図は本発明の一
実施例による符号例を示す図、第3図A,b,cは本発
明の一実施例の動作を説明するための図、第4図は本発
明による符号を無記憶情報源に適用した場合の符号化効
率を示す図、第5図は本発明の一実施例による符号化装
置のプロツク図である。 100・・・・・・゛0″シンボルカウンタ、101・
・・・・・“1゛シンボルカウンタ、102・・・・・
・符号器。
FIG. 1 is a diagram showing a conventional code format, FIG. 2 is a diagram showing an example of a code according to an embodiment of the present invention, and FIGS. 3A, b, and c are diagrams for explaining the operation of an embodiment of the present invention. FIG. 4 is a diagram showing encoding efficiency when the code according to the present invention is applied to a memoryless information source, and FIG. 5 is a block diagram of an encoding apparatus according to an embodiment of the present invention. 100...゛0'' symbol counter, 101...
・・・・・・“1゛Symbol counter, 102...
・Encoder.

Claims (1)

【特許請求の範囲】[Claims] 1 発生頻度の高い優勢シンボルの出現確率Pと発生頻
度の低い劣勢シンボルの出現確率(1−P)とが近接し
ている情報源からの出力シンボルに符号語を与える符号
化装置において、出力シンボル系列を、優勢シンボルが
合計(n+1)個(n:P^n^+^1>(1−P)^
nを満たす正整数)もしくは、劣勢シンボルが合計n個
出現する毎に区切り、該区切られたパターンが、優勢シ
ンボルのみからなる時はこれにnビットの符号語を与え
、劣勢シンボルのみからなる時は(n+1)ビットの符
号語を与え、両シンボルからなる時は該パターンと同じ
ビット数の符号語を与えることを特徴とする符号化装置
1. In an encoding device that gives a code word to an output symbol from an information source in which the appearance probability P of a frequently occurring dominant symbol and the appearance probability (1-P) of a less frequently occurring symbol are close to each other, the output symbol The sequence has a total of (n+1) dominant symbols (n:P^n^+^1>(1-P)^
(a positive integer that satisfies n) or each time a total of n inferior symbols appear, and when the divided pattern consists of only dominant symbols, an n-bit code word is given to it, and when it consists of only inferior symbols, it is given an n-bit code word. An encoding device characterized in that it gives a code word of (n+1) bits, and when it consists of both symbols, it gives a code word of the same number of bits as the pattern.
JP52015858A 1977-02-15 1977-02-15 encoding device Expired JPS5921235B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52015858A JPS5921235B2 (en) 1977-02-15 1977-02-15 encoding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52015858A JPS5921235B2 (en) 1977-02-15 1977-02-15 encoding device

Publications (2)

Publication Number Publication Date
JPS53100713A JPS53100713A (en) 1978-09-02
JPS5921235B2 true JPS5921235B2 (en) 1984-05-18

Family

ID=11900490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52015858A Expired JPS5921235B2 (en) 1977-02-15 1977-02-15 encoding device

Country Status (1)

Country Link
JP (1) JPS5921235B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155838U (en) * 1984-09-18 1986-04-15
JPH0474048U (en) * 1990-11-08 1992-06-29
JPH0451625Y2 (en) * 1987-12-23 1992-12-04
JPH0546320U (en) * 1991-03-28 1993-06-22 道代 吉永 OA system desk structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155838U (en) * 1984-09-18 1986-04-15
JPH0451625Y2 (en) * 1987-12-23 1992-12-04
JPH0474048U (en) * 1990-11-08 1992-06-29
JPH0546320U (en) * 1991-03-28 1993-06-22 道代 吉永 OA system desk structure

Also Published As

Publication number Publication date
JPS53100713A (en) 1978-09-02

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