KR20010044876A - Doulble locking delay locked loop clock generation device using ring oscillator - Google Patents

Abstract

PURPOSE: A device of generating a delay locked loop(DLL) clock for double locking using a ring oscillator is provided to reduce the size of the device, to produce fast the DLL clock having a small jitter, and to control the whole jitter only through a fine delay stage when noises occur. CONSTITUTION: In a block diagram of a delay locked loop(DLL) clock generator, a delay model(210) delays a clock(clk) by the difference between the clock(clk) and a data output signal and produces a delay model clock signal(clk_d). A controller(230) responds to the clock signal(clk), an enable signal(en) and the delay model clock signal(clk_d). The controller(230) produces a control signal and an internal clock signal to produce a delay locked loop clock signal(dll_clk). A first delay stage(250) delays the clock(clk) roughly responding to the control signal and the internal clock signal. A second delay stage(270) delays finely the signal delayed by the first delay stage(250) and produces the delay locked loop clock signal(dll_clk).

Description

Double locking delay locked loop clock generation device using ring oscillator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a delay locked loop (DLL).

Generally, clock generation for compensating clock and data or skew between an external clock and an internal clock in a memory device operating at a high speed such as double data rate (DDR) synchronous DRAM (SDRAM). Use a delay lock loop as a device.

A timing diagram for explaining the principle of the delay locked loop of FIG. 1 will be described.

When the time difference of td1 is shown between the clock signal clk and the output data dout, the clock signal and the output data are synchronized using the internal clock signal dll_clk which delays the clock signal by td2.

Digital delay lock loops arrange dozens of unit delay elements in series to extract the appropriate output. To increase the resolution, the unit delay time should be minimized.

However, as the unit delay time decreases, a larger number of unit delay elements are required to form the entire delay locked loop, thereby increasing the area and power consumption.

In order to make up for this drawback, a method of going through the two stages of the course delay stage (corse delay stage) which delays the overall delay process by increasing the delay time and the fine delay stage which is delayed by the minute delay element is described. In this case, however, the jitter of the entire delay loop in the presence of noise eventually becomes the same as that of the course delay with a large delay time, resulting in very large jitter.

The present invention is to solve the problems of the prior art as described above, the present invention made as described above, the delayed fixed loop clock generating apparatus that reduces the total area while generating a delay fixed loop clock signal with a small jitter within a short time The purpose is to implement it.

In addition, another object of the present invention is to implement a delay locked loop clock generation apparatus such that the entire jitter is continuously controlled only by the fine delay unit even when noise is generated.

1 is a timing diagram for explaining the principle of the delay lock loop of FIG.

2 is a block diagram of a delay locked loop according to an embodiment of the present invention.

Figure 3 is a detailed circuit diagram of the primary delay unit according to an embodiment of the present invention.

4 is a detailed circuit diagram of a shift register according to an embodiment of the present invention.

5 to 7 are operation timing diagrams of the primary delay unit according to an embodiment of the present invention.

8 is a detailed circuit diagram of a secondary delay unit according to an embodiment of the present invention.

9 is a detailed circuit diagram of a flag register according to an embodiment of the present invention.

10A to 10C are timing diagrams and process diagrams of an operation of a second delay measuring unit according to an exemplary embodiment of the present invention.

11 is an operation timing diagram of a secondary delay unit according to an embodiment of the present invention.

12 is an overall operation timing diagram according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

250: 1st delay

251: first delay measurement unit 252: first replication delay unit

270: second delay

271: second delay measurement unit 272: second replication delay unit

According to an aspect of the present invention, there is provided a delay locked loop clock generation apparatus comprising: a delay model for generating a delay clock signal delaying a clock signal by a time difference between the clock signal and a data output signal; A control unit for generating a control signal and a ring oscillator signal for generating a delay locked loop clock signal in response to the clock signal, the enable signal, and the delay clock signal; A primary delay unit configured to generate a primary clock delay signal in which jitter is determined by a period of the ring oscillator in response to the control signal and the ring oscillator signal, and approximately delays the clock signal in a short time; And a secondary delay unit configured to finely delay a clock signal approximately delayed by the primary delay unit in response to the control signal and the internal clock signal to generate the delay locked loop clock signal. Jitter is determined by the unit fine delay element of the secondary delay unit.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a block diagram of a delay locked loop according to an embodiment of the present invention.

Referring to FIG. 2, the delay lock loop includes a delay model 210 for generating a delay model clock signal clk_d that delays a clock signal clk by a time difference between the clock signal and the data output signal, and the clock signal. a control unit 230 for generating a control signal for generating a delay locked loop clock signal dll_clk and an internal clock signal in response to a clk, an enable signal en, and the delayed model clock signal clk_d; A primary delay unit 250 delaying the clock signal in response to a control signal and an internal clock signal, and a clock signal approximately delayed in the primary delay unit 250 in response to the control signal and the internal clock signal. The second delay unit 270 generates a delay locked loop clock signal dll_clk by finely delaying the delay loop.

The primary delay unit 250 is composed of a first delay measurement unit 251 and a first delay replica unit 252, the secondary delay unit 270 is a second delay measurement unit 271 and a second delay replica It consists of a part 272, the detailed configuration of which will be described with reference to FIG.

3 is a detailed circuit diagram of the primary delay unit 250 according to an embodiment of the present invention.

Referring to FIG. 3, the primary delay unit 250 responds to the measurement oscillation signal m_osc, the secondary clock signal clk2, and the shift signal shift by the secondary delay clock signal / clk_d2 and the secondary delay clock. Delay measurement in the art, the output signal and the replica signal (/ replica) of the first delay measuring unit 251 and the first delay measuring unit 251 for storing the delayed signal (/ clk_d2) at a predetermined period, respectively It is used to mean the same as the oscillator signal used in the terminology, which is also commonly used as a mirror signal) and the copy oscillation signal (r_osc) in response to the bypass signal (subpass) and the subflag signal (/ falg) and the primary delay clock. The first delay copy unit 252 generates a signal sub_clk and a replication initialization signal rep_rst.

The first delay measuring unit 251 is a first to fifth measurement node N31, N32, N33, N34, the second delay clock signal / clk_d2 is delivered in step in response to the measurement oscillation signal (m_osc) First through fifth transfer control units 311, 312,..., 315 for controlling transmission to N35, the second delayed clock signal and the first through fourth measurement node signals, respectively; To the first to fourth input transfer units 321, 322, 323, and 324 to the transfer control unit 312, 313, 314, and 315, respectively, to the secondary clock signal clk2 and the shift signal. The first to fifth measurement in response to the bypass shift register 330 for receiving and storing the secondary delay clock signal / clk_d2 in response to the secondary clock signal clk2 and the shift signal. The first through fifth shift registers 331, 332,..., 335 storing the signals of the nodes N31, N32, N33, N34, and N35.

The first delay replication unit 252 is enabled at a high frequency in response to the positive / negative output signal of the bypass shift register 330 and the negative output signal of the first shift register 331, so as to provide a delay locked loop clock. Copying in response to the bypass signal generator 340 for generating a bypass signal for controlling generation and the positive / negative output signals of the first to fifth shift registers 331, 332,..., 335. A response to the delay determination unit 350 for generating the first to fifth determination nodes I1, I2, I3, I4, and I5 signals to determine the delay amount, and the second determination node I2 and the fourth determination node I4 signals. A flag signal generator 341 which generates the subflag signal / flag, the first to fifth determination nodes I1, I2, I3, I4, and I5, the replication oscillation signal r_osc, and the The replication delay time transmitted through the delay determining unit 350 in response to a replication signal (/ replica) is the first to fifth replication node R3. First through fifth replication transfer units 371, 372, ..., 375 delayed through 1, R32, R33, R34, and R35, and the first through fifth replication in response to the replication oscillation signal r_osc. First to fifth replication transfer control units 361, 362, ..., 365 for controlling the transfer of nodes R31, R32, R33, R34, and R35, the replication signal / replica and the replication oscillation signal r_osc In response to the first delayed replication output unit 380 for generating the primary delayed clock signal (sub_clk), and the replication initialization signal in response to the bypass signal (bypass) and the primary delayed clock signal (sub_clk) and a duplicate initialization signal generation unit 390 for generating rep_rst.

The delay determining unit 350 generates a signal of the first determining node I1 in response to the positive output signal of the first shift register 331 and the negative output signal of the second shift register 332. And a NOR gate NOR32 which generates a signal of the second determination node I2 in response to a positive output signal of the second shift register 332 and a negative output signal of the third shift register 333, respectively. NOR gates NOR33, NOR34, and NOR35 for generating the third to fifth determination nodes I3, I4, and I5 signals.

The first delayed replication output unit 380 is an NOR gate NOR36 for inputting the second replication node R32 and the replica signal / replica, an output signal of the subflag signal / flag, and the NOR gate NOR36. A NAND gate ND31 for generating a signal of the node R30 in response thereto, a transfer control unit 381 for controlling the transmission of the signal of the node R30 to generate a signal of the node R301, an inverter INV31 for inverting the duplicated signal, A PMOS transistor PM31 that receives an output signal of the inverter INV31 through a gate and delivers a supply power to a node R302 through a source-drain path, and the primary delay clock signal sub_clk in response to signals of the node R301 and the node R302. It consists of a NAND gate ND32.

4 is a detailed circuit diagram of a shift register according to an embodiment of the present invention.

Referring to FIG. 4, the shift register includes an input unit 410 for controlling input of an input signal in in response to the secondary clock signal clk2, and data input through the input unit 410 is stored. A storage unit 430 and an output for outputting the input signal in stored in the latch 430 as a positive output signal out and an inverted sub output signal / out in response to the shift signal; It is made of a portion 450.

The input unit 410 transmits an inverter INV41 for inverting the input signal in, an inverter INV42 for inverting the secondary clock signal clk2, and an output signal of the inverter INV41 in response to the secondary clock signal. It consists of a passgate P41 which controls what happens. The output unit 430 includes an inverter INV43 for inverting the shift signal, a passgate P42 for controlling the output signal of the storage unit 430 in response to the shift signal, and the positive output signal. and a latch 451 which inverts and stores (out) to generate the sub output signal.

8 is a detailed circuit diagram of the secondary delay unit 270 according to an embodiment of the present invention.

Referring to FIG. 8, the secondary delay unit 270 may finely respond to the subflag signal / flag, the secondary clock signal clk2, the shift signal, and the measurement oscillation signal m_osc. A delay delay loop clock signal dll_clk by delaying the second delay measurement unit 271 and the first delay clock signal sub_clk for the minute delay time obtained by the second delay measurement unit 271. It consists of a second delay replication unit 272 to generate a.

The second delay measurement unit 271 is a delay node signal a1, b1, c1, ... which delays the measurement oscillation signal finely. The unit delay elements 831, 832,..., And the positive / subflag signals flag and / flag and the secondary clock signal clk2 and the shift are measured in response to the plurality of unit delay elements 831 and 832. An oscillation signal m_osc and the delay node signals a1, b1, c1,... A plurality of flag registers 811, 812,..., And delay information nodes N81, a2, b2, c2,..., Having a delay information amount in response to the plurality of flag registers 811, 812,. The delay measurement output unit 820 is generated.

The second delayed replica unit 272 performs the second delayed clock signal sub_clk and the delay information nodes N81, a2, b2, c2,... The delay replication loop dll_clk is received at the final stage in response to the delay replication input unit 840 which determines the amount of replication delay, and the output signal of the delay replication input unit and the output signal of the other fine unit replication delay element. A plurality of micro-unit replication delay elements 851, 852, 853, ... are generated.

9 is a detailed circuit diagram of a flag register according to an embodiment of the present invention.

Referring to FIG. 9, the flag register converts the positive output signal out or the sub output signal / out in response to the shift register of FIG. 4 and the positive / subflag signals (flag and / flag). f_out), an output selector 900 for selectively outputting.

The output selector 900 receives the subflag signal / flag through a gate and transmits the positive output signal out to the flag output signal f_out through a source-drain path, and a PMOS transistor PM91; An NMOS transistor NM91 that receives the positive flag output signal through a gate and transmits the positive output signal to the flag output signal through a source-drain path; and receives the positive flag output signal through a gate and source-drain A PMOS transistor PM92 which transfers the sub output signal / out to the flag output signal through a path, and receives the sub flag output signal through a gate to convert the sub output signal into the flag output signal through a source-drain path. It is composed of NMOS transistor NM92 which transmits.

5 to 7 are timing diagrams of the primary delay unit of FIG. 5, FIGS. 10B and 10C are diagrams illustrating a transfer process block diagram of the second delay unit, and a timing diagram of the secondary delay unit of FIG. The operation will be described with reference to a gram and an overall timing diagram of the operation according to an embodiment of the present invention of FIG.

First, the primary delay unit 250 uses a shift register as a unit delay element, and in response to the output of the measurement oscillation signal m_osc which is an output signal of a ring oscillator, the first delay measurement unit 251. Shifts the logic "low" to the left by a falling edge input through the secondary delay clock signal / clk_d2. The transferred logic "low" is shift registers 331 and 332 connected to each stage. ,…).

The shift register accepts and stores an input only while the secondary clock signal clk2 is "high", and outputs it while the shift signal is "high".

The timing skew td2 between the clock signal clk and the delay clock signal clk_d to be measured by the first delay measuring unit is the secondary clock at the polling edge of the secondary delay clock signal / clk_d2 as shown in FIG. 5. This is the interval between polling edges of the signal clk2.

While the secondary clock signal clk2 is "low L, the oscillator is disabled, and while the secondary delay clock signal / clk_d2 is" high, "the measurement nodes N31, N32, N33, ... are" high. " Is reset to ".

When the secondary clock signal clk2 becomes "high", the shift register can accept an input, and when the secondary delay clock signal falls to "low", it is first stored in the bypass shift register, and the measurement oscillation is performed. In response to the signal m_osc, the " low " signal of the secondary delay clock signal is supplied to the measurement nodes N31, N32,... Is delivered to. At the same time, the "low" signal is also stored in the shift registers 331, 332, ....

As shown in the timing diagram of FIG. 5, when the "low" signal is transmitted to the fifth measurement node N35 and the secondary clock signal clk2 is disabled, the "low" signal is stored up to the fifth shift register 335. . As a result, only the fifth determination node I5 becomes "high" and the first to fourth determination nodes I1, I2, I3, and I4 become "low", and the subflag signal / flag becomes "low."

As shown in the timing diagram of FIG. 6, when the replica signal / replica is activated "low", the replication oscillation signal r_osc is toggled so that the logic "high" signal of the fifth determination node I5 is "high". The reset first to fifth replication nodes transmit logic "low" signals in the order of R35, R34, R33, R32, and R31.

Since the subflag signal / flag is " low ", the node R30 becomes " high " and the node R301 remains " high " and the signal is transmitted by the first replication node R31 transmitted through the node R302. The primary delay clock signal sub_clk is activated "high" after the fifth transition of the copy oscillation signal r_osc.

That is, the approximate delay time obtained by the output signal of the ring oscillator in the primary delay unit 250 is the time required for the fifth transition of the ring oscillator, and the resolution of the primary delay unit is determined by the cycle of the ring oscillator.

As described above, the delay delay clock signal dll_clk is generated by slightly delaying the delay delay unit 270 after obtaining the delay time in the primary delay unit 250.

Looking at the flag register prior to the description of the secondary delay unit 270, the flag register is a flag register output unit 900 is added to the shift register, when the sub-flag signal / flag is activated A signal identical to the received signal is output, and when the positive flag signal is activated, a signal opposite to the input signal is output.

In the situation shown in FIG. 10A, first, when the fifth transition is recognized by the primary delay unit 250, the subflag signal / flag is activated as "low" so that the same signal as that of the input signal is input in the flag register. Is output. The second clock signal is disabled just before the signal due to the fifth transition is propagated so that the node a1 has not yet received the "high" signal of the fifth transition, so that only the node N81 signal is "high" and the remaining node a2 , b2, c2,... Becomes " low " so that locking occurs at the node N81.

FIG. 10C illustrates a case in which the fifth transition is not recognized by the primary delay unit. The subflag signal is "high" and the flag register outputs the opposite signal. Thus, only node h2 is "high" and the remaining nodes are "low", so locking occurs at h2.

In Fig. 11, it can be seen that locking occurs at nodes N81 and h2, which is caused by the fact that the fifth transition is recognized or not recognized, which is the time required for the transition to accept the input from the shift register. can actually be caused by noise when it is not larger than the margin. In other words, it can happen when the shift register has secured the margin necessary to accept the input due to noise.

However, even in this situation, the jitter of the entire delay locked loop is determined by the micro-unit delay element of the secondary delay portion, not the primary delay portion.

Referring to the overall operation timing diagram of FIG. 12, since the fifth transition is not recognized, the first delay clock signal sub_clk also comes from the fourth transition and the fifth transition of the replication oscillation signal. However, as the locking position of the secondary delay portion changes with the flag signal, it can be seen that the final delay locked loop clock remains td1 ahead of the clock signal.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention made as described above implements a delay locked loop clock generating apparatus which reduces the total area while generating a delay locked loop clock signal having a small jitter within a short time.

Claims (13)

In the delay locked loop generating device, A delay model for generating a delay clock signal delaying a clock signal by a time difference between the clock signal and the data output signal; A control unit for generating a control signal and a ring oscillator signal for generating a delay locked loop clock signal in response to the clock signal, the enable signal, and the delay clock signal; A primary delay unit configured to generate a primary clock delay signal in which jitter is determined by a period of the ring oscillator in response to the control signal and the ring oscillator signal, and approximately delays the clock signal in a short time; And A second delay unit configured to generate the delay locked loop clock signal by finely delaying a clock signal approximately delayed by the primary delay unit in response to the control signal and the internal clock signal, And the jitter of the delay locked loop clock signal is determined by a unit fine delay device of the secondary delay unit. The method of claim 1, The first delay portion, A first delay measuring unit for storing the second delayed clock signal and the delayed signal of the secondary delayed clock signal at regular intervals in response to the measurement oscillation signal, the secondary clock signal, and the shift signal; A first delay replication unit configured to generate a bypass signal, a subflag signal, the first delay clock signal, and a replication initialization signal in response to the output signal, the replication signal, and the replication oscillation signal of the first delay measurement unit; Delay fixed loop clock generating device comprising a. The method of claim 2, The first delay measuring unit, A plurality of transfer control units which control the second delayed clock signal to be transferred step by step in response to the measurement oscillation signal and transmitted as a plurality of measurement node signals; A plurality of input transfer units for combining the secondary delay clock signal and the plurality of measurement node signals, respectively, and transmitting the combined signals to the plurality of transfer control units; A bypass shift register configured to receive and store the secondary delay clock signal in response to the secondary clock signal and the shift signal; And A plurality of shift registers for storing the plurality of measurement node signals in response to the secondary clock signal and the shift signal; Delay fixed loop clock generating device comprising a. The method of claim 3, The shift register, An input unit for controlling input of an input signal in response to the secondary clock signal; A storage unit for storing data input through the input unit; An output unit configured to output the input signal stored in the storage unit as a positive output signal and an inverted sub output signal in response to the shift signal Delay fixed loop clock generating device comprising a. The method of claim 4, wherein The input unit, A first inverter for inverting the input signal; A second inverter for inverting the secondary clock signal; A first passgate that controls the output signal of the first inverter to be transmitted in response to the secondary clock signal Delay fixed loop clock generating device comprising a. The method of claim 4, wherein The output unit, A third inverter for inverting the shift signal; A second pass gate controlling the output signal of the storage unit in response to the shift signal; A latch configured to invert and store the positive output signal to generate the sub output signal Delay fixed loop clock generating device comprising a. The method of claim 2, The first delay replication unit, A bypass signal generator configured to generate a bypass signal that is enabled at a high frequency and controls generation of a delay locked loop clock in response to the positive / negative output signal of the bypass shift register and the negative output signal of the first shift register; A delay determination unit generating a plurality of determination node signals for determining a delay amount to be copied in response to the positive / negative output signals of the plurality of shift registers; A flag signal generator configured to generate the subflag signal in response to the plurality of determination node signals; A plurality of copy transfer units for delaying the copy delay time transmitted through the delay determining unit in response to the plurality of determination node signals, the copy oscillation signal, and the copy signal through a plurality of copy nodes; A plurality of copy transfer controllers controlling the transmission of the plurality of copy node signals in response to the copy oscillation signal; A first delay copy output unit configured to generate the primary delay clock signal in response to the copy signal and the copy oscillation signal; A duplicate initialization signal generator for generating the duplicate initialization signal in response to the bypass signal and the primary delay clock signal. Delay fixed loop clock generating device comprising a. The method of claim 7, wherein The first delay replication output unit, A second replication node, which is an output signal of a second replication transmission control unit, and a NOR gate as an input of the replication signal; A first NAND gate configured to receive the sub-flag signal and an output signal of the NOR gate; A transfer control unit controlling the transfer of the output signal of the first NAND gate to a first output node; A PMOS transistor receiving the copy signal inverted by the gate and delivering a supply power to a second output node through a source-drain path; A second NAND gate generating the primary delay clock signal in response to the signals of the first output node and the second output node; Delay fixed loop clock generating device comprising a. The method of claim 1, The secondary delay unit, A second delay measuring unit measuring a time to finely delay in response to the subflag signal, the secondary clock signal, the shift signal, and the measurement oscillation signal m_osc; A second delay replication unit generating the delay locked loop clock signal by delaying the first delay clock signal for a fine delay time obtained by the second delay measurement unit; Delay fixed loop clock generating device comprising a. The method of claim 9, The second delay measuring unit, A plurality of unit delay elements for generating a plurality of delay node signals in which the measurement oscillation signal is finely delayed; A plurality of flag registers respectively storing the measurement oscillation signal and the plurality of delayed node signals in response to the positive / subflag signal, the secondary clock signal, and the shift signal; A delay measurement output unit for generating a plurality of delay information node signals having a delay information amount in response to output signals of the plurality of flag registers Delay fixed loop clock generating device comprising a. The method of claim 10, The flag register, The shift register; An output selector for selectively outputting the positive output signal or the sub output signal of the shift register as a flag output signal in response to a positive / sub flag signal; Delay fixed loop clock generating device comprising a. The method of claim 11, The output selector, A first PMOS transistor receiving the sub-flag signal through a gate and transferring the positive output signal to the flag output signal through a source-drain path; A first NMOS transistor receiving the positive flag output signal through a gate and transferring the positive output signal to the flag output signal through a source-drain path; A second PMOS transistor receiving the positive flag output signal through a gate and transferring the sub-output signal to the flag output signal through a source-drain path; A second NMOS transistor receiving the sub-flag output signal through a gate and transferring the sub-output signal to the flag output signal through a source-drain path; Delay fixed loop clock generating device comprising a. The method of claim 9, The second delay replica unit, A delay replication input unit configured to receive the secondary delay clock signal and the plurality of delay information node signals and determine a copy delay amount; A plurality of fine unit replication delay elements generating the delay locked loop clock signal at a final stage in response to an output signal of the delay replication input unit and an output signal of another fine unit replication delay element. Delay fixed loop clock generating device comprising a.