TW508593B - Delay locked loop for use in synchronous dynamic random access memory - Google Patents

Abstract

A delay locked loop (DLL) is used to compensate for a skew in a synchronous dynamic random access memory. The delay locked loop includes: a delay model for delaying an external clock signal by the skew to generate a delayed clock signal; a signal generation unit, in response to the external clock signal and the delayed clock signal, for generating control signals; a first delay unit, in response to the control signals, for delaying the delayed control signal to generate a first DLL clock signal, wherein the first delay unit has a large unit delay; and a second delay unit, in response to the control signals, for delaying the first DLL clock signal to generate a second DLL clock signal, wherein the second delay means has a small unit delay.

Description

V. Description of the invention (1) I. The invention relates to a semiconductor integrated circuit; more specifically, it relates to a delay-locked loop (DLL) used in synchronous dynamic random access memory, which can Obtain a fast lock time and reduced sea movement. Prior art description In order to achieve high-speed operation in semiconductor memory devices, synchronous memory access memory (SDRAM) 4DRAM has been developed to operate in synchronization with an external clock signal. SDRAM includes a single data rate (Sdr) sdram, a high speed (DDR) SDRAM, and the like. For i-2, when the data is output synchronously with the external clock signal, the skew between the external time, the Lixun number and the output data will occur. In _ΑΜ, it can be = one; lock loop (DLL) to compensate for the skew between the external clock signal and the output. The bell clock signal and the internal clock signal-the digital DLL is a combination of multiple unit delay elements to achieve: from = to increase the resolution, the unit delay time should be minimized. By the way, m-units require more unit delay elements. Therefore, — the power rate / the consumption rate and the size of the daily film will increase. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a gain-fast lock time and reduced jitter. According to an aspect of the present invention, it can provide a delay lock for accessing skew in memory :: to compensate synchronous dynamic random delay lock loop, which includes:

$ 5 页 508593 V. Description of the invention (2) Delay a delay model of an external clock signal to generate a delayed clock signal, a signal generating device in response to the external clock signal and the delayed clock signal to generate A control signal; a first delay device that delays the delayed control signal in response to the control signal to generate a first delay lock loop (DLL) clock signal, wherein the first delay device has a large unit delay; And a second delay device, in response to the control signal, to delay the first delay-locked loop (DLL) clock signal to generate a second delay-locked loop (DLL) clock signal, wherein the second delay device has a small Unit delay. The drawings are briefly described with reference to the drawings. FIG. 1 is a timing chart. FIG. 2 is a block diagram. FIG. 3 is a circuit diagram. FIG. 4 is a circuit diagram. FIG. 5 is a circuit diagram. The following examples will be used for reference, in which: to explain the principle of the DLL; to explain the DLL according to the present invention; to explain a first delay unit shown in FIG. 2; to explain a temporary storage shown in FIG. 3. _ Illustrate a second delay unit shown in FIG. 2; Illustrate a flagpole shown in FIG. 5 is crying temporarily; Figures 7 and 8 explain 1 when the ^ late unit shown in FIG. 3 is a sub-sequence diagram Figures: 1 to 1 illustrate the timing diagrams of the second delay unit shown in Figure 5 ', and Figure 12 illustrates the overall timing diagram of the DLL according to the present invention. Detailed description of the iLil embodiment Figure 1 is a timing diagram to explain the principle of the DLL. Here, the time period of the external clock signal CLK. ck

Page 6 V. Description of the invention (3) As shown, when the ^ is scrolled, the skew tdl of the synchronous output with the external clock signal CLK α at 2 2 will be caused. Skew t 蕻: internal clock signal tdl between? CLK and -output data Dout: = external clock signal The skew DLL-CLK is determined by the time t at which the internal clock signal first determines The clock signal CLK is delayed by a predetermined DLL clock signal according to (tk-tdl). Therefore Tsai. This internal clock signal DLL —CLK is called a data source D. The external clock signal is synchronized with the DLL clock signal, and once the input signal is 10 ut, the external clock signal CLK is synchronized. ^ Is a ^ block diagram illustrating a DLL according to the present invention. 270. The first delay early 60 and a second delay unit ▲ The delay model 210 delays an external clock signal CLK by a number between the external clock tongue it and CLK and '-屮 也 也 L + Μ AA M n, ^: _ Deflection tdl between ffi Beco to generate a delayed clock signal CLK_D. The signal generating unit 220 includes a control unit 230, a voltage-controlled oscillator (VCO) 240, and a mirror vc0 25.

The control unit 230 receives the external clock signal CLK and the delayed clock signals CLK-D to generate a control signal. The control signals include a control clock signal CLK2, a delayed control signal / CLK_D2, a response signal / REPLICA, and a response enable signal rep_EN. Here, the control clock signal CLK2 is enabled to a high level, from the first rising edge to the second rising edge of the external clock signal CLK, so that the control clock signal CLK2 has one or two time periods located on the external clock signal CLK.

508593 V. Description of the invention (4) period. Enable the delayed control signal / CLK_D2 to a low level, from the first rising edge to the second rising edge of the delayed clock signal CLK-D, such as-this makes the delayed control signal / CLK-D2 have one or two Time period that is twice the delayed clock signal CLK_D. The response enable signal REP-EN is used to activate the mirror VC0 250, and the response signal / REPLICA is a control signal used to hold a response oscillator signal R_〇Sc. The VCO 240 performs an oscillating operation to generate a measurement oscillating signal iosg in response to the control clock signal CLK2 to delay the control signal / CLK_D2. Measure ... The oscillating signal M-OSC is blocked, and the control clock signal CLK2 and the delayed control signal / CLK_D2 are enabled. The mirror VCO 250 performs an oscillating operation to generate a response oscillating signal R_sc to respond to the response signal / REPLICA and the response enable signal / REp_EN. In response to the Zhenying signal R-OSC was detained, at the same time the response signal / REpLICA and the response enable signal REP-EN were enabled. The first delay unit 260 has a large unit delay, and generally delays the external clock signal CLK in response to the control signal and generates a first DLL clock signal DLL_CLK1. The first delay unit 260 also includes a first delay measurement unit 261 and a first delay response unit m2. The second delay unit 270 has a small unit delay, and finely delays the first DLL clock signal DLL_CLK1 in response to the control signal and generates a first DLL% clock signal DLL_CLK2. The second delay unit 270 also includes a second delay measurement unit 271 and a second delay response unit 272. FIG. 3 is a circuit diagram illustrating the first delay unit shown in FIG. 2

508593 V. Description of the invention (5) 260 ° Referring to FIG. 3, the first delay measurement unit 261 shifts the low bit of the delayed control signal 1 / CLK-D2 to the measurement nodes N31 to N35 in response to the measurement oscillation signal, M-0SC . Then, the registers 331 to 335 store the shifted low levels of the measurement nodes N31 to N35 while controlling the clock signal CLK2 to be high. The low-order bits stored in the registers 331 to 335 are output to the first delay response unit 262 in response to the control clock signal CLK2 and the one-bit signal SHIFT. In the first delay, in the quantity unit 261, the plurality of first conversion control units 3j to 315 convert the low-order bits of the delayed control signal / CLK_D2 to the node to N35 in response to the measurement oscillation signal M_〇sc. In response to the delayed control signal / CLK-D2 logic combination signal and the voltage levels on the measurement nodes N31 to N35, multiple second conversion control orders 7L321 to 324 convert the lower bits of the measurement nodes N31 to N35 to change control respectively Units 311 to 315. The registers 331 to 335 store the low bits of the measurement nodes N3! To N35 in response to the delayed control signal / CLK-D2 and the shift control signal shift. ~ ”The square way register 330 stores the delayed control signal / CLK_D 2 power ~ presses the level to respond to the delayed control signal / CLK —D2 and the displacement control signal SHI FT. In the first delayed response unit In 2 62, a bypass signal generating unit 34 is enabled, and responds to the output signal of the bypass register 33 and the output signal of the register 331 and generates a bypass signal BYPASS. In response to the registers 331 to 335 Non-inverting / inverting signal, one delay decision

Page 9 508593 V. Description of the invention (6) The fixed unit 350 generates the lock signals η to 15 to determine the magnitude of the delay to be responded to. A plurality of third conversion control units 371 to 375 convert a predetermined voltage level to The response nodes r 3 1 to R 3 5 respond to the lock signals 11 to I 5, the response signal / REPLICA, and the oscillation signal R_〇sc. The plurality of fourth conversion control units 361 to 365 convert each output signal of the third conversion control units 371 to 375 to the next conversion control unit. An output unit 380 outputs the first DLL clock signal DLL_CLK1 to respond to the retalination signal / REPLICA and the response oscillation signal R_〇sc. FIG. 4 is a circuit diagram illustrating the register shown in FIG. 3. Referring to FIG. 4, each of the registers 331 to 335 includes: a first transmission gate TG41 to transmit the voltage level of each measurement node [N in response to the control clock signal CLK2; — a first flash lock 430 to store the first transmission The output signal of the gate TG41; a second transmission gate TG42 to transmit the output signal of the first interlock 43 () in response to the shift control signal SHIFT; and a second latch 450 to store the output signal of the second transmission gate TG4 2 and Output a non-inverting signal OUT and one inversion; phase signal / OUT. 5 is a circuit diagram illustrating the second delay unit -270 shown in FIG. 2. Referring to FIG. 5, the second delay unit 270 includes a second delay measurement unit 271 to measure a time to be finely delayed, and a second The delay response unit 272 delays the first DLL clock DLL_CLK1 by the measured time to generate a second DLL clock DLL_CLK2. The second delay measurement unit 2 71 includes a plurality of unit delay elements 831 to 834

Page 10 508593 V. Description of the invention (7) Delayed measurement of oscillation signals M — 0sc to produce delayed measurement oscillation signals A1, B1, C1, and D1; multiple flag registers 511 to 514 to store Delayed measurement oscillation signals A1, B1, C1 * D1 in response to the flag signal ", an inverted flag signal / FLAG, a control clock signal CLK2 and a displacement control signal SHIFT; and an output unit 820 to receive The output signals of the flag registers 511 to 514 are used to generate the node signal 1 ′ 232, 62, (3: the first delay response unit 272 logically combines the node signals ιΙΝ2, A2, B2, C3 and the first DLL clock signal DLL_CLK1 to generate a second DLL clock signal DLL_CLK2. Figure 6 is a circuit diagram illustrating the flag register shown in Figure 5. Referring to Figure 6, the parent flag register includes a first transfer The gate% 6 丨 sends a delayed measurement oscillation signal 丨 the inverted signal of N to respond to the control ¥ 钟 钟 号 CLK2;-the first latch 630 to store the signal of the first transmission gate TG61; The second transmission gate TG62 responded by transmitting the output signal of the first latch 630 Displacement control signal SHIFT;-The second latch 650 stores the output signal of the second transmission gate TG 62; a third transmission gate TG63 outputs the output signal of the second transmission chamber TG62 in response to the non-inverting / inverting flag The signals ^ ... and 1LAG; and a fourth transmission gate TG64a outputs the output of the second latch 650-Λ in response to the non-inverted / inverted flag signals FLAG and / FLAG. Right inverted flag signal / When FLAG is activated, the flag register outputs a delayed measurement oscillation signal, and if the flag signal is "enabled", the flag register outputs a delayed inverse signal of the amount of oscillation signal. [Invention]) The operation of LL will be described with reference to FIGS. 7 to 13.

Page 11 508593 V. Description of the invention (8) ----- Referring to Figure 7, when the control clock signal CLK2 and the delayed control signal / CLK_D2 are low and high, respectively, vc〇240 is turned off and the node To N35 is reset to a high position. "Then, when the control clock signal CLK2 and the delayed control signal / CLLD2 are a high bit and a low bit, respectively, the bypass register stores the delayed control signal / CLK — the low bit of D2 and the delayed control signal / The low level of CLK-D2 stomach was then shifted from measurement node N31 to measurement nodes 5 in response to the measurement oscillation signal 10SC. As a result, the registers 331 to 335 stored the shifted low position. ^ Assume that the control clock signal CLK2 is a high level At the same time, the low bit is shifted to the node N335, and the low bit is changed from the register 331 to the register 335. Therefore, 'only the lock signal 15 is high and the other lock signals 丨 丨' are "low." In addition, the inverted flag signal / FLAG goes low. Refer to Figure 8. If the response signal / replica is activated to a low position, the response oscillation signal R_0SC is blocked, so that the low position is subsequently switched from the response node R35 to the node R31. : Because the inverted flag signal / FLAG is a low bit, the node becomes a high bit, so that the first DLL · clock signal DLL_CLK responds to the oscillation signal — R-0SC is changed after the fifth conversion because of the voltage level of node R31 Was started. Fig. 9 illustrates the timing chart of the control signal CLK2 and the measurement oscillation signal M-osc, and Fig. 10 illustrates the second delay unit 27 0 in the first delay unit 26 (). Logical level in case of conversion. Referring to FIGS. 9 and 10, since the inverted flag signal / FLAG is activated to a low position, the flag registers 511 to 514 output a signal equal to the input signal. 508593

At this time, because the control clock is more than m ^ ^ ^ ^ ^ Yuli efl ^ CLK2 was turned off at the high position just after the fifth transition, and the ribs a 1 and 4 were held in the low position, while Only node IIN2 becomes up. That is, a lock is completed at the node M_IN2. A figure 11 illustrates the logical level of the second Yanbian army ’s opening 970 / Zan ϋ ^ ^ ^ η stealing, then early 270 in the case of the fifth delay of the first delay early 7L260 without confirming the measured oscillation signal M-0SC . Referring to FIG. 11, because the inverted flag signal is turned off to a high level, the flag register outputs a signal opposite to the input signal. Therefore, only "node 2" becomes high, and other nodes become low. That is, a lock is completed on section Η2. ·

Figure 12 illustrates the overall timing diagram of a DLL according to the present invention. Referring to FIG. 12, if the first delay unit 26 confirms the fifth transition of the measurement oscillation signal M-0SC, the first DLL clock signal DLL_CLK1 is generated on the fifth transition. At the same time, if the first delay unit 260 does not confirm the fifth transition of the measurement oscillation signal M-0SC, the first dll clock signal DLL_CLK1 is generated on the fourth transition. However, because the locked position is changed according to the flag signal FLAG, it is possible to obtain a final DLL clock signal, that is, the first: DLL clock signal DLL-CLK, which will be ahead of the external clock signal CLK skewed tdi.

Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will understand that different modifications, additions and deletions are possible without violating the scope and spirit of the invention, as disclosed in the scope of the attached patent of.

508593 Case No. 89127733 91 · f Modified diagram Brief description of component symbols 210 220 230 240 250 260 26 1 262 270 271 272 311-315 321-324 330 33 Bu 335 340 361-365 371-375 380 430 450 51 Bu 521 630 820 Delay model 831-834 Signal generation unit 11-15 Control unit R31-R35 Voltage controlled oscillator (VCO) TG41, TG61 Mirror VCO First delay unit First delay measurement unit First delay response unit Second delay unit Second Delay measurement unit second delay response unit first conversion control unit second conversion control unit bypass temporary storage | § register bypass signal generation unit fourth conversion control unit third conversion control unit output unit first latch second Latch flag register First latch output unit TG42, TG62 TG63 Unit delay element lock signal Copy node first transfer gate second transfer gate Third transfer gate

O: \ 67 \ 67432-9l0911.ptc Page 14

Claims (1)

508593 VI. Scope of Patent Application 1 · A delay-locked loop to compensate for skew in a synchronous dynamic random access memory, which includes: ~ A delay model for delaying an external clock signal by the skew to generate A delayed clock signal; A signal generating device responds to the external clock signal and the delayed clock signal to generate a control signal; a first delay device responds to the control signal to delay the external clock signal to generate a first delay-locked loop (DLL) clock signal , Where the first delay device has a large unit delay; and A second delay device responds to the control signal to delay the first delay-locked loop (DLL) clock signal to generate a second delay-locked loop (DLL) clock signal, wherein the second delay device has a small unit delay. 2. If the delay lock loop of item 1 of the patent application scope, the signal generating device includes: U control device 'response to an external clock signal and a delayed clock signal' to generate a control sfl signal ', where the control signal includes a control clock signal: 'A delayed control signal, a response signal, and a response enable signal, — A first voltage-controlled oscillation device responds to the control clock signal with a delayed control signal to generate a measurement oscillation signal; and a second voltage-controlled oscillation device responds to the response signal and the response enable signal. Generate a response Zhenying signal. 3. The delay-locked loop of item 2 in the scope of patent application, wherein the clock is controlled from one of the first rising edge to one of the second rising edge of the external clock signal 508593 VI. Scope of Patent Application Yuan was enabled to a high level. 4. The delay-locked loop of item 3 of the patent application range, wherein the delayed control signal is enabled to a low level from the first rising edge to a second rising edge of the delayed clock signal. 5. The delay-locked loop according to item 4 of the scope of patent application, wherein the first delay device includes: a delay measurement unit that responds to the measured low level of the control signal delayed by the displacement and stores the displaced low level; And a delayed response unit for generating the first DLL clock signal to respond to the response oscillation signal. 6. The delay-locked loop according to item 5 of the scope of patent application, wherein the delay measurement unit includes: a plurality of first conversion control units, which respond to the measurement oscillation signal to convert the low level of the delayed control signal to the measurement node; #Multiple second conversion control units, which respond to the logical combination signal of the delayed control signal and the voltage level of the measurement node, for converting the low level of the measurement node to the first conversion control unit; a bypass register, used The voltage level of the delayed control signal is stored in order to respond to the delayed control signal and a displacement control signal; and, a plurality of registers are used to store the low level of the measurement node in order to respond to the delayed control signal. Signal and the displacement control signal. \ For example, the delay lock loop of the 6th scope of the patent application, where each register includes: 〃 The second transmission gate is used to transmit the voltage level of each measurement node to Page 16 6. The patent application scope responds to the control clock signal; a first latch for a second transmission gate for the output signal of the special gate; the displacement control signal; and the first The output signal of the latch responds to a second latch and is used to store the second output signal. Ying Peizhi includes: The delay lock loop of ， where the delayed return bypass signal is generated, the output signal of the Tianlu register and the bypass signal are used to respond to the next delay decision-the output signal of the first register; the lock signal It is determined by waiting for the output signal of the response register 'to generate: Now the size of the delay to be responded is determined; multiple third conversion control units and mi ^ $ are used to respond to the lock signal, and the response signal should be processed. The pre-determined voltage is converted back to I f. Each of the second and fourth conversion control units is used to convert the output signal of the third conversion control unit to an adjacent conversion control unit; and an output unit is used to The first DLL clock signal is output to respond to the response signal JU and the response oscillation signal. — 9 · If the delay-locked loop of item 4 of the patent application scope, the second delay device in the middle includes: a delay measurement unit for measuring a time to be delayed; and ^ B a delay response unit for The first DLL clock signal is delayed by an amount of time to generate the second DLL clock signal. 1 0 · If the delay lock loop of item 9 of the patent application scope, Page 17 The measurement unit includes: multiple unit delay elements, delayed measurement oscillation signals; multiple flag registers to respond to control clock signals, signals; and delay measurement oscillation signals to generate and store delayed delay signals. Measure the oscillation signal, a flag signal and a displacement control signal. Μ st # 噃 ^^ is used to receive the output signal of the flag register to generate the " s, child and node signals logically and the first DLL clock. Signal group: 11 · If the delay lock loop of item 10 of the scope of patent application, each flag register of Lizhong includes: / 'A first transmission gate, which is used to transmit an inverted signal of a delayed test number in response to control Clock signal; Set Zhenhuang first latch, a second transmission gate displacement control signal; used to store the output signal of the first transmission gate; 'used to transmit the output signal of the first latch to respond ^ door lock The third transmission gate is used to store the output signal of the first transmission gate. The third transmission gate is used to output the output signal of the second transmission gate. The fourth transmission gate is used for outputting a second response flag signal u ^