KR20010039964A - Use of silicon germanium and other alloys as the replacement gate for the fabrication of mosfet - Google Patents

Abstract

PURPOSE: Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET is provided to manufacturing a MOSFET device wherein the source region and the drain region are formed before formation of the gate and allows the use of any type of gate dielectric material. CONSTITUTION: A method for fabricating a MOSFET structure on a substrate comprises the steps of: forming an island above a gate region in the substrate, island being formed of Si.sub.1-x Ge.sub.x, wherein x is in the range of about 0.05 to about 1.0; building a sidewall about island; forming a source region and a drain regions in the substrate; selectively removing the island without removing the sidewall, thereby leaving a void over the gate region; and filling the void with a gate structure.

Description

USE OF SILICON GERMANIUM AND OTHER ALLOYS AS THE REPLACEMENT GATE FOR THE FABRICATION OF MOSFET}

The present invention relates to a method of manufacturing an integrated circuit, in particular a method of manufacturing a MOSFET device formed using a substitution gate.

Methods of fabricating MOSFET semiconductors are known in the art. The structure is shown in US Pat. No. 4,702,792, which describes a technique for making small conductive channels.

The substitution or "cast" process is a good candidate for fabricating transistors with a wide selection of gate materials. However, in recent years, since process controllability becomes a problem, such a process is not widely used. A major obstacle in using a substitution gate process is the control of the gate critical dimensions during the gate substitution process.

Chatterjee et al. Describe a substitution gate process, in particular the use of polysilicon as a substitution gate material, in IEDM Tech Digest, page 777, 1998. A disadvantage of using polysilicon as a substitution gate material is the difficulty of removing polysilicon using a wet etching process that is selective for silicon dioxide.

Yagishita et al. Describe a substitution gate process in the literature "IEDM Tech Digest, page 785, 1998". Yagishita also describes the use of polysilicon as a substitution gate material.

US patent application Ser. No. 09 / 028,157, filed Feb. 23, 1998, to Evans et al. Describes the use of silicon nitride as a substitution gate material. Although using silicon nitride as the substitution gate material is effective, it is difficult to pattern the silicon nitride substitution gate using a dry etching process. In order to optimize dry silicon nitride, the etchant must be selective for both silicon and silicon dioxide.

Until now, silicon germanium and other Group IV-B element alloys have not been used as dummy or replacement gates in the manufacture of MOSFET devices.

It would be advantageous to have a method of fabricating a substitution gate MOSFET that improves the etching selectivity between the substitution gate material and adjacent materials used in spacers and other structures. Although these documents describe the manufacture of MOSFET devices, they do not provide the advantages of the present invention.

It is an object of the present invention to provide a method of manufacturing a MOSFET device in which a source region and a drain region are formed before gate formation.

It is still another object of the present invention to provide a MOSFET device that can be fabricated in both conventional silicon and silicon-on-insulator (SOI).

It is still another object of the present invention to provide a method of manufacturing a MOSFET device that can use any type of gate dielectric.

It is still another object of the present invention to provide a method of manufacturing a MOSFET device having a highly conductive material such as a refractory metal or copper as a gate electrode.

It is a further object of the present invention to provide a method for fabricating a MOSFET device characterized by obtaining the desired gate critical dimension due to the improved controllability of the etching process.

Accordingly, the method of the present invention comprises the steps of forming a similar alloy island or silicon germanium, preferably selected from Periodic Group IV-B elements, on the gate region in the substrate; Silicon oxide (representative example of a preferred alloy of Group IV-B elements used) setting oxide or nitride sidewalls around islands; Forming a source region and a drain region in the substrate; Removing silicon germanium islands without leaving sidewalls around the islands to leave voids on the gate region; And filling the voids with the gate structure by forming a gate dielectric on the gate region within the voids and filling the rest of the voids with the gate electrode material.

Removing the silicon germanium (or other Group IV-B alloy) preferably comprises a layer of non-islet material that allows the island's alloy to be removed without simultaneously removing the selectively dissolved or deposited non-island material layer. Depositing on portions and islands on the drain region. The non-islet material layer may be polysilicon when an elevated source / drain region is provided (polycrystalline silicon may be used by those skilled in the art), or silicon nitride or when a conventional supply / drain region is provided It may be a suitable dielectric such as silicon oxide. After filling the voids with the gate structure, it is preferable to planarize the upper surface of the structure by chemical mechanical polishing. In an embodiment of the invention wherein an elevated source / drain region is formed, depositing a metal layer on a top surface of the structure, and metallizing the structure to form electrodes in the source region, the gate region, and the drain region. It is desirable to.

1-12 illustrate successive steps for fabricating a MOSFET device in accordance with a first embodiment of the present invention having an elevated source / drain region.

13 illustrates an element on an SOI substrate.

FIG. 14 shows the device structure after deposition of the barrier layer in another embodiment of the present invention. FIG.

15 shows the structure of a finished device having a deposited barrier layer.

16 shows a completed structure with a gate barrier layer deposited on the SIMOX substrate.

17-22 illustrate successive steps for fabricating a MOSFET device in accordance with another embodiment of the present invention.

[Embodiment of the Invention]

Referring first to FIG. 1 of the accompanying drawings, the substrate is represented by "20" when it is a single crystal silicon substrate. As used herein, the term “substrate” or “silicon substrate” refers to a bulk silicon, single crystal substrate, or silicon on insulator (SOI) substrate, including a separation by implantation of OXygen (SIMOX) substrate. Substrate 20 is particularly provided to form electrically active and / or isolation regions suitable for the fabrication of devices described below. Pre-processing can be accomplished by conventional n-wall and / or p-wall confinement and separation; Trench separation as polysilicon or oxide refill: conventional fully grooved local oxidation (LOCOS); And / or SOI mesa structures formed by LOCOS or etching. These steps may be used alone or together. SOI substrates can be fabricated by injecting large amounts of oxygen into single crystal silicon followed by annealing to form SIMOX, bonded silicon wafers and etch backs, heteroepitaxial, and the like. An example of a SIMOX is to inject oxygen at about 200 keV with an oxygen content of 1-2 x 10 ¹⁸ cm ^-2 . The wafer is annealed at 1300 ° C to 1350 ° C for 4 to 10 hours. Buried oxide thickness is about 300 nm. As soon as the pre-processing is finished, the substrate can be planarized entirely by planarizing, ie, chemical mechanical polishing (CMP). An oxide layer 22 is formed on the substrate 20 to a thickness of about 5 to 30 nm (not shown in the figure).

The oxide layer 22 refers to the pad oxide layer 22 in the present invention. A layer of material that is an alloy of group IV-B elements of the periodic table is deposited on the oxide layer 22. Preferred examples of alloys of group IV-B elements are polycrystalline silicon germanium which is deposited to a thickness of about 150-500 nm by chemical vapor deposition (CVD). As described below, silicon germanium, which is used as a representative example of a suitable alloy of group IV-B elements, acts as an "island" material.

The silicon germanium layer is preferably represented by Si _1-x Ge _x , where x is 0.05-1.0, preferably 0.1-0.5. The silicon germanium alloy layer is formed of silicon germanium islands 24 in FIG. 1 by photolithography and anisotropic plasma etching processes of the deposited silicon germanium layer. The region of silicon germanium removed by etching is indicated by line 23 in FIG. Etching of the region 23 outside the island region 24 stops at the pad oxide layer 22. In other words, after the silicon germanium layer 23 is masked in the gate region, the remainder of the silicon germanium is etched to form islands 24. The pad oxide layer 22 outside the masked "island" region 24 may act as an etch stop in subsequent steps, but may be partially etched or completely removed during this etch process. In the embodiment of the present invention, the pad oxide layer 22 is not removed.

Silicon germanium islands 24 form a substitution “cast” to the gate electrode. In other words, silicon germanium islands 24 form a dielectric image that becomes a gate electrode. As described below, this image is preferably used as a pattern for forming a metal gate electrode or a gate electrode of another material without a separate photolithography step. For example, the image of island 24 may be converted to a deeply doped polysilicon or polysilicon germanium alloy material gate electrode.

This figure shows the formation of a MOSFET transistor that can be of n-channel or p-channel type. If both forms are formed simultaneously during the fabrication process, photoresist is used to mask the n-channel transistors during the p-LDD (Low Dose or Lightly Doped Drain) ion implantation process. The p-LDD regions 26 and 28 are formed by BF ₂ ion implantation or plasma doping, as shown in FIG. Preferred ion dose amounts are 5 to 50 x 10 ¹³ cm ^-2 , and BF ₂ ion energy is 10 keV to 80 keV. The ion energy is low enough that no ions are injected through the silicon germanium layer. Then, after the photoresist is stripped, a new photoresist is used to mask the p-channel transistor for n-LDD ion implantation. The n-LDD region is formed by injecting 5 to 50 x 10 ¹³ cm ^-2 of arsenic or phosphorus ion dose with an ion energy of 40 keV to 100 keV for arsenic and an ion energy of 10 keV to 60 keV for phosphorus. The transistor shown in the figure represents an n-channel or p-channel transistor.

An optional oxidation step is carried out to thicken the pad oxide 22 in the shape of a “bird beak” at the edge of the island, as shown at 30 and 32 in FIG. 2. The new beak can improve the breakdown voltage of the gate oxide at the edge of the gate electrode. The oxidation step is carried out by heating the structure of FIG. 1 in oxygen and thickening the pad oxide region 22 which is not covered by the "islands" 24 as is known. As shown in Figure 2, during this oxidation process, ions in the LDD region diffuse and extend beyond the length of the new beak. The silicon nitride layer 34 is deposited on the structure by an advanced process such as plasma-enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) to obtain the structure shown in FIG. In another embodiment, oxide may be used as the material for layer 34.

When silicon nitride is used for layer 34 (FIG. 2), the wafer is anisotropic nitride etched, leaving a thin layer of nitrides 36 and 38 around the sidewalls of silicon germanium as shown in FIG.

Referring to FIG. 4, a layer 4 of a material different from the alloy of group IV-B elements used in the island 24 is deposited over the structure of FIG. Since layer 40 (FIG. 4) must be different from the material of island 24, it is formed of a non-islet material to facilitate removal of the island without removing the material used in layer 40 at the same time. In the first embodiment of the present invention, layer 40 is preferably deposited polysilicon. Polysilicon layer 40 is deposited on the wafer, island sidewalls and source and drain regions on the alloy islands. Layer 40 is thicker than silicon germanium layer 24 by an amount "T". The layer 40 may be the first polysilicon layer 40. The structure is processed by CMP as shown in FIG. 5 to expose the silicon germanium island 24.

Photoresist mask 33 is used to cover the device active region. The polysilicon layer 40 in the field region 35 (shown diagonally in FIG. 6) is not covered by the resist. Any suitable portion of polysilicon layer 40 and substrate 20 is etched away to remove field region 35. Then, the resist layer 33 is removed. At this point, only the source region 26 and the drain region 28 of both the p-channel and n-channel transistors are covered with the polysilicon layer 40. The wafer is coated with an oxide layer (indicated by line 37 in FIG. 6) having a thickness greater than or equal to the depth of the oxide deposited in the field region 35. The oxide is planarized by CMP and stopped at the top surface of the polysilicon and silicon germanium layers. Highly selective slurries that remove oxides faster than polysilicon are preferred for this process. This separates the oxide region 41 as shown in FIGS. 7 and 8, and surrounds the polysilicon layer 40. Regions 41 insulate the devices from each other on the substrate. As shown in Figures 7 and 8, region 41 is present in other figures after the steps described in connection with Figures 5 and 6.

The next step is to implant source / drain ions into the polysilicon region 40 remaining in Figures 5-7. When p-channel and n-channel devices are fabricated and first implanted into the p-channel device, photoresist is applied to mask the n-channel transistors. In FIG. 5, BF ₂ ions are implanted into the p-channel source / drain region including the polysilicon region 40. Preferred ion dose amounts are 1.0 to 5.0x10 ¹⁵ cm ^-2 , and BF ₂ ion energy is 10 keV to 80 keV. The ion energy is low enough that no ions are injected into the channel region through the gate dielectric layer. Ion implantation forms raised p ⁺ source and p ⁺ drain regions for the p-channel transistor. The photoresist is removed and a new photoresist is used to mask the p-channel transistor for channel source / drain ion implantation.

The n-channel source / drain is formed by implanting arsenic (or phosphorus) ions at an ion dose of 1.0 to 5.0x10 ¹⁵ cm ^-2 , arsenic ion energy of 40 keV to 100 keV, or phosphorous energy of 10 keV to 60 keV. The masking resist is removed and the wafer is annealed in an inert gas atmosphere for 15 seconds to 60 minutes at about 800 ° C to 1100 ° C. The source and drain of the p-channel transistor are doped to p ⁺ , while the corresponding region of the n-channel transistor is doped to n ⁺ .

Referring to Figure 9, silicon germanium islands 24 are removed by any one of several methods, such as high selectivity wet etching. There are several types of wet etching processes that selectively remove silicon germanium on silicon, including a mixture of acetic acid, nitric acid, and HF, at least 100 to 1 for silicon and 1,000 to 1 for silicon dioxide. The selectivity to etch silicon germanium is shown. The mixture of NH ₄ OH, H ₂ O ₂ and water selectively etches silicon germanium at least five times faster than silicon. The mixture of H ₂ O ₂ , HF and water also selectively etches silicon germanium on silicon. All of these wet etching processes have the structure shown in FIG. Due to the high selectivity and pattern control possible while etching the silicon germanium islands 24, the critical dimensions of the gate, ie the length of the gate, can be adjusted. In other words, the inner sidewalls of the spacers 36 and 38 remain almost normally on the surface of the gate region during the present process so that the critical dimensions of the gate do not change during the manufacturing step. In the embodiment shown above, the gate has a critical dimension of 0.10 to 0.2 microns, preferably about 0.13 microns, which extends along the width of the gate region from region 26 to region 28. The portion of the completed transistor, which becomes the channel region 42 and where the island 24 is removed, is referred to as the void 45. The voids 45 are also called voids on the gate region.

Upon removal of the silicon germanium, the remainder of the original pad oxide 22 was exposed, shown only in line 22 in FIG. Although this oxide layer serves as the gate dielectric, the rest of the pad oxide is susceptible to contamination or damage after removal of the silicon germanium islands. Pad oxide 22 may act as a screen oxide for non-masked critical control implantation, contaminating pad oxide 22. Thus, pad oxide 22 is not desirable as a gate dielectric. Once the pad oxide 22 is removed, the channel region 42 is exposed, which necessitates placing a portion of the gate insulator thereon.

The simplest way to form a gate dielectric is to regrow the dielectric on the silicon exposed in the channel region 42, which re-thinks the edges and ultimately causes the device to have an undesirably low gate breakdown voltage. do. This effect can be reduced by the obvious design of the oxidation step of FIG. During the oxidation step, new beaks 30 and 32 are formed around the silicon germanium island to thicken the pad oxide at the edge of the gate. If the remaining pad oxide strips are carefully controlled, a so-called "toe" is formed at the bottom of the spacers 36 and 38 which offsets the edge thickness.

On the other hand, the gate dielectric may be formed in any deposition, silicon oxide having desirable properties such as high dielectric constant and / or high fracture strength, such as AlN, Al ₂ O ₃ , TiO ₂ , ZrO ₂ or Ta ₂ O ₅ Preferred is because other materials may be used. In addition, zirconium oxide and hafnium oxide compounds such as aluminum doped zirconium oxide, silicon doped zirconium oxide, hafnium oxide, aluminum doped hafnium oxide and silicon doped hafnium oxide may be used. In these cases, the formation of new beaks by the oxidation step is unnecessary, so this step can be omitted in the process. This material may be deposited by CVD, PVD or atomic layer deposition (ALD). The final goal is to form the gate dielectric layer 44 as shown in FIG. 10 regardless of the method used.

After forming the gate dielectric 44, gate electrode material 46 is deposited throughout the structure to obtain the structure shown in FIG. The deposition layer 46 may be made of polysilicon. However, materials other than polysilicon may be used to fill the voids and extend into the source, gate drain regions. Refractory metals such as tungsten (W), tantalum (Ta), platinum (Pt) or molybdenum (Mo), or highly conductive metals such as copper (Cu) are titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride ( It can be used with a barrier metal such as WN). In another embodiment, polysilicon germanium may be used to form the gate. When covering the structure with the selected material, the structure is globally planarized by CMP to remove the polysilicon layer 40 and the gate material layer 46 portion as well as the sidewall spacers 36 and 38 portion as shown in FIG. You get

Any salicide (self-matched silicide) process can be performed to minimize parasitic resistance of the gate, source and drain electrodes. As shown in Fig. 12, the silicide layers 52 and 54 may be formed by any modern process such as annealing. A problem with the prior art for salicide is that the gate can be shorted to the source and / or drain by the unetched metal remaining in the spacers 36 and 38. This problem is solved by the so-called "touch polish", a very short CMP step.

The device of Fig. 12 is in a state capable of conducting metallization for forming electrodes for source regions, gate regions, and drain regions in which electrodes are electrically connected to respective regions, as is well known to those skilled in the art. It is shown. This can be accomplished by conventional patterning and etch metallization, such as aluminum alloys. However, since the surface is entirely planarized, embedded metallization using copper and CMP can be easily performed.

As shown in FIG. 13, a structure on a SIMOX substrate having a bulk silicon layer 60 and an oxide layer 62 embedded therein is shown. The remaining structure is indicated by the same number as the above element.

14 and 15 show another embodiment of the invention in which a barrier layer is deposited in the voids 45 of FIG. The barrier layer 70 is preferably a suitable barrier material such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN) used with the copper gate electrode 73 deposited in the voids 45. Excess barrier material on the source and drain regions is removed by CMP, resulting in a natural self-alignment of the barrier material to the gate electrode 78. Figure 16 shows the embodiment of Figure 15 on a SIMOX substrate. The gate dielectric 44 of FIG. 16 is provided by suitable means, such as deposition of high dielectric constant materials, such as Ta ₂ O ₅ , TiO ₂ , ZrO _2, or HfO ₂ , which materials may be Si or Al, or other suitable dielectric material. Can be doped with material. Similar processes can be used to provide the gate dielectric 44 in the embodiment shown in FIG.

Group IV-B alloys such as SiSn can be used as dummy or replacement gates in the process. Similar processes can be used for silicon germanium in silicon tin alloy processes based on the similar chemistry of these materials. Their new dummy gate materials can also be used in the manufacture of other devices such as ferroelectric memories.

The above embodiment of the present invention uses an elevated source / drain structure, and the embodiments of Figs. 17-22 use a conventional source / drain structure. 17, 18, 19 and 20 represent the same steps as those of the first embodiment shown in Figs. 3, 4, 5 and 9, respectively, and like numerals denote like elements in all the above figures. In FIG. 17, after formation of the islands 24 and the sidewall spacers 36, 38, an implantation step is performed to provide a suitable p- or n-type dopant (depending on the conductivity type of the device being formed) of the substrate 20. Inject in. After suitable annealing is performed to activate the dopant, source and drain regions 100 and 102 are formed.

In this embodiment, the next step (Figure 18) is to deposit a dielectric layer 106, such as silicon dioxide, on the alloy islands, island sidewalls, and source and drain regions. Layer 106 is also referred to as a non-islet material or “first layer of dielectric material” deposited on the structure. In layer 40 of FIG. 4, layer 106 is thicker than silicon germanium (“island”) layer 24 by an amount “T” (see FIG. 4). The structure is processed by CMP to expose the silicon germanium island 24 as shown in FIG. In Fig. 19, the source / drain regions 100/102 are each covered by the silicon oxide layers 110/112. Field regions for device isolation may be formed as in FIGS. 6 to 8.

In this regard, the silicon germanium island 24 is removed by any suitable method to selectively remove the island 24 material, but by any suitable method that does not remove the sidewall spacers 36 and 38 or the silicon dioxide regions 110 and 112. do. There are several known wet etching processes that selectively remove silicon germanium on silicon dioxide or silicon nitride. As a result of the above removal, as shown in Fig. 20, the voids 45 are formed in the gate region or the channel region 42 of the device.

Formation of gate dielectric layer 44 (FIG. 21) and deposition of gate electrode material layer 46 in the embodiments of FIGS. 17-22 are the same as shown in FIG. Filling the void 45 with the gate structure occurs after planarizing the top surface of the structure to the level shown by line 118 in FIG. The planarization step is carried out by chemical mechanical polishing.

Finally, a second layer of dielectric 122 is deposited over the planarization structure. Holes 124, 126, 128 are formed through layer 122, with holes 126 extending to gate structure 130, holes 124, 128 passing through first dielectric layer 110, 112, and source and drain regions 100, 102. Are each extended up to). A suitable metal layer (not shown) is formed over the structure and in the holes 124, 126, 128 to form an electrode in electrical contact with the source region 100, the gate region 130, and the drain region 102 to complete the device.

Therefore, a method of forming a MOSFET using silicon germanium or a similar alloy, a substitution gate has been described. Although the preferred method of forming the structure and the technique of using the same in the SIMOX substrate have been described, various modifications can be made without departing from the scope of the present invention.

The present invention uses new materials for dummy or replacement gates that can be selectively removed by good adjustment of gate critical dimensions. In particular, silicon germanium substitution gates can be patterned faster and easier than conventional substitution gates. In addition, the use of silicon germanium or similar alloys as the substitution gate material allows the use of oxide or nitride spacers to form the substitution gate islands. However, conventional polysilicon substitution gates can only be formed with oxide spacers.

Claims (27)

A method of fabricating a MOSFET structure on a substrate comprising the following steps: Forming an island made of an alloy of group IV-B elements of the periodic table on the gate region in the substrate; Establishing sidewalls around the island; Forming a source region and a drain region in the substrate; Selectively removing islands without removing sidewalls to leave voids on the gate area; And Filling the voids with the gate structure. The method of claim 1, wherein the alloy of group IV-B elements is Si _1-x Ge _x , wherein x is about 0.05-1.0. The method of claim 1, wherein prior to forming the islands, depositing an oxide layer on a substrate having a thickness of 5 to 30 nm and forming the islands comprises forming islands on the oxide layer. 4. The method of claim 3, wherein forming the island comprises depositing a layer of material formed from an alloy of group IV-B elements to a thickness of about 150-500 nm over the oxide layer. 5. The method of claim 4, wherein forming the islands comprises: depositing a layer of material of an alloy of periodic table IV-B elements on the oxide layer; Masking the deposited layer on the island portion; And etching the deposited layer to remove the deposited layer except portions on the gate region. The method of claim 1, wherein removing the silicon germanium alloy islands comprises depositing a layer of non-island material over the islands, sidewalls and source and drain regions; Chemical mechanical polishing the structure of the top of the island; And dissolving the island with a solvent to leave voids. 7. The method of claim 6 wherein the non-islet material layer is polysilicon, i.e., a first polysilicon layer, and wherein filling the voids comprises depositing a gate material layer over the remaining first polysilicon layers and the voids and the first polysilicon. Chemical mechanical polishing the structure to remove material to the upper level of the layer. 8. The method of claim 7, wherein the gate material comprises polysilicon; Tungsten (W); Tantalum (Ta); Platinum (Pt); Molybdenum (Mo); Copper (Cu) used with barrier metals such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN); And polysilicon germanium. The method of claim 6, wherein the non-islet material layer is a first layer of dielectric material. 10. The method of claim 9, wherein the first layer of dielectric material is selected from the group consisting of silicon nitride and oxides. 10. The method of claim 9 including after the step of filling the voids with the gate structure, planarizing the top surface of the structure by chemical mechanical polishing. 12. The method of claim 11, after the step of flattening the structure, depositing a second layer of dielectric material over the planarizing structure, forming a hole through the second layer of dielectric material to the gate structure, the dielectric material Forming a hole through the second layer and the first layer of the electrode to the source and drain regions, and depositing a metal layer on the structure to the hole to electrically connect the electrode to the source region, the gate region and the drain region. Forming. 2. The method of claim 1, wherein setting the sidewalls around the island comprises setting sidewalls of a material selected from the group consisting of silicon nitride and oxides. The method of claim 1 wherein the voids have a length extending from 0.10 to 0.2 microns from the source region to the drain region. 2. The process of claim 1, wherein filling the voids with the gate structure comprises depositing a gate dielectric layer over the source region, the drain region, and the void to form a gate dielectric layer in the void, and depositing a gate electrode material layer over the gate dielectric layer. How to. 16. The method of claim 15, wherein forming the gate dielectric layer comprises depositing a material having a high dielectric constant and high breaking strength. The method of claim 15, wherein the deposited gate dielectric comprises: Ta ₂ O ₅ , TiO ₂ , ZrO ₂ or HfO ₂ ; Ta ₂ O ₅ , TiO ₂ , ZrO ₂ or HfO ₂ materials doped with Si; A material comprising a material selected from the group consisting of Ta ₂ O ₅ , TiO ₂ , ZrO ₂ or HfO ₂ materials doped with Al. The method of claim 15, wherein depositing the gate dielectric layer is performed by a process selected from physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma accelerated chemical vapor deposition (PECVD). 2. The method of claim 1 including after the step of filling the voids with the gate structure, planarizing the top surface of the structure by chemical mechanical polishing. 20. The method of claim 19, wherein after planarizing the top surface of the structure, a metal layer is deposited on the top surface of the structure and the structure is metalized to form an electrode in electrical connection with the source region, the gate region and the drain region. Way. 21. The method of claim 20 including annealing the structure to promote a salicide process after depositing a metal layer on the top surface of the structure and before metallizing the structure. A method of making a MOSFET comprising the following steps: Depositing an oxide layer on the silicon substrate for device isolation; Forming a silicon tin alloy island over a gate region in the substrate; Setting a sidewall around the silicon tin alloy island; Forming a source region and a drain region in the substrate; Removing the silicon tin alloy islands to leave voids on the gate region; Filling portions and voids on the source and drain regions; And Planarizing the upper surface of the structure by chemical mechanical polishing. The method of claim 22, wherein the silicon tin alloy is represented by Si _1-x Sn _x , wherein x is about 0.05 to 1.0. 23. The method of claim 22, wherein establishing side measurements around the silicon tin alloy islands comprises setting the sidewalls with sidewall material selected from the group consisting of silicon nitride and oxide. A method of making a MOSFET comprising the following steps: Depositing an oxide layer on the silicon substrate for device isolation; Forming a silicon germanium alloy island over a gate region in the substrate; Setting the sidewalls on the silicon germanium alloy island edge; Forming a source region and a drain region in the substrate; Removing the silicon germanium alloy island to leave voids on the gate region; Filling portions and voids on the source and drain regions; And Planarizing the upper surface of the structure by chemical mechanical polishing. The method of claim 25, wherein the silicon germanium alloy is represented by Si _1-x Ge _x , wherein x is about 0.05 to 1.0. 27. The method of claim 25, wherein setting the sidewalls around the silicon germanium alloy island comprises setting the sidewalls with sidewall material selected from the group consisting of silicon nitride and oxide.