KR20010039174A - A method of forming contact in semiconductor devices - Google Patents

Abstract

PURPOSE: A method for manufacturing a contact of a semiconductor device is provided to prevent resistance from increasing in an interface of the contact through a re-silicidation process even if a silicide layer for an ohmic contact formed under a contact hole is damaged in patterning an interlayer dielectric and forming the contact hole. CONSTITUTION: A portion where a contact is to be formed is silicified. An interlayer dielectric(21) is stacked. A contact hole is formed on the portion where the contact is to be formed. Metal used in the silicidation is stacked to re-form a silicide of the metal on the bottom surface of the contact hole. A barrier metal layer(31) is stacked. A chemical vapor deposition(CVD) tungsten layer is filled in the contact.

Description

Method for forming contact of semiconductor device {A METHOD OF FORMING CONTACT IN SEMICONDUCTOR DEVICES}

The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a method for forming a contact having a metal silicide layer as an ohmic contact layer at an interface in a semiconductor device manufacturing process.

BACKGROUND OF THE INVENTION A semiconductor device is a very sophisticated and complicated device fabricated by forming various kinds of conductors, non-conductors, and semiconductors on a semiconductor substrate, processing them to form electronic and electrical elements, and combining them by wiring. Many devices are integrated on a narrow semiconductor substrate, and device integration in semiconductor devices continues to increase exponentially.

The main problem is how to form a large number of devices in a small area according to the trend of high integration of semiconductor devices. For this purpose, it is important to reduce wiring and device sizes. On the other hand, one of the trends due to the high integration of devices is the multilayering, three-dimensional or wiring of semiconductor devices. As the size of devices and wirings are reduced and multilayering proceeds, the formation of contacts connecting devices and wirings, wirings and wirings is also becoming more important in the manufacture of semiconductor devices.

The difficulty in forming a contact is that the area of the contact decreases and the contact depth becomes relatively deep, thus increasing the aspect ratio and increasing the stepped portion, making it difficult to fill the contact hole with the contact hole in terms of the process. will be. For example, in the process of simple sputtering, the contact reliability decreases due to an overhang of the contact hole inlet and a void in the contact during the formation of the contact. In addition, in terms of the function of the semiconductor to be formed, the resistance due to the contact increases, and the design difficulty is highlighted when considering that the resistance at the interface to be contacted is increased because the material of the contact and the contact element are different.

In order to operate quickly and efficiently in a semiconductor device, a delay time of device operation must be small. Conventionally, the gate delay time mainly takes up a large portion of the delay time, but in recent years, as the line width is reduced due to the high device integration, the delay time according to the resistance and the capacitance, that is, the RC delay time, takes up a large portion. Increasing the resistance of the contact increases the RC delay time, resulting in a negative phenomenon such as slowing down the operation or operation of the semiconductor device and increasing power consumption. Therefore, a method for reducing contact resistance in a semiconductor device requiring high device integration is actively requested.

In order to fill the contact hole with a normal contact function, it is necessary to use a reflow of metal such as aluminum, to form a contact through reflow and multiple stacking, and to fill a space-filled CVD tungsten. And a method of using as a contact metal. In addition, the increase in resistance caused by the increase in the formation thickness of the contact is relatively large compared to the width, and a method of using a conductive material has been studied. The problem of resistance at the contact interface, which is one of the most important factors for increasing the contact resistance, There are many methods to form and use an interlayer material that can reduce unstable elements such as spike phenomenon at the interface and electrically connect two materials forming the interface.

At the interface where aluminum or tungsten, which is used as a wiring and a contact metal, and silicon are in contact with each other, there is a tendency of a spike phenomenon due to diffusion of silicon into the metal. When the spike phenomenon occurs, the electrical connection of the interface is not normally made, so the resistance value increases significantly, so that a barrier metal, which can prevent the diffusion of silicon, is first deposited before the contact metal is laminated. Mainly used as barrier metal is a Ti / TiN layer.

Considering the above, an example of a method of forming a metal contact in a source / drain of a conventional MOS transistor will be described with reference to the accompanying drawings.

FIG. 1 shows a gate insulating film 12 and a gate 15 formed after separating a region of a substrate 10 by a field insulating film 11 in a conventional semiconductor device manufacturing process, and forming spacers 17 on sidewalls of the gate 15. In one state, ion implantation is performed on the active region, and then a metal such as titanium or cobalt is deposited on the front surface of the wafer, and reacted with silicon of the substrate through a rapid thermal annealing (RTA) to source / drain regions 13 and gate (15) The state in which the titanium or cobalt silicide 19 (TiSi ₂ , CoSi ₂ ) was formed on the electrode. After stacking, the remaining metal that does not form silicide 19 by reacting with silicon of the substrate 10 is removed by wet etching, so that the metal layer and the source / drain region 13 stacked on the field insulating layer 11 or other inactive region 13 are removed. Some of the metal layers which did not react among the metal layers laminated on the cavities are then removed. As a result, silicidation occurs only on the source / drain regions 13 and the gate 15.

FIG. 2 is a state in which an interlayer dielectric (ILD: Inter Layer Dielectric) 21 is stacked in the state of FIG. 1, and then a contact hole 23 is formed through dry etching. In this process, the metal silicide 19 is present under the interlayer insulating layer 21 of the portion where the contact hole 23 is to be formed. A part of the thickness of the metal silicide layer may be removed by etching.

FIG. 3 is a Ti / TiN layer formed of a barrier metal 31 on the inner surface of the contact hole 23 in the state in which the contact hole 23 is formed as shown in FIG. It shows the state which formed. Tungsten is deposited via Chemical Vapor Depisition (CVD). CVD tungsten is widely used for forming deep contact plugs in semiconductor devices having high space filling and high integration rates. Although the wiring can be formed by patterning the tungsten film laminated over the interlayer insulating film 21, the wiring is often formed by removing and removing the tungsten film except for the plug by CMP processing and laminating and patterning aluminum. The barrier metal stacked on the interlayer insulating film 21 can be removed simultaneously with the tungsten film through CMP (Chemical Mechanical Polishing) processing.

However, in the conventional contact forming process described above with reference to the drawings, the metal silicide layer for improving the electrical contact state between the contact metal and the silicon interface is erroneously adjusted due to incorrect etching rate or time during the etching of the interlayer insulating film. Removal may occur. In this case, the contact resistance of the interface is greatly increased, and even if the signal is not transmitted well, the RC delay time due to the high resistance increases even when the signal is transmitted, which may cause a problem in the function of the device.

The present invention is to improve the RC delay time due to the increase in the contact resistance in the semiconductor device described above, and to reduce the delay time by reducing the resistance of the interface in the contact can improve the function of the semiconductor device An object of the present invention is to provide a method for forming a semiconductor device contact.

1 is a cross-sectional view illustrating a state in which metal silicide is formed on a silicon exposed portion by stacking metal and reacting with silicon on a substrate in a conventional semiconductor device manufacturing process;

FIG. 2 is a process cross-sectional view illustrating a state in which a contact hole is formed through dry etching after stacking an interlayer dielectric (ILD) in the state of FIG. 1; FIG.

FIG. 3 is a cross-sectional view illustrating a state in which a barrier metal layer is formed inside a contact hole in a state where a contact hole is formed, a CVD tungsten is laminated, and a plug is formed by CMP processing;

4 is a cross-sectional view illustrating a state in which cobalt silicide (CoSi ₂ ) is formed on a silicon layer in an upper gate and a source / drain region according to the present invention;

FIG. 5 is a cross-sectional view illustrating a state in which a contact hole is formed over a gate electrode and a source / drain region by forming an interlayer dielectric layer in the state of FIG. 4 and patterning;

FIG. 6 is a cross-sectional view illustrating a state in which cobalt silicide is formed on the bottom of a contact hole in the state of FIG. 5; FIG.

FIG. 7 is a cross-sectional view illustrating a state in which a contact plug is formed by sequentially depositing titanium (Ti) and titanium nitride (TiN) with a barrier metal on the front surface of a wafer in the state of FIG. 6 and depositing tungsten through CVD.

* Explanation of symbols for main parts of the drawings

10: substrate 11: field insulating film

12: gate insulating film 13: source / drain region

15 gate 17 spacer

19, 61: silicide 21: interlayer insulating film (ILD)

23: contact hole 31: barrier metal

33: plug

In the semiconductor device contact forming method of the present invention for achieving the above object, in the formation of a semiconductor device having a MOS transistor element, the step of silicided the portion where the contact is to be formed, such as the source / drain region and the gate top, interlayer insulating film Forming a contact hole over the stacked and silicided region, laminating a metal used for the silicidation to re-form silicide of the metal on the bottom of the contact hole, laminating a barrier metal, laminating CVD tungsten Characterized in that it comprises a step of filling the contact.

Examples of the metal used for the silicidation in the present invention include titanium and cobalt. When these metals are in contact with silicon and subjected to heat treatment, the metal diffuses with temperature to form a silicide layer and a stable contact surface, and lowers interfacial resistance as an ohmic contact layer between the conductive layer formed thereon and the silicon layer below. Do it.

In addition, the general process of silicide formation used in the present invention will be described in detail, first laminating the metal used for silicide formation, and induces bonding of the metal and the lower silicon layer through a heat treatment process such as rapid thermal prcessing (RTP). Then, the metal remaining without the silicide reaction is removed by wet etching or wet cleaning.

Hereinafter, the present invention will be described in more detail with reference to the drawings showing the process steps from FIG. 4 to FIG. 7.

FIG. 4 is a view similar to FIG. 1, in which the substrate 10 is separated into a field insulating film 11, a gate insulating film 12 and a gate 15 pattern are formed, and then source / drain regions are formed through ion implantation. 13 is a cross-sectional view showing a state in which cobalt silicide 19 (CoSi ₂ ) is formed on the gate 15 and the silicon layer of the source / drain region 13. In order to form the silicide 19, a cobalt layer is deposited on the entire surface of the wafer by sputtering or the like, and induction of silicidation of the silicon and the cobalt metal exposed through the rapid thermal annealing (RTA) is performed. And metal cobalt remaining without forming silicide is removed over the entire wafer surface by wet etching.

FIG. 5 illustrates a state in which an interlayer dielectric 21 layer is formed in the state of FIG. 4 and a contact hole 23 is formed over the gate 15 electrode and the source / drain region 13 through a patterning process. It is a cross section. At this time, in the etching process, the cobalt silicide 19 layer formed in advance in order to reduce contact resistance at the interface between the metal to form the contact hole 23 and the silicon layer forming the electrode is removed. This state does not intentionally remove silicide, but silicide is removed due to variation in etching control.

FIG. 6 is a cross-sectional view illustrating a state in which cobalt silicide 19 is formed on the bottom of the contact hole 23 in the state of FIG. 5. Cobalt, which is the same metal used for silicidation in the process of Fig. 4, is laminated on the entire wafer surface including the inner surface of the contact hole 23 again and subjected to RTP for a predetermined time, and cleaned with an etching solution for cobalt. The cobalt silicide 61 is formed on the bottom of the contact hole 23 again, and the cobalt metal is removed from the other portions.

FIG. 7 illustrates a state in which the contact plug 33 is formed by sequentially depositing titanium (Ti) and titanium nitride (TiN) with the barrier metal 31 on the front surface of the wafer in the state of FIG. It is a cross section. Tungsten is deposited by a space-filling CVD method, and tungsten fluoride (WF ₆ ) is generally used as a source gas. Barrier metals that prevent diffusion between tungsten and silicon are possible with titanium, but titanium can be easily reacted with and removed from the source gas of CVD tungsten, WF ₆ , thus stacking titanium nitride over titanium to stabilize it. In the state where tungsten is stacked, the tungsten layer and the barrier metal layer on the interlayer insulating film are removed by CMP, leaving only the portion forming the contact plug. Later, for wiring, aluminum may be laminated and patterned.

According to the present invention, even when the silicide layer for ohmic contact previously formed is damaged in the process of etching the contact hole by patterning the interlayer insulating film, the phenomenon of increasing the resistance at the contact interface can be reduced through resilicide. As the device is highly integrated, an increase in resistance due to a decrease in size of a contact or the like and an increase in defects due to this can be reduced.

Claims (3)

In forming a semiconductor device having a MOS transistor element, Silicidating the portion where the contact is to be formed, Stacking an interlayer insulating film and forming a contact hole over said portion, Stacking the metal used for silicidation to re-form silicide of the metal on the bottom of the contact hole; Laminating the barrier metal, and And depositing CVD tungsten to fill the contact. The method of claim 1, The method of forming a contact of a semiconductor device, wherein cobalt is used as the metal. The method of claim 1, The silicided or silicide re-formation, Laminating the metal used to form the silicide, Inducing bonding of the metal and the lower silicon layer through a heat treatment process; And removing the metal remaining without reacting with silicon by wet etching.