KR20010039147A - Method of forming a metal wiring in a semiconductor device using a dual damascene process - Google Patents

Abstract

PURPOSE: A method for manufacturing a metal interconnection of a semiconductor device by a dual damascene process is provided to eliminate overlap of a contact hole and a trench, by simultaneously forming the contact hole and the trench in a one-time mask process. CONSTITUTION: A substrate(11) is prepared which has a lower structure for forming a metal interconnection. The first insulating layer(13) is formed on the substrate. An etch barrier layer pattern is formed on the first insulating layer to define a region for forming a metal contact(19) and a region for forming a metal interconnection. The second insulating layer(16) is formed on the entire structure, and the second insulating layer in the region for the metal interconnection is etched to form a trench by using the mask for forming a damascene pattern. The first insulating layer in the region for the metal contact of the etch barrier layer pattern is etched to form a contact hole, so that the damascene pattern composed of a trench and a contact hole is formed. The mask for the damascene pattern is eliminated. A metal layer is formed on the entire structure including the damascene pattern and planarized.

Description

Method of forming a metal wiring in a semiconductor device using a dual damascene process}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, when a metal wiring is formed using a dual damascene process, a misalignment of a contact plug and a metal wiring can be prevented to form a stable wiring structure. A metal wiring formation method of a semiconductor device using a damascene process.

In the general semiconductor device forming process, the metal wiring is formed by forming an oxide film on the substrate on which the conductive pattern is formed and planarizing, forming a contact hole using a contact mask, and then forming a glue layer on the entire structure including the contact hole. And then tungsten is deposited and then planarized to form a plug, which is then formed by forming and patterning a metal layer. In this case, as the line width of the circuit decreases, the gap and width of the metal line decrease, so that a bridge occurs between the metal wires and the metal wire sidewall is damaged. In addition, there is a problem that the plug is damaged by the misalignment of the plug and the metal wiring.

A technology introduced to solve this problem is a damascene process, and a dual damascene process will be described below.

In the dual damascene process, after forming the first insulating film and the etch stop layer, a portion of the etch stop layer is etched by the photolithography process and the etch process to define a portion where a contact hole is to be formed, and a second insulating film thereon. After forming, the trench and contact holes are again formed by a photolithography process and an etching process to form a dual damascene pattern. Thereafter, the metal layer is polished on the second insulating film including dual damascene by metal deposition and chemical mechanical polishing to form a metal wiring. The dual damascene method has a problem in that contact holes and trenches are misaligned because the dual damascene pattern is formed by performing the photolithography process and the etching process twice. In addition, when the aspect ratio of the photoresist pattern is high, there is a problem that the photoresist pattern collapses. Furthermore, since both upper and lower insulating layers are oxides, it is difficult to control the exact etch stop point during dry etching, thereby precisely adjusting the thickness of the metal wiring. Inevitably, there is a problem that the stability of the metal wiring forming process is insufficient, resulting in a decrease in reliability and yield of the device.

Accordingly, the present invention provides a method for forming a metal wiring in a semiconductor device using a dual damascene process that can prevent misalignment between a plug and a metal wiring by forming a damascene pattern such that a contact hole for a metal contact and a trench for a metal wiring are formed at the same time. The purpose is to provide.

In the method of forming a metal wiring of a semiconductor device using a dual damascene process according to the present invention for achieving the above object, a substrate having a substructure for forming metal wiring is provided, and forming a first insulating film on the substrate. step; Forming an etch barrier layer pattern on the first insulating layer to define a metal contact formation region and a metal wiring formation region; After forming a second insulating film on the entire structure including the etch barrier layer pattern, a trench is formed by etching the second insulating film of the predetermined region for forming the metal wiring by using a mask for forming a damascene pattern, wherein the trench is formed. Forming a contact hole by etching the first insulating layer in the region where the metal contact is to be formed in the layer pattern, thereby forming a damascene pattern consisting of a trench and a contact hole; And removing the damascene pattern forming mask and forming and planarizing a metal layer on the entire structure including the damascene pattern.

1A to 1F are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device using a mashin process according to the present invention.

<Explanation of symbols on the main parts of the drawing>

11: substrate 12: conductive pattern

13 first insulating film 14 etching barrier layer

15 metal / contact mask 16 second insulating film

17: mask for damascene pattern formation 18A: trench

18B: contact hole 18: damascene pattern

19: metal contact 20: metal wiring

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1A to 1F are cross-sectional views of devices sequentially illustrated to explain a method for forming metal wirings of a semiconductor device using a dual damascene drinking process according to the present invention.

Referring to FIG. 1A, when the substrate 11 having the conductive pattern 12 is provided, the first insulating film 13 is formed and planarized over the entire structure, and then a large etching selectivity with the first insulating film 13 is obtained. The etching barrier layer 14 is formed by using a material having the same. Here, the first insulating film 13 is formed to a thickness of 6000 to 10000 kV using an oxide film. In addition, the material of the etching barrier layer 14 may be any material as long as the material has a high etching selectivity with respect to the first insulating film 13, and thereafter, a contact characteristic with a metal used for filling the gap, and the first insulating film 13. This is determined in consideration of contact characteristics with, and is mainly formed using metal or nitride material. In addition, the thickness of the etching barrier layer 14 is formed to a thickness sufficient to act as a barrier while the first insulating layer 13 is etched in a subsequent process, for example, titanium (Ti) and titanium nitride (TiN). When formed using a metal, such as to form a thickness of 1000 to 2000Å, if formed using a nitride material to form a thickness of 100 to 500Å.

Referring to FIG. 1B, the metal / contact mask 15 is formed and etched to pattern the etch barrier layer 14. The etch barrier layer 14 is then patterned as large as about 0.05 μm in consideration of an overlap margin with the mask for forming a damascene pattern.

Referring to FIG. 1C, the metal / contact mask 15 is removed, the second insulating layer 16 is formed and planarized on the entire structure including the patterned etching barrier layer 14, and then the damascene pattern is formed. The mask 17 is formed. Here, the second insulating film 16 is formed to a thickness of a metal wiring, for example, a thickness of 6000 to 10000 kPa using an oxide film. In addition, since the etch barrier layer 14 is formed low, the planarization process of the second insulating film 16 may be omitted.

Referring to FIGS. 1D and 1E, the second insulating layer 16 and the first insulating layer 13 are etched using the damascene pattern forming mask 17. At this time, the portion where the metal wiring is formed is etched only to the etch barrier layer 14 by selective etching, so that the trench 18A is formed, and the remaining portion of the metal contact is etched to the conductive pattern 12 to form a contact hole. 18B is formed. Accordingly, the damascene pattern 18 is formed, and the metal wirings formed in the trench 18A have a uniform thickness. The first and second insulating films 13 and 16 are removed by a dry etching method. In the case where the nitride material is used as the etching barrier layer 14, the nitride material remaining after the first and second insulating layers 13 and 16 are etched is removed by the difference in etching selectivity from the oxide layer.

Referring to FIG. 1F, the damascene pattern forming mask 17 is removed to form and planarize a metal layer on the entire structure including the finished damascene pattern 17. As a result, the trench 18A and the contact hole B are embedded to complete the metal contact 19 and the metal wiring 20. As described above, a design rule having zero overlap between the metal contact 19 and the metal wiring 20 is possible using only one mask 17 for forming a madsin pattern, thereby reducing the size of the device. Can be reduced.

As described above, in the present invention, since the contact hole and the trench are simultaneously formed in one mask process in the dual damascene process, the overlap between the contact hole and the trench can be zero. In addition, it is possible to prevent the thickness of the metal wiring from being changed due to the difference in the thickness of the insulating film due to the load effect.

Claims (9)

Providing a substrate having a lower structure for forming metal wiring, and forming a first insulating film on the substrate; Forming an etch barrier layer pattern on the first insulating layer to define a metal contact formation region and a metal wiring formation region; After forming a second insulating film on the entire structure including the etch barrier layer pattern, a trench is formed by etching the second insulating film of the predetermined region for forming the metal wiring by using a mask for forming a damascene pattern, wherein the trench is formed. Forming a contact hole by etching the first insulating layer in the region where the metal contact is to be formed in the layer pattern, thereby forming a damascene pattern consisting of a trench and a contact hole; And Removing the damascene pattern forming mask and forming and planarizing a metal layer on the entire structure including the damascene pattern; and forming a metal layer on the entire structure including the damascene pattern. The method of claim 1, The first insulating film is a metal wiring forming method of a semiconductor device using a dual damascene process, characterized in that to form a thickness of 6000 to 10000Å using an oxide film. The method of claim 1, The etching barrier layer is a metal wiring forming method of a semiconductor device using a dual damascene process, characterized in that formed using a material having a large etching selectivity with the first insulating film. The method of claim 1, The etching barrier layer is a metal wiring forming method of a semiconductor device using a dual damascene process, characterized in that to form a thickness of 1000 to 2000Å using a metal material. The method of claim 1, The etching barrier layer is a metal wiring forming method of a semiconductor device using a dual damascene process, characterized in that to form a thickness of 100 ~ 500Å by using a nitride material. The method of claim 1, The etching barrier layer pattern is a metal wiring forming method of a semiconductor device using a dual damascene process, characterized in that for patterning about 0.05㎛ large considering the overlap margin with the mask for forming the damascene pattern. The method of claim 1, The second insulating film is a metal wiring forming method of a semiconductor device using a dual damascene process, characterized in that formed by the thickness of the metal wiring using an oxide film. The method of claim 1, Wherein the first and second insulating layers are removed by a dry etching method. The method of claim 1, When the nitride material is used as the etch barrier layer, the method may further include removing the nitride material remaining after the first and second insulating layers are etched.