KR20010039115A - Multi chip package - Google Patents

Multi chip package Download PDF

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Publication number
KR20010039115A
KR20010039115A KR1019990047364A KR19990047364A KR20010039115A KR 20010039115 A KR20010039115 A KR 20010039115A KR 1019990047364 A KR1019990047364 A KR 1019990047364A KR 19990047364 A KR19990047364 A KR 19990047364A KR 20010039115 A KR20010039115 A KR 20010039115A
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KR
South Korea
Prior art keywords
semiconductor chips
semiconductor
leads
bonding pads
semiconductor chip
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KR1019990047364A
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Korean (ko)
Inventor
정영두
안상호
이충우
Original Assignee
윤종용
삼성전자 주식회사
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Priority to KR1019990047364A priority Critical patent/KR20010039115A/en
Publication of KR20010039115A publication Critical patent/KR20010039115A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A multi chip package is to broaden a selecting range of a semiconductor chip by forming a multi chip package with semiconductor chips having similar size and to reduce a fabrication cost. CONSTITUTION: A multi chip package comprises two horizontally arranged semiconductor chips having similar size. A lead(130,135) is mounted to a predetermined part of top surface of each semiconductor chip for electrically connecting an exterior terminal to the semiconductor chip. A conductive wire(140,145) electrically conducts the semiconductor and the leads. A moulding product(150) surrounds the semiconductor chip, the conductive wire and the lead to protect them from exterior environment. A bonding pad electrically connected to the lead by the conductive wire is in series arranged in one end of top surface of the semiconductor chip along a longitudinal direction of the semiconductor chip. When two semiconductor chips are horizontally arranged, the bonding pads formed on the chips are symmetrical with respect to each other. The leads are attached to a part of top surface of each semiconductor chip displaced from the bonding pad. A cut groove(155) is formed to individually separate two semiconductor chips on which the molding product is formed.

Description

멀티 칩 패키지{Multi chip package}Multi chip package

본 발명은 멀티 칩 패키지에 관한 것으로, 더욱 상세하게는 일측단부에만 본딩패드들이 형성되고 크기가 거의 비슷한 반도체 칩을 적어도 2개이상의 리드프레임에 수평으로 부착하여 패키징한 멀티 칩 패키지에 관한 것이다.The present invention relates to a multi-chip package, and more particularly, to a multi-chip package in which bonding pads are formed only at one end and are packaged by attaching a semiconductor chip having a substantially similar size to at least two lead frames horizontally.

최근, 전자 및 정보기기의 다기능화, 고속화 및 대용량화에 대응하고 메모리 모듈의 실장밀도를 향상시켜 전자 및 정보기기를 소형화시키기 위해서 여러개의 반도체 칩을 수직으로 적층시켜 실장한 멀티 칩 패키지가 개발되고 있다.In recent years, multi-chip packages have been developed in which multiple semiconductor chips are stacked vertically in order to cope with the multi-function, high-speed and large-capacity of electronic and information devices, and to increase the mounting density of memory modules and to miniaturize electronic and information devices. .

이러한 멀티 칩 패키지의 제조 방법을 개략적으로 설명하면, 소정크기를 갖고 폭방향 양측단부에 본딩패드들이 형성된 제 1 반도체 칩을 리드프레임의 다이패드에 부착하고, 제 1 반도체 칩의 본딩패드들이 외부로 노출되도록 제 1 반도체 칩보다 크기가 작은 제 2 반도체 칩을 제 1 반도체 칩의 상부면에 부착한다.When the manufacturing method of the multi-chip package is schematically described, a first semiconductor chip having a predetermined size and bonding pads formed at both ends in the width direction thereof is attached to the die pad of the lead frame, and the bonding pads of the first semiconductor chip are moved to the outside. A second semiconductor chip smaller in size than the first semiconductor chip is attached to the upper surface of the first semiconductor chip so as to be exposed.

그리고, 제 1 및 제 2 반도체 칩의 상부면에 형성된 본딩패드들과 리드프레임의 리드들을 도전성 와이어를 이용하여 전기적으로 연결시킨다.The bonding pads formed on the upper surfaces of the first and second semiconductor chips and the leads of the lead frame are electrically connected using conductive wires.

앞에서 설명한 바와 같이 제 1 및 제 2 반도체 칩들을 수직으로 적층시키는 경우, 반드시 제 1 반도체 칩의 본딩패드들은 에지에 형성되어야 하며, 제 1 반도체 칩의 크기가 제 2 반도체 칩의 크기보다 커야된다. 이는 제 2 반도체 칩의 외부로 제 1 반도체 칩의 본딩패드들을 노출시켜 리드프레임의 리드들과 제 1 반도체 칩의 본딩패드들을 도전성 와이어로 연결시키기 위해서 이다.As described above, when the first and second semiconductor chips are vertically stacked, the bonding pads of the first semiconductor chip must be formed at the edges, and the size of the first semiconductor chip must be larger than the size of the second semiconductor chip. This is to expose the bonding pads of the first semiconductor chip to the outside of the second semiconductor chip to connect the leads of the lead frame and the bonding pads of the first semiconductor chip with conductive wires.

이와 같이 와이어 본딩이 완료되면, 제 1 및 제 2 반도체 칩과 도전성 와이어 리드프레임의 소정부분을 보호하기 위해서 제 1 및 제 2 반도체 칩을 포함하여 리드프레임의 리드의 소정부분까지 몰딩수지로 덮어 몰딩물을 형성한다.When the wire bonding is completed as described above, in order to protect certain portions of the first and second semiconductor chips and the conductive wire lead frame, the first and second semiconductor chips are covered with molding resin to cover a predetermined portion of the lead of the lead frame. Forms water.

이후에 댐바를 절단하는 트림 공정을 진행하고, 몰딩물의 외부로 노출된 리드들을 소정형상으로 절곡하는 포밍공정을 진행하여 멀티 칩 패키지를 완성한다.Thereafter, the trim process is performed to cut the dam bar, and the forming process of bending the leads exposed to the outside of the molding to a predetermined shape is performed to complete the multi-chip package.

그러나, 반도체 칩들이 수직으로 적층된 멀티 칩 패키지의 경우 상술한 바와 같이 리드프레임의 다이패드에 접착되는 반도체 칩의 본딩패드들이 반도체 칩의 상부에 적층되는 다른 반도체 칩에 의해 덮여지면 와이어 본딩 공정이 불가능하기 때문에 리드프레임의 다이패드에서 접착되는 반도체 칩 보다 이 반도체 칩의 상부에 적층되는 다른 반도체 칩의 크기가 훨씬 작아야 하므로 멀티 칩 패키지를 제조하는데 반도체 칩의 크기에 제약을 받게된다.However, in the case of a multi-chip package in which semiconductor chips are vertically stacked, as described above, when the bonding pads of the semiconductor chip bonded to the die pad of the lead frame are covered by another semiconductor chip stacked on the semiconductor chip, the wire bonding process is performed. Since the size of other semiconductor chips stacked on top of the semiconductor chip is much smaller than that of the semiconductor chip bonded on the die pad of the lead frame, the size of the semiconductor chip is limited in manufacturing the multi-chip package.

또한, 패키징된 복수개의 반도체 칩들 중 어느 하나의 반도체 칩에 불량이 발생되면 이 멀티칩 패키지의 전체를 폐기처분 해야하기 때문에 제품의 생산성 및 생산원가가 상승되는 문제점이 있다.In addition, when a defect occurs in any one of the plurality of packaged semiconductor chips, it is necessary to dispose of the entire multichip package, thereby increasing the productivity and production cost of the product.

따라서, 본 발명의 목적은 상기와 같은 문제점을 감안하여 안출된 것으로써, 크기가 거의 비슷한 반도체 칩들로 멀티 칩 패키지를 형성하여 반도체 칩의 선택의 폭을 넓히는데 있다.Accordingly, an object of the present invention is to conceive in view of the above problems, to form a multi-chip package with semiconductor chips of almost the same size to broaden the choice of semiconductor chips.

본 발명의 다른 목적은 제품의 생산성 및 제조 비용을 절감하는데 있다.Another object of the present invention is to reduce the productivity and manufacturing cost of the product.

본 발명의 또 다른 목적은 다음의 상세한 설명과 첨부된 도면으로부터 보다 명확해 질 것이다.Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

도 1은 본 발명에 의한 멀티 칩 패키지를 제조하기 위해서 반도체 칩들을 수평으로 배열한 상태를 나타낸 사시도.1 is a perspective view showing a state in which the semiconductor chips are arranged horizontally in order to manufacture a multi-chip package according to the present invention.

도 2는 본 발명에 의한 멀티 칩 패키지의 구조를 나타낸 단면도.Figure 2 is a cross-sectional view showing the structure of a multi-chip package according to the present invention.

이와 같은 목적을 달성하기 위해서 본 발명은 서로 비슷한 크기를 갖고 폭방향 일측에 본딩패드들이 형성되며 본딩패드들이 서로 인접한 방향에 놓이도록 수평으로 배열되는 적어도 2개 이상의 반도체 칩들, 본딩패드들과 소정간격 이격되어 각각의 반도체 칩들의 상부면에 부착되며 외부단자와 반도체 칩들을 전기적으로 연결시키는 리드들, 일단이 본딩패드들에 본딩되고 타단이 리드들과 본딩되어 각각의 반도체 칩들과 리드들을 전기적으로 연결시키는 도전성 재질의 와이어들 및 반도체 칩들과 와이어들 및 리드들의 소정부분을 감싸고 있어 이들을 외부환경으로부터 보호하는 몰딩물을 포함한다.In order to achieve the above object, the present invention has a similar size, bonding pads are formed on one side in the width direction, and the at least two semiconductor chips, the bonding pads, and the predetermined intervals are arranged horizontally so that the bonding pads are located in the adjacent directions. Leads spaced apart from each other and attached to the upper surface of each semiconductor chip to electrically connect the external terminals and the semiconductor chips, one end is bonded to the bonding pads and the other end is bonded to the leads to electrically connect the respective semiconductor chips and leads. And a molding covering the predetermined portions of the wires and the semiconductor chips, the wires and the leads of the conductive material to protect them from the external environment.

바람직하게, 몰딩물 중 반도체 칩들 사이에는 하나의 반도체 칩과 리드프레임을 갖도록 몰딩물을 절단하기 위한 절단홈이 소정깊이로 형성된다.Preferably, a cutting groove for cutting the molding to have one semiconductor chip and a lead frame is formed at a predetermined depth between the semiconductor chips of the molding.

그리고, 웨이퍼 상태에서 인접한 열에 형성된 반도체 칩들의 본딩패드들이 서로 대칭이되도록 형성되며, 본딩패드들이 서로 대칭이되도록 형성된 적어도 2개이상의 반도체 칩들은 하나로 절단된다.The bonding pads of the semiconductor chips formed in adjacent rows in the wafer state are formed to be symmetrical with each other, and the at least two semiconductor chips formed such that the bonding pads are symmetrical with each other are cut into one.

이하, 본 발명에 의한 멀티 칩 패키지의 구조를 첨부된 도면 도 1 내지 도 2를 참조하여 설명하면 다음과 같다.Hereinafter, the structure of a multi-chip package according to the present invention will be described with reference to FIGS. 1 to 2.

본 발명에 의한 멀티 칩 패키지(100)는 도 2에 도시된 바와 같이 크기가 거의 비슷하고 수평으로 배열된 2개의 반도체 칩들(110,120)과, 각 반도체 칩(110,120)의 상부면에 소정부분에 부착되어 외부단자와 반도체 칩들(110,120)을 전기적으로 연결시키는 리드들(130,135)과, 각 반도체 칩들(110,120)과 리드들(130,135)을 전기적으로 도통시키는 도전성 와이어(140,145) 및 수평으로 배열된 2개의 반도체 칩(110,120), 도전성 와이어(140,145) 및 도전성 와이어(140,145)가 연결된 리드들(130,135)의 단부 소정부분을 감싸 이들을 외부환경으로부터 보호하는 몰딩물(150)로 구성된다.As shown in FIG. 2, the multi-chip package 100 according to the present invention has two semiconductor chips 110 and 120 which are substantially similar in size and arranged horizontally, and are attached to a predetermined portion on the upper surface of each semiconductor chip 110 and 120. Leads 130 and 135 electrically connecting the external terminals and the semiconductor chips 110 and 120, conductive wires 140 and 145 electrically connecting the semiconductor chips 110 and 120 and the leads 130 and 135, and two horizontally arranged The semiconductor chip 110 and 120, the conductive wires 140 and 145, and the moldings 150 are formed to surround predetermined portions of ends of the leads 130 and 135 to which the conductive wires 140 and 145 are connected to protect them from the external environment.

여기서, 각 반도체 칩들(110,120)의 상부면 일단에는 도전성 와이어(140,145)에 의해서 리드들(130,135)과 전기적으로 연결되는 본딩패드들(115,125)이 각 반도체 칩(110,120)의 길이방향을 따라 일렬로 배열된다.Here, bonding pads 115 and 125 electrically connected to the leads 130 and 135 by conductive wires 140 and 145 at one end of the upper surface of each of the semiconductor chips 110 and 120 are arranged in a line along the length direction of each of the semiconductor chips 110 and 120. Are arranged.

바람직하게, 2개의 반도체 칩(110,120)을 수평으로 배열했을 때 각 반도체 칩들(110,120)에 형성된 본딩패드들(115,125)은 서로 대칭되며, 이는 반도체 칩들(110,120)이 복수개 형성되는 웨이퍼(미도시) 상에 서로 인접한 2개의 반도체 칩들(110,120)의 본딩패드들(115,125)이 서로 대칭되도록 형성되므로 가능하다.Preferably, when the two semiconductor chips 110 and 120 are arranged horizontally, the bonding pads 115 and 125 formed on the semiconductor chips 110 and 120 are symmetric with each other, which is a wafer (not shown) in which a plurality of semiconductor chips 110 and 120 are formed. Since the bonding pads 115 and 125 of the two semiconductor chips 110 and 120 adjacent to each other are formed to be symmetrical with each other.

또한, 리드들(130,135)은 각 반도체 칩(110,120)의 상부면 중 본딩패드들(115,125)의 바깥쪽으로 소정간격 이격된 부분에 접착제(133)에 의해 부착된다.In addition, the leads 130 and 135 are attached to the portions of the upper surfaces of the semiconductor chips 110 and 120 spaced apart from the bonding pads 115 and 125 by a predetermined distance from each other by the adhesive 133.

바람직하게는, 몰딩물(150)의 중앙부분, 즉 2개의 반도체 칩들(110,120)이 서로 소정간격 이격된 부분과 대응하여 몰딩물(150)이 형성된 2개의 반도체 칩(110,120)을 개별적으로 분리하기 위한 절단홈(155)이 형성된다.Preferably, separately separating the two semiconductor chips 110 and 120 in which the moldings 150 are formed in correspondence with the center portion of the molding 150, that is, the two semiconductor chips 110 and 120 spaced apart from each other by a predetermined distance. Cutting grooves 155 are formed.

이와 같이 구성된 멀티 칩 패키지의 제조 과정을 도 1과 도 2를 참조하여 설명하면 다음과 같다.The manufacturing process of the multi-chip package configured as described above will be described with reference to FIGS. 1 and 2.

먼저, 도 1에 도시된 것과 같이 각 반도체 칩들(110,120)에 형성된 본딩패드들(115,125)이 서로 마주보도록 2개의 반도체 칩(110,120)을 수평으로 배열하는데, 이때 본딩패드들(115,125)은 수평으로 배열된 2개의 반도체 칩들(110,120)의 중앙에 위치하게 된다.First, as shown in FIG. 1, the two semiconductor chips 110 and 120 are horizontally arranged such that the bonding pads 115 and 125 formed on the semiconductor chips 110 and 120 face each other, wherein the bonding pads 115 and 125 are horizontally disposed. The two semiconductor chips 110 and 120 are arranged at the center of the array.

여기서, 웨이퍼에서 낱개로 분리된 반도체 칩들을 도 1에 도시된 바와 같이 서로 소정간격 이격시켜 수평으로 배열하기도 하고, 웨이퍼에서 서로 인접한 열에 형성된 반도체 칩들의 본딩패드들이 서로 대칭이되도록 형성하여 본딩패드들이 대칭이되는 두 개의 반도체 칩들을 하나로 절단하여 멀티 칩 패키지를 제조하기도 한다.Here, as shown in FIG. 1, the semiconductor chips separated from the wafer may be arranged horizontally with a predetermined distance therebetween, and the bonding pads of the semiconductor chips formed in rows adjacent to each other on the wafer may be symmetric with each other. A multi-chip package is also manufactured by cutting two symmetrical semiconductor chips into one.

상술한 것과 같이 2개의 반도체 칩들(110,120)이 수평으로 배열되면 본딩패드들(115,125)과 소정간격 이격되도록 2개의 반도체 칩들(110,120) 사이드에 접착제를 이용하여 리드들(130,135)을 부착한 후에, 도전성 와이어(140,145)의 일단은 각각의 본딩패드들(115,125)에 연결하고 타단은 리드들(130,135)에 연결하여 반도체 칩들(110,125)과 리드들(130,135)을 전기적으로 연결시킨다.As described above, when the two semiconductor chips 110 and 120 are horizontally arranged, the leads 130 and 135 are attached to the two semiconductor chips 110 and 120 by using an adhesive so as to be spaced apart from the bonding pads 115 and 125 by a predetermined distance. One end of the conductive wires 140 and 145 is connected to the respective bonding pads 115 and 125 and the other end is connected to the leads 130 and 135 to electrically connect the semiconductor chips 110 and 125 to the leads 130 and 135.

이어, 도전성 와이어(140,145)가 연결된 리드들(130,135)의 소정부분과 반도체 칩(110,120)) 및 도전성 와이어들(140,145)을 외부환경으로부터 보호하기 위해서 리드들(130,135))이 부착된 반도체 칩들(110,120)을 금형설비(미도시)로 이송시켜 2개의 반도체 칩(110,120)을 포함하여 도전성 와이어(140,145)가 연결된 리드들(130,135)의 단부 소정부분까지 에폭시 몰딩 컴파운드로 감싸고 에폭시 몰딩 컴파운드를 경화시켜 도 2에 도시된 바와 같이 반도체 칩들(110,120)의 외부에 몰딩물(150)을 형성한다.Subsequently, predetermined portions of the leads 130 and 135 to which the conductive wires 140 and 145 are connected, the semiconductor chips 110 and 120, and the semiconductor chips to which the leads 130 and 135 are attached to protect the conductive wires 140 and 145 from the external environment ( 110 and 120 are transferred to a mold facility (not shown), including two semiconductor chips 110 and 120, wrapped with epoxy molding compound to predetermined portions of the leads 130 and 135 to which the conductive wires 140 and 145 are connected, and the epoxy molding compound is cured. As shown in FIG. 2, the molding 150 is formed outside the semiconductor chips 110 and 120.

여기서, 몰딩공정이 완료된 후에 각 반도체 칩들(110,120)을 기준으로 멀티 칩 패키지(100)를 분할하여 낱개의 반도체 칩 패키지를 형성할 필요성이 있을 경우에 몰딩물(150)을 절단하기 위해서 도 2에 도시된 바와 같이 몰딩물(150)의 중앙부분, 즉 반도체 칩들(110,120) 사이에 절단홈(155)을 형성하는데, 절단홈(155)은 상부금형(미도시)과 하부금형(미도시)의 중앙부분에 소정높이의 돌출부를 형성하여 몰딩공정을 진행 중에 형성하는 것이다.Here, in order to cut the molding 150 when it is necessary to form a single semiconductor chip package by dividing the multi chip package 100 based on the semiconductor chips 110 and 120 after the molding process is completed, FIG. As shown, the cutting groove 155 is formed between the center portion of the molding 150, that is, between the semiconductor chips 110 and 120, and the cutting groove 155 is formed of the upper mold (not shown) and the lower mold (not shown). Protruding portions of a predetermined height are formed in the central portion to form the molding process in progress.

이와 같이 반도체 칩들(110,120)의 외부에 몰딩물(150)이 형성되면, 댐바(미도시)를 절단하는 트리밍 공정과 각 리드들(130,135)을 소정의 형상으로 절곡하는 포밍공정을 진행함으로써 멀티 칩 패키지(100)를 형성한다.As described above, when the molding 150 is formed outside the semiconductor chips 110 and 120, a trimming process of cutting a dam bar (not shown) and a forming process of bending the leads 130 and 135 to a predetermined shape are performed. The package 100 is formed.

만약, 반도체 칩들(110,120)을 기준으로 몰딩물(150)을 절단하여 멀티 칩 패키지(100)를 낱개의 반도체 칩 패키지로 분리할 필요성이 있거나, 테스트 결과 2개의 반도체 칩들(110,120) 중 어느 하나의 반도체 칩에 불량이 발생된 경우에는 몰딩물(150)의 중앙부분에 형성된 절단홈(155)을 기준으로 몰딩물(150)을 절단하여 하나의 반도체 칩과 복수개의 리드들을 갖는 낱개의 반도체 칩을 형성한다.If the molding 150 is cut based on the semiconductor chips 110 and 120, it is necessary to separate the multi-chip package 100 into individual semiconductor chip packages, or, as a result of the test, any one of the two semiconductor chips 110 and 120 may be used. When a defect occurs in the semiconductor chip, the molding 150 is cut based on the cutting groove 155 formed in the center of the molding 150 to obtain a single semiconductor chip having a single semiconductor chip and a plurality of leads. Form.

이상에서 설명한 바와 같이 크기가 서로 비슷하고 본딩패드들이 서로 대칭이 되도록 형성된 2개의 반도체 칩을 수평으로 배열하여 멀티 칩 패키지를 형성하면, 서로 동일한 크기 또는 서로 비슷한 크기를 가진 반도체 칩으로도 멀티 칩 패키지를 형성할 수 있어 멀티 칩 패키지를 조립할 수 있는 반도체 칩들의 선택의 폭이 넓어진다.As described above, when two semiconductor chips having similar sizes and bonding pads formed to be symmetrical to each other are horizontally arranged to form a multi-chip package, a multi-chip package may also be used as semiconductor chips having the same size or similar size to each other. It is possible to form a wide range of choice of semiconductor chips that can assemble a multi-chip package.

그리고, 서로 수평으로 배열된 2개의 반도체 칩들 중 어느 하나의 반도체 칩에 불량이 발생된 경우 2개의 반도체 칩들 사이에 형성된 갭과 대응되는 부분을 절단하여 멀티 칩 패키지를 낱개의 반도체 칩 패키지로 분리할 수 있어 제품의 생산성을 향상시킬 수 있는 효과가 있다.When a defect occurs in one of the two semiconductor chips arranged horizontally with each other, a portion corresponding to a gap formed between the two semiconductor chips may be cut to separate the multi-chip package into a single semiconductor chip package. It can have the effect of improving the productivity of the product.

Claims (3)

서로 비슷한 크기를 갖고 폭방향 일측에 본딩패드들이 형성되며, 상기 본딩패드들이 서로 인접한 방향에 놓이도록 수평으로 배열되는 적어도 2개 이상의 반도체 칩들;At least two semiconductor chips having similar sizes to each other and having bonding pads formed at one side in a width direction thereof, and arranged horizontally such that the bonding pads are disposed adjacent to each other; 상기 본딩패드들과 소정간격 이격되어 각각의 상기 반도체 칩들의 상부면에 부착되며 외부단자와 상기 반도체 칩들을 전기적으로 연결시키는 리드들;Leads connected to an upper surface of each of the semiconductor chips at predetermined intervals from the bonding pads and electrically connecting an external terminal to the semiconductor chips; 일단이 상기 본딩패드들에 본딩되고, 타단이 상기 리드들과 본딩되어 상기 반도체 칩들 각각과 상기 리드들을 전기적으로 연결시키는 도전성 재질의 와이어들; 및Conductive wires having one end bonded to the bonding pads and the other end bonded to the leads to electrically connect each of the semiconductor chips to the leads; And 상기 반도체 칩들과 와이어들 및 상기 리드들의 소정부분을 감싸고 있어 이들을 외부환경으로부터 보호하는 몰딩물을 포함하는 것을 특징으로 하는 멀티 칩 패키지.And a molding covering the semiconductor chips, wires, and predetermined portions of the leads to protect the semiconductor chips, wires, and leads from the external environment. 제 1 항에 있어서, 상기 몰딩물 중 상기 반도체 칩들 사이에는 하나의 상기 반도체 칩과 상기 리드프레임을 갖도록 상기 몰딩물을 절단하기 위한 절단홈이 소정깊이로 형성되는 것을 특징으로 하는 멀티 칩 패키지.The multi-chip package according to claim 1, wherein a cutting groove for cutting the molding is formed between the semiconductor chips of the molding to have one of the semiconductor chip and the lead frame. 제 1 항에 있어서, 상기 반도체 칩들은 웨이퍼 상태에서 인접한 열에 형성된 반도체 칩들의 본딩패드들이 서로 대칭이되도록 형성되며, 상기 본딩패드들이 대칭이 되는 적어도 2개 이상의 반도체 칩들은 웨이퍼로부터 하나로 절단되는 것을 특징으로 하는 멀티칩 패키지.The method of claim 1, wherein the semiconductor chips are formed such that bonding pads of semiconductor chips formed in adjacent rows in a wafer state are symmetrical with each other, and at least two semiconductor chips whose symmetrical bonding pads are symmetrical are cut into one from a wafer. Multichip package.
KR1019990047364A 1999-10-29 1999-10-29 Multi chip package KR20010039115A (en)

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