KR20010038119A - Mold apparatus for BGA package - Google Patents
Mold apparatus for BGA package Download PDFInfo
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- KR20010038119A KR20010038119A KR1019990045987A KR19990045987A KR20010038119A KR 20010038119 A KR20010038119 A KR 20010038119A KR 1019990045987 A KR1019990045987 A KR 1019990045987A KR 19990045987 A KR19990045987 A KR 19990045987A KR 20010038119 A KR20010038119 A KR 20010038119A
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- South Korea
- Prior art keywords
- package
- molding
- circuit board
- printed circuit
- molding apparatus
- Prior art date
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- 238000000465 moulding Methods 0.000 claims abstract description 73
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims description 18
- 239000011347 resin Substances 0.000 claims description 18
- 239000004593 Epoxy Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229920006336 epoxy molding compound Polymers 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 15
- 239000002184 metal Substances 0.000 description 4
- 210000000988 bone and bone Anatomy 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체 칩 패키지 제조에 사용되는 성형 장치에 관한 것으로서, 더욱 상세하게는 전기적인 동작의 신뢰성을 확보하기 위하여 반도체 칩 패키지를 봉지하는 BGA 패키지 몰딩 장치에 관한 것이다.The present invention relates to a molding apparatus used for manufacturing a semiconductor chip package, and more particularly, to a BGA package molding apparatus for encapsulating a semiconductor chip package in order to ensure the reliability of electrical operation.
오늘날 전자산업의 추세는 더욱 경량화, 소형화, 고속화, 다기능화, 고성능화 되고 높은 신뢰성을 갖는 제품을 저렴하게 제조하는 것이다. 이와 같은 제품 설계의 목표 달성을 가능하게 하는 중요한 기술 중의 하나가 바로 패키지 조립 기술이며, 이에 따라 근래에 개발된 패키지 중의 하나가 볼 그리드 어레이(BGA; Ball Grid Array) 패키지이다.The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the important technologies that enables the achievement of the goal of product design is package assembly technology. Accordingly, one of the packages developed in recent years is a ball grid array (BGA) package.
BGA 패키지는 일반적인 플라스틱 패키지와 달리 리드 프레임(lead frame) 대신에 인쇄회로기판을 사용한다. 인쇄회로기판은 반도체 칩이 접착되는 면의 반대쪽 전면(全面)을 솔더 볼(solder ball)들을 배치할 수 있는 영역으로 제공할 수 있기 때문에, 모기판(mother board)에 대한 실장 면적 축소와 우수한 전기적 특성 등 많은 장점들을 갖고 있다.Unlike conventional plastic packages, BGA packages use printed circuit boards instead of lead frames. The printed circuit board can provide the entire surface opposite to the surface where the semiconductor chip is bonded to the area where solder balls can be placed, thereby reducing the mounting area for the mother board and providing excellent electrical performance. It has many advantages including its characteristics.
이와 같은 BGA 패키지는 물리적 또는 화학적인 외부환경으로부터 동착에 대한 신뢰성 확보를 위하여 반도체 칩과 그와 전기적으로 연결된 부분들이 에폭시 성형 수지(epoxy molding compound)와 같은 수지 봉지재로 봉지되어 있다. 이러한 공정을 몰딩(molding) 공정이라 한다.In such a BGA package, the semiconductor chip and its electrically connected parts are encapsulated with a resin encapsulation material such as an epoxy molding compound to secure reliability of the adhesion from a physical or chemical external environment. This process is called a molding process.
몰딩 공정은 패키지 외형에 적합한 형태의 캐버티(cavity)가 형성된 성형 금형을 갖는 몰딩 장치를 이용하게 된다. 몰딩 장치에 반도체 칩이 실장된 인쇄회로기판을 개재한 상태에서 성형 수지 타블렛을 용융시켜 겔 상태로 만들어 캐버티로 공급한 후 경화시키게 된다. 이 몰딩 장치는 패키지 형태 또는 핀 수 등에 따라 서로 각기 다른 패키지 형태의 캐버티가 형성된 성형 금형을 구비하벼 패키지 형태가 변화될 경우에 그에 적합한 성형 금형으로 교체하여 줄 수 있도록 구성된다.The molding process utilizes a molding apparatus having a molding die in which a cavity of a shape suitable for package appearance is formed. The molded resin tablet is melted in a state in which a molded resin tablet is melted through a printed circuit board on which a semiconductor chip is mounted in a molding apparatus, and then fed into a cavity and cured. The molding apparatus has a molding die in which cavities of different packages are formed according to the package type or the number of pins, and is configured to be replaced with a molding die suitable for a change in the package shape.
도 1은 종래 기술에 따른 BGA 패키지용 몰딩 장치에 의해 몰딩이 진행되는 상태를 나타낸 개략 단면도이고, 도 2는 종래 기술에 따른 BGA 패키지용 몰딩 장치에 의해 몰딩이 완료후에 소잉 공정이 진행되는 상태를 나타낸 개략 단면도이다.1 is a schematic cross-sectional view illustrating a molding process performed by a molding apparatus for a BGA package according to the prior art, and FIG. 2 illustrates a state in which a sawing process is performed after molding is completed by a molding apparatus for a BGA package according to the prior art. It is a schematic sectional drawing shown.
도 1과 도 2를 참조하여 BGA 패키지용 몰딩 장치(110)를 소개하기로 한다. 여기서, BGA 패키지용 몰딩 장치(110)는 단일 인쇄회로기판(122)에 복수의 반도체 칩(121)을 실장한 후 반도체 칩(121)이 모두 봉지되도록 하여 단일 패키지 형태로 만들어주는 형태의 것으로서, 후속으로 이어지는 소잉(sawing) 공정을 통하여 여러 개의 단위 BGA 패키지(120)로 분할하게 된다.Referring to FIGS. 1 and 2, a molding apparatus 110 for a BGA package will be introduced. Here, the BGA package molding apparatus 110 is a type of forming a single package form by mounting a plurality of semiconductor chips 121 on a single printed circuit board 122 so that all the semiconductor chips 121 are sealed. Subsequently, the sawing process is divided into several unit BGA packages 120.
이 BGA 패키지용 몰딩 장치(110)는 반도체 칩(121)이 실장된 인쇄회로기판(122)이 놓여지는 패키지 탑재대(111)와 반도체 칩(121)의 봉지에 적합한 형태의 캐버티(113)가 형성된 성형 금형(112)을 구비하고 있다. 복수의 반도체 칩(121)이 실장된 인쇄회로기판(122)을 탑재대 상부에 고정시킨 상태에서 성형 금형(112)이 인쇄회로기판(122) 상부의 공간을 외부와 차단한 상태에서 그 공간에 에폭시 성형 수지(125)를 주입한 후 경화시키게 된다. 수지 성형이 완료된 패키지는 다시 소잉 휠(sawing wheel;150)을 이용한 소잉 공정을 거치면서 구성된 셀의 디자인 및 패키지의 크기에 따라 소잉 공정에서 절단된다.The molding apparatus 110 for a BGA package has a cavity 113 having a shape suitable for encapsulating the semiconductor package 121 and the package mounting table 111 on which the printed circuit board 122 on which the semiconductor chip 121 is mounted is placed. Is provided with a molding die 112. In a state in which the printed metal circuit board 122 on which the plurality of semiconductor chips 121 are mounted is fixed to the upper portion of the mounting table, the molding die 112 blocks the space above the printed circuit board 122 from the outside, and then, in the space. The epoxy molding resin 125 is injected and then cured. After the resin molding is completed, the package is cut in the sawing process according to the size of the package and the design of the configured cell while going through the sawing process using a sawing wheel 150.
그러나, 소잉 공정의 진행 중에 패키지 두께가 1㎜되지 않는 얇은 상태에서 소잉 휠의 절단 작업시 브레이크 버어(break burr)의 발생 및 패키지와 반도체 칩 간의 들뜸 문제 등의 발생으로 인하여 신뢰성 저하 및 품질 저하의 원인이 되게 한다.However, during the sawing process, when the sawing wheel is cut in a thin state in which the thickness of the package is not 1 mm, the occurrence of break burrs and lifting problems between the package and the semiconductor chip may occur due to occurrence of break burrs. Cause.
본 발명의 목적은 소잉 휠 절단 작업시 인쇄회로기판과 에폭시 성형 수지간의 계면 접착력 약화에 의한 들뜸을 최소화하고 소잉이 완료된 사각 구성의 패키지 에지 부분이 날카롭기 때문에 미세한 충격 또는 사용자의 취급에 의한 들뜸 현상이 발생하지 않도록 하는 BGA 패키지용 몰딩 장치를 제공하는 데 있다.The object of the present invention is to minimize the lifting due to the weakening of the interfacial adhesion between the printed circuit board and the epoxy molding resin when cutting the sawing wheel, and because the edge of the package has a sharp edge and the sharp edge of the package is lifted due to the minute impact or the handling of the user. The present invention provides a molding apparatus for a BGA package that does not occur.
도 1은 종래 기술에 따른 비지에이(BGA; Ball Grid Array) 패키지용 몰딩 장치에 의해 몰딩이 진행되는 상태를 나타낸 개략 단면도,1 is a schematic cross-sectional view showing a state that molding is performed by a molding apparatus for a ball grid array (BGA) package according to the prior art;
도 2는 종래 기술에 따른 BGA 패키지용 몰딩 장치에 의해 몰딩이 완료후에 소잉 공정이 진행되는 상태를 나타낸 개략 단면도,2 is a schematic cross-sectional view showing a state in which a sawing process is performed after molding is completed by a molding apparatus for BGA packages according to the prior art;
도 3은 본 발명에 따른 BGA 패키지용 몰딩 장치에 의해 몰딩이 진행되는 상태를 나타낸 개략 단면도,Figure 3 is a schematic cross-sectional view showing a state in which molding proceeds by the molding apparatus for BGA package according to the present invention,
도 4는 본 발명에 따른 BGA 패키지용 몰딩 장치에 의해 몰딩이 완료후에 소잉 공정이 진행되는 상태를 나타낸 개략 단면도,4 is a schematic cross-sectional view showing a state in which a sawing process is performed after molding is completed by a molding apparatus for BGA packages according to the present invention;
도 5는 본 발명에 따른 BGA 패키지용 몰딩 장치에 의해 제조된 반도체 칩 패키지의 평면도이다.5 is a plan view of a semiconductor chip package manufactured by a molding apparatus for a BGA package according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; BGA 패키지용 몰딩 장치 11; 탑재대10; Molding device 11 for BGA package; Mount
12; 성형 금형 13; 캐버티(cavity)12; Molding mold 13; Cavity
14; 돌출부 20; BGA 패키지14; Protrusion 20; BGA Package
21; 반도체 칩 22; 인쇄회로기판21; Semiconductor chip 22; Printed circuit board
23; 도전성 금속선 25; 에폭시 성형 수지23; Conductive metal wire 25; Epoxy molding resin
25a; 경사면 26; 골25a; Slope 26; goal
50; 소잉 휠(sawing wheel)50; Sawing wheel
상기 목적을 달성하기 위한 본 발명에 따른 BGA 패키지용 몰딩 장치는 복수의 반도체 칩이 실장된 인쇄회로기판을 단일 패키지 형태로 몰딩하고 절단에 의해 단위 패키지로 제조되는 BGA 패키지 제조에 적용되는 몰딩 장치로서, 인쇄회로기판이 놓여지는 탑재대와, 인쇄회로기판의 상부를 에폭시 성형 수지가 공급되는 공간을 형성하도록 캐버티가 형성된 성형 금형을 구비하는 BGA 패키지용 몰딩 장치에 있어서, 상기 성형 금형은 소잉 라인에 대응되는 위치에 돌출되어 형성된 돌출부를 갖는 것을 특징으로 한다.The molding apparatus for BGA package according to the present invention for achieving the above object is a molding apparatus that is applied to the production of a BGA package manufactured by molding a printed circuit board mounted with a plurality of semiconductor chips in the form of a single package and manufactured as a unit package by cutting. A molding apparatus for a BGA package having a mounting table on which a printed circuit board is placed, and a molding die having a cavity formed on the upper portion of the printed circuit board to form a space for supplying an epoxy molding resin, wherein the molding die is a sawing line. It characterized in that it has a protrusion formed to protrude at a position corresponding to.
이하 첨부 도면을 참조하여 본 발명에 따른 BGA 패키지용 몰딩 장치를 보다 상세하게 설명하고자 한다.Hereinafter, a molding apparatus for a BGA package according to the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 BGA 패키지용 몰딩 장치에 의해 몰딩이 진행되는 상태를 나타낸 개략 단면도이고, 도 4는 본 발명에 따른 비지에이 패키지용 몰딩 장치에 의해 몰딩이 완료후에 소잉 공정이 진행되는 상태를 나타낸 개략 단면도이며, 도 5는 본 발명에 따른 지비에이 패키지용 몰딩 장치에 의해 제조된 반도체 칩 패키지의 평면도이다.3 is a schematic cross-sectional view showing a molding process by the molding apparatus for BGA package according to the present invention, Figure 4 is a state in which the sawing process is carried out after the molding is completed by a molding apparatus for a BGA package according to the present invention 5 is a plan view of a semiconductor chip package manufactured by a molding apparatus for a GB package according to the present invention.
도 3내지 도 5를 참조하면, 본 발명에 따른 몰딩 장치(10)는 반도체 칩(21)이 실장된 인쇄회로기판(22)을 단일 패키지 형태로 몰딩하고 절단에 의해 단위 패키지로 제조되는 BGA 패키지 제조에 적용되는 것으로 탑재대(11)와 성형 금형(12)을 구비하고 있다.3 to 5, the molding apparatus 10 according to the present invention is a BGA package manufactured by molding a printed circuit board 22 on which the semiconductor chip 21 is mounted into a single package, and manufacturing the unit package by cutting. Applied to manufacture, the mounting table 11 and the molding die 12 are provided.
복수의 단위 패키지 영역을 갖는 단일 인쇄회로기판(22)에는 각각의 영역에 복수의 반도체 칩(21)이 실장되어 있다. 반도체 칩(21)과 인쇄회로기판(22)는 도전성 금속선(23)에 의해 와이어 본딩(wire bonding)으로 접합되어 전기적으로 연결되어 있다. 탑재대(11)는 이와 같은 상태의 인쇄회로기판(22)이 수지 성형을 위하여 탑재되어 공정이 진행될 때 인쇄회로기판(22)을 지지하게 된다.In a single printed circuit board 22 having a plurality of unit package regions, a plurality of semiconductor chips 21 are mounted in each region. The semiconductor chip 21 and the printed circuit board 22 are bonded by wire bonding by the conductive metal wires 23 and electrically connected thereto. The mounting table 11 supports the printed circuit board 22 when the printed circuit board 22 in this state is mounted for resin molding and the process proceeds.
성형 금형(12)은 복수의 반도체 칩(21)이 실장된 인쇄회로기판(22)을 단일 패키지 형태로 수지 성형할 수 있도록 내부에 캐버티(13)가 형성되어 있다. 그리고, 성형 금형(12)의 캐버티(13)에는 도 3에서 일점쇄선으로 도시된 바와 같은 각각의 반도체 칩(21)이 실장된 인쇄회로기판(22)으로 절단하기 위한 소잉 라인(sawing line)에 대응되는 위치에 각각 소정의 높이로 돌출부(14)가 형성되어 있다. 이때, 각각의 돌출부(14)는 소정의 각을 갖는 경사면으로 형성되어 있고, 돌출부(22)의 하단 폭이 소잉 휠(50)의 두께보다는 크도록 되어 있으며, 돌출부(22)의 말단 폭이 그 하단의 폭보다 좁도록 되어 있다.In the molding die 12, a cavity 13 is formed therein so that the printed circuit board 22 on which the plurality of semiconductor chips 21 are mounted may be resin molded in a single package. In addition, a sawing line for cutting into a printed circuit board 22 in which each semiconductor chip 21 as shown by a dashed-dotted line in FIG. 3 is mounted in the cavity 13 of the molding die 12. The protrusions 14 are formed at predetermined heights at positions corresponding to the respective positions. At this time, each of the protrusions 14 is formed of an inclined surface having a predetermined angle, the bottom width of the protrusion 22 is larger than the thickness of the sawing wheel 50, the end width of the protrusion 22 is It is narrower than the width of the bottom.
복수의 반도체 칩(21)이 탑재되어 있는 인쇄회로기판(22)이 탑재대(11)에 놓여지면 성형 금형(12)이 그 상부를 밀폐하여 에폭시 성형 수지(25)를 주입시키게 된다. 주입된 에폭시 성형 수지(25)는 경화되어 반도체 칩(21)과 도전성 금속선(23) 및 접합 부위를 봉지한다.When the printed circuit board 22 on which the plurality of semiconductor chips 21 are mounted is placed on the mounting table 11, the molding die 12 seals the upper portion thereof to inject the epoxy molding resin 25. The injected epoxy molding resin 25 is cured to encapsulate the semiconductor chip 21, the conductive metal wire 23, and the bonding portion.
봉지가 완료되면 단일 패키지 형태가 되며, 인쇄회로기판(22)의 상부에 경화된 에폭시 성형 수지(25)는 소잉 라인 부분에 골(26)이 형성되며, 소잉 휠(50)으로 소잉 라인을 따라 절단하게 된다. 이때, 이미 어느 정도 깊이로 골(26)이 파여져 있기 때문에 소잉 휠(50)이 골(26) 부분을 절단시키게 되며 인쇄회로기판(22)과 에폭시 성형 수지(25)에 전달되는 충격은 종래에 비하여 크게 감소된다. 절단이 완료되면 단일 패키지 형태로부터 각각의 단위 BGA 패키지(20)가 분할되어 완성된다. 완성되는 BGA 패키지(20)는 도 5에서와 같이 모서리 부분에 소정의 각을 이루는 경사면(25a)이 형성된다.When the encapsulation is completed, a single package is formed, and the epoxy molding resin 25 cured on the upper portion of the printed circuit board 22 is formed with a valley 26 at a sawing line portion, and along the sawing line with the sawing wheel 50. Will cut. At this time, since the bone 26 is already dug to a certain depth, the sawing wheel 50 cuts the portion of the bone 26, and the impact transmitted to the printed circuit board 22 and the epoxy molding resin 25 is conventional. It is greatly reduced. When the cutting is completed, each unit BGA package 20 is divided and completed from a single package form. The finished BGA package 20 is formed with an inclined surface 25a having a predetermined angle at a corner portion as shown in FIG. 5.
위의 실시예에서와 같이 본 발명에 따른 BGA 패키지용 몰딩 장치는 캐버티가 형성된 상부 금형에 소정의 경사각을 이루도록 하여 소잉 라인을 따라 돌출부가 형성되어 있어서, 에폭시 성형 수지가 경화될 때 음각으로 일정한 경사면을 갖는 골이 형성된다. 이에 의해 소잉 휠로부터 인쇄회로기판 또는 에폭시 성형 수지에 전달되는 충격이 크게 줄어들고, 최종적으로 얻어지는 단위 BGA 패키지는 모서리 부분에 경사면이 형성되어 취급시 걸림을 방지한다.As in the above embodiment, the molding apparatus for the BGA package according to the present invention has a protrusion formed along a sawing line so as to form a predetermined inclination angle in the upper mold in which the cavity is formed, so that when the epoxy molding resin is cured negatively constant A valley with a slope is formed. As a result, the impact transmitted from the sawing wheel to the printed circuit board or the epoxy molding resin is greatly reduced, and the finally obtained unit BGA package has an inclined surface formed at a corner thereof to prevent a jam during handling.
이상과 같은 본 발명에 의한 BGA 패키지용 몰딩 장치에 따르면, 소잉 라인을 따라 음각으로 골이 형성되어 있기 때문에 소잉 공정이 진행될 때 충격이 감소되어 인쇄회로기판과 에폭시 성형 수지간의 계면 접착력이 손상되는 것을 방지하여 들뜸을 최소화할 수 있고, 소잉이 완료된 패키지의 모서리 부분이 날카롭지 않고 소정의 각도로 각을 갖고 형성되어 사용자의 취급에 의한 패키지 손상을 방지할 수 있다. 이에 따라, 작업성의 향상 및 안정적인 품질의 공급이 가능하다.According to the molding apparatus for BGA package according to the present invention as described above, since the bone is formed in the intaglio along the sawing line, the impact is reduced when the sawing process proceeds to damage the interface adhesion between the printed circuit board and the epoxy molding resin It can be prevented by minimizing the lifting, and the corner portion of the sawing is not sharp but formed at an angle at a predetermined angle to prevent damage to the package by the user's handling. Accordingly, it is possible to improve workability and supply stable quality.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990045987A KR20010038119A (en) | 1999-10-22 | 1999-10-22 | Mold apparatus for BGA package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990045987A KR20010038119A (en) | 1999-10-22 | 1999-10-22 | Mold apparatus for BGA package |
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| KR20010038119A true KR20010038119A (en) | 2001-05-15 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008044813A1 (en) * | 2006-10-10 | 2008-04-17 | Bse Co., Ltd | An apparatus and a method of producing for microphone assembly |
| CN106653655A (en) * | 2016-12-01 | 2017-05-10 | 无锡吉迈微电子有限公司 | Plastic packaging mold for achieving rewiring of multi-chip pins and technique |
| WO2020166814A1 (en) * | 2019-02-11 | 2020-08-20 | (주)실리콘인사이드 | Led pixel package comprising active pixel ic, and manufacturing method therefor |
| KR20200108617A (en) * | 2019-03-11 | 2020-09-21 | 주식회사 루멘스 | METHOD FOR MAKING CSP LEDs |
| WO2023008726A1 (en) * | 2021-07-30 | 2023-02-02 | 엘지전자 주식회사 | Light emitting element package manufacturing method, display apparatus, and display apparatus manufacturing method |
-
1999
- 1999-10-22 KR KR1019990045987A patent/KR20010038119A/en not_active Application Discontinuation
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008044813A1 (en) * | 2006-10-10 | 2008-04-17 | Bse Co., Ltd | An apparatus and a method of producing for microphone assembly |
| JP2008099256A (en) * | 2006-10-10 | 2008-04-24 | Bse Co Ltd | Apparatus and method of fabricating microphone assembly |
| JP4727631B2 (en) * | 2006-10-10 | 2011-07-20 | ビーエスイー カンパニー リミテッド | Microphone assembly manufacturing apparatus and manufacturing method |
| CN106653655A (en) * | 2016-12-01 | 2017-05-10 | 无锡吉迈微电子有限公司 | Plastic packaging mold for achieving rewiring of multi-chip pins and technique |
| WO2020166814A1 (en) * | 2019-02-11 | 2020-08-20 | (주)실리콘인사이드 | Led pixel package comprising active pixel ic, and manufacturing method therefor |
| KR20200097941A (en) * | 2019-02-11 | 2020-08-20 | (주)실리콘인사이드 | LED Pixel Package including Active Pixel IC and Method Thereof |
| KR20200108617A (en) * | 2019-03-11 | 2020-09-21 | 주식회사 루멘스 | METHOD FOR MAKING CSP LEDs |
| US11152544B2 (en) | 2019-03-11 | 2021-10-19 | Lumens Co., Ltd. | Methods for fabricating CSP LEDs |
| WO2023008726A1 (en) * | 2021-07-30 | 2023-02-02 | 엘지전자 주식회사 | Light emitting element package manufacturing method, display apparatus, and display apparatus manufacturing method |
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