KR100253388B1 - Method for fabricating semiconductor package - Google Patents

Method for fabricating semiconductor package Download PDF

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Publication number
KR100253388B1
KR100253388B1 KR1019970072868A KR19970072868A KR100253388B1 KR 100253388 B1 KR100253388 B1 KR 100253388B1 KR 1019970072868 A KR1019970072868 A KR 1019970072868A KR 19970072868 A KR19970072868 A KR 19970072868A KR 100253388 B1 KR100253388 B1 KR 100253388B1
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South Korea
Prior art keywords
lead frame
package
mold
strips
cavity
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KR1019970072868A
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Korean (ko)
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KR19990053262A (en
Inventor
김선동
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김영환
현대반도체주식회사
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Priority to KR1019970072868A priority Critical patent/KR100253388B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: A method for manufacturing a semiconductor package of a bottom lead type is provided to improve productivity and to prevent occurrence of mold flash. CONSTITUTION: In the method, a plurality of semiconductor chips(1) are attached and wire-bonded to a lead frame strip(3). Such lead frame strips(3) with chips(1) are then inserted into a cavity of a mold die(30) with an intermediate separating bar(20) lying across the cavity. Particularly, some of the lead frame strips(3) are disposed above the separating bar(20) and others below. Next, an epoxy(10) is injected into the cavity thereby to form molded package strips. Thereafter, the molded package strips including the lead frame strips(3) are separated from the separating bar(20) as well as the mold die(30). An exposed portion of the lead frame strips(3) is then plated. Finally, the molded package strips are divided into individual unit packages.

Description

반도체 패키지의 제조방법Manufacturing method of semiconductor package

본 발명은 반도체 패키지의 제조방법에 관한 것으로, 특히 생산성은 향상되고 경박 단소화에 적합한 반도체 패키지의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor package, and more particularly, to a method of manufacturing a semiconductor package, which has improved productivity and is suitable for light and thin reduction.

최근들어 각종 전자제품들이 소형화 및 다기능화되어 가면서 반도체 패키지 역시 경박단소화 및 고집적화된 제품들을 요구하게 되는 바, 이러한 요구에 부흥하기 위하여 통상 비엘피 패키지라고 불리우는 버텀리드형 패키지가 제안되어 왔다.In recent years, as various electronic products have been miniaturized and multifunctional, semiconductor packages have also been required to be lighter, shorter, and more highly integrated. Accordingly, a bottom-lead package, commonly referred to as a BLP package, has been proposed to meet such demands.

일반적인 버텀리드형 패키지(이하, 비엘피 패키지로 통칭함)는 도1에 도시된 바와 같이, 반도체 칩(1)과, 그 반도체 칩(1)의 저면 양측에 절연접착제(2)로 부착되고 소정위치에서 절곡되어 상기 칩(1)과 평행하게 배치되는 리드프레임(3)과, 그 리드프레임(3)의 대향부위 저면과 상기 칩(1)의 패드(1a) 를 전기적으로 연결시켜주는 골드 와이어(4)와, 상기 칩(1)의 외부로부터의 열적, 기계적, 화학적 충격을 보호하기 위하여 에폭시(EMC; Epoxy Molding Compound)로 몰딩되는 봉지부(5)로 구성되어 있다.A general bottom lead type package (hereinafter, referred to as a BLP package) is a semiconductor chip 1 and attached to both sides of the bottom surface of the semiconductor chip 1 with an insulating adhesive 2 as shown in FIG. A gold wire which is bent at a position and arranged in parallel with the chip 1, and electrically connects the lead frame 3, the bottom surface of the opposite portion of the lead frame 3, and the pad 1a of the chip 1. (4) and an encapsulation portion 5 molded with epoxy (Epoxy Molding Compound) in order to protect thermal, mechanical and chemical impacts from the outside of the chip 1.

상기 리드프레임(3)은 그 저면의 일부가 봉지부(5)로부터 노출되고, 그 노출된 리드프레임의 저면에는 인쇄회로기판(PCB)의 랜드와 접촉되는 외부단자용 도금부(이하, 전기단자와 혼용함)(3a)가 형성된다.The lead frame 3 has a portion of its bottom surface exposed from the encapsulation portion 5, and a plating portion for an external terminal (hereinafter referred to as an electric terminal) which contacts a land of a printed circuit board (PCB) on the bottom surface of the exposed lead frame. 3a) is formed.

상기와 같은 종래의 비엘피 패키지를 제조하기 위한 방법은 도2a 내지 도2f에 도시된 바와 같다.The method for manufacturing the conventional BLP package as described above is as shown in FIGS. 2A to 2F.

즉, 반도체 칩(1)의 저면 양측에 절연접착제(2)로 리드프레임(3)의 일측 상면을 대향되게 부착하고, 그 각 리드프레임(3)의 대향부 저면과 반도체 칩(1)의 패드(1a)는 골드 와이어(4)로 본딩하여 전기적으로 연결시킨 후에 소정형상의 금형(6)에 얹고 에폭시로 몰딩하여 봉지부(5)를 형성하는데, 여기서 상기 금형은 도2d에 도시된 바와 같이, 금형(6)의 캐비티 상, 하면이 각각 칩(1)의 상면 및 리드프레임(3)의 저면과 밀착되지 않도록 하여 상기 봉지부(5)가 칩(1)의 상면을 완전히 밀봉하도록 설계되어 있다.That is, the upper surface of one side of the lead frame 3 is attached to both sides of the bottom surface of the semiconductor chip 1 with the insulating adhesive 2 so as to face each other, and the bottom surface of the opposing portion of each lead frame 3 and the pad of the semiconductor chip 1. (1a) is bonded with a gold wire (4) and electrically connected to it, then placed on a mold 6 of a predetermined shape and molded with epoxy to form an encapsulation portion 5, where the mold is shown in Fig. 2d. The encapsulation portion 5 is designed to completely seal the upper surface of the chip 1 by preventing the upper and lower surfaces of the cavity 6 from contacting the upper surface of the chip 1 and the lower surface of the lead frame 3, respectively. have.

다음, 상기의 몰딩공정이 끝난 패키지의 리드프레임(3) 노출부위에 부착된 몰드 프레쉬(Mold Flash)(미도시)를 제거한 이후에 그 리드프레임(3)의 노출면에 전기도금을 실시하고, 이러한 플래팅(Plating)공정이 완료되면, 트리밍(Trimming)공정을 통해 각 패키지를 상호 연결시키고 있는 아웃리드를 절단하여 비엘피 패키지를 완성하는 것이었다.Next, after removing the mold flash (not shown) attached to the exposed portion of the lead frame 3 of the package after the molding process, electroplating is performed on the exposed surface of the lead frame 3, When the plating process was completed, the trimming process was performed to cut out leads that interconnect each package to complete the BLP package.

그러나, 상기와 같은 종래 비엘피 패키지의 제조방법에 있어서는, 리드프레임(3)에 칩(1)이 접착되어 골드와이어(4)가 본딩된 리드프레임 스트립(Lead Frame Strip)(미부호)이 단열(單列)형 금형(6)에 일렬로만 얹혀져 몰딩되므로, 한번의 몰딩공정으로는 단열의 패키지만을 생산하게 되어 생산성 향상에 제약이 뒤따르게 되는 것은 물론, 상기 칩(1)과 리드프레임(3)의 양측면이 금형(6)의 상, 하면에 밀착되지 못하여 밀봉공정중에 에폭시의 일부가 리드프레임(3)의 저면으로 스며들어 밀봉 후 디플레쉬 공정이 필요하게 되고, 또한, 봉지부(5)가 칩(1)을 완전히 밀봉하게 되어 패키지가 두꺼워지게 되는 문제점이 있었다.However, in the conventional method of manufacturing a BLP package, a lead frame strip (unsigned) in which a chip 1 is bonded to the lead frame 3 and the gold wire 4 is bonded is insulated. Since the mold (6) is mounted on the die (6) in a row, only one thermal insulation package is produced in a single molding process, which leads to a restriction in productivity improvement, as well as the chip (1) and the lead frame (3). Both sides of the mold 6 do not come into close contact with the upper and lower surfaces of the mold 6, and a part of the epoxy penetrates into the bottom surface of the lead frame 3 during the sealing process, so that a sealing and defreshing process is required. There is a problem that the package is thickened by completely sealing the chip (1).

따라서, 본 발명은 상기와 같은 종래 반도체 패키지의 제조방법이 가지는 문제점을 감안하여 안출한 것으로, 패키지의 생산성이 향상되는 것은 물론, 별도의 디플레쉬 공정이 불필요하며 경박단소한 패키지를 생산할 수 있는 반도체 패키지의 제조방법을 제공하려는데 그 목적이 있다.Accordingly, the present invention has been made in view of the problems of the conventional method of manufacturing a semiconductor package as described above, and the productivity of the package is improved, as well as the need for a separate de-processing process, a semiconductor that can produce a light and simple package It is an object of the present invention to provide a method for manufacturing a package.

도1은 종래 비엘피 패키지의 일례를 보인 종단면도.Figure 1 is a longitudinal sectional view showing an example of a conventional BLP package.

도2a 내지 도2f는 종래 비엘피 패키지를 제조하는 과정을 보인 종단면도.Figures 2a to 2f is a longitudinal sectional view showing a process of manufacturing a conventional BLP package.

도3은 본 발명에 의한 비엘피 패키지의 일례를 보인 종단면도.Figure 3 is a longitudinal sectional view showing an example of the BLP package according to the present invention.

도4a 내지 도4f는 본 발명에 의한 비엘피 패키지를 제조하는 과정을 보인 종단면도.Figures 4a to 4f is a longitudinal sectional view showing a process of manufacturing a BLP package according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 칩 2 : 접착제1: semiconductor chip 2: adhesive

3 : 리드프레임 4 : 골드와이어3: lead frame 4: gold wire

10 : 에폭시 20 : 이연성 분리대10: epoxy 20: flammable separator

30 : 금형30: Mold

이와 같은 본 발명의 목적을 달성하기 위하여, 리드프레임 스트립에 수개의 반도체 칩을 접착시키고, 각 반도체 칩의 패드와 리드프레임을 금속와이어로 각각 본딩하는 단계와; 상기 수개의 반도체 칩을 접착함과 아울러 금속와이어가 각각 본딩된 복수개의 리드프레임 스트립이 그 사이에 개재되는 이연성(離緣性) 분리대를 중심으로 서로 대칭되도록 금형의 캐비티에 삽입하는 단계와; 상기 금형의 캐비티에 몰딩재를 주입하여 패키지 스트립을 형성하도록 몰딩하는 단계와; 상기 몰딩재가 응고된 이후에 금형을 분리하고, 이연성 분리대의 양측면으로부터 패키지 스트립을 각각 분리하는 단계와; 상기 리드프레임의 노출면에 전기도금을 실시하고, 트리밍공정을 통해 각 패키지를 상호 연결시키고 있는 아웃리드를 절단하여 단품의 패키지를 완성하는 단계로 진행함을 특징으로 하는 반도체 패키지의 제조방법이 제공된다.In order to achieve the object of the present invention, bonding a plurality of semiconductor chips to the lead frame strip, and bonding the pad and lead frame of each semiconductor chip with a metal wire, respectively; Bonding the plurality of semiconductor chips and inserting the plurality of leadframe strips each of which is bonded with a metal wire into a cavity of the mold such that the plurality of leadframe strips are symmetrical with respect to a decoupled separator interposed therebetween; Molding to inject a molding material into the cavity of the mold to form a package strip; Separating the mold after the molding material is solidified, and separating the package strips from both sides of the flexible separator; Provided is a method of manufacturing a semiconductor package, characterized in that the electroplating on the exposed surface of the lead frame, and proceeds to cut the outlead that interconnects each package through a trimming process to complete a single package package do.

이하, 본 발명에 의한 반도체 패키지의 제조방법을 첨부도면에 도시된 일실시예에 의거하여 상세하게 설명한다.Hereinafter, a method of manufacturing a semiconductor package according to the present invention will be described in detail with reference to an embodiment shown in the accompanying drawings.

도3은 본 발명에 의한 비엘피 패키지의 일례를 보인 종단면도이고, 도4a 내지 도4f는 본 발명에 의한 비엘피 패키지를 제조하는 과정을 보인 종단면도이다.Figure 3 is a longitudinal cross-sectional view showing an example of a BLP package according to the present invention, Figures 4a to 4f is a longitudinal cross-sectional view showing a process of manufacturing a non-LP package according to the present invention.

이에 도시된 바와 같이 본 발명에 의한 반도체 패키지는, 도3에 도시된 바와 같이, 반도체 칩(1)과, 그 반도체 칩(1)의 저면 양측에 절연접착제(2)로 부착되고 소정위치에서 절곡되어 상기 칩(1)과 평행하게 배치되는 리드프레임(3)과, 그 리드프레임(3)의 대향부위 저면과 상기 칩(1)의 패드(1a)를 전기적으로 연결시켜주는 골드와이어(4)와, 상기 칩(1)을 외부로부터의 열적, 기계적, 화학적 충격을 보호하기 위하여 에폭시로 몰딩되는 봉지부(10)로 구성된다.As shown in FIG. 3, the semiconductor package according to the present invention, as shown in FIG. 3, is attached to the semiconductor chip 1 and the bottom surface of the semiconductor chip 1 with an insulating adhesive 2 and bent at a predetermined position. A gold wire 4 electrically connecting the lead frame 3 arranged in parallel with the chip 1, the bottom surface of the lead frame 3, and the pad 1a of the chip 1. And an encapsulation portion 10 molded with epoxy to protect the chip 1 from thermal, mechanical and chemical impacts from the outside.

상기 봉지부(10)의 일측은 리드프레임(3)의 저면이 노출되도록 형성되고, 타측은 반도체 칩(1)의 상면이 노출되도록 형성된다.One side of the encapsulation part 10 is formed so that the bottom surface of the lead frame 3 is exposed, and the other side is formed so that the top surface of the semiconductor chip 1 is exposed.

도면중 종래와 동일한 부분에 대하여는 동일한 부호를 부여하였다.In the drawings, the same reference numerals are given to the same parts as in the prior art.

도면중 미설명 부호인 3a는 외부단자이다.In the figure, 3a, which is not described, is an external terminal.

상기와 같은 본 발명의 비엘피 패키지를 제조하기 위한 방법은 도4a 내지 도4f에 도시된 바와 같다.The method for manufacturing the BLP package of the present invention as described above is as shown in Figures 4a to 4f.

즉, 반도체 칩(1)의 저면 양측에 절연접착제(2)로 리드프레임(3)의 일측 상면을 대향되게 부착하고, 그 각 리드프레임(3)의 대향부 저면과 반도체 칩(1)의 패드(1a)는 골드 와이어(4)로 본딩하여 전기적으로 연결시킨 후에 소정형상의 금형(6)에 얹고 에폭시로 몰딩하여 봉지부(5)를 형성하는데, 여기서 상기 수개의 반도체 칩(1)을 접착함과 아울러 골드 와이어(4)가 각각 본딩된 복수개의 리드프레임 스트립(미부호)을 그 사이에 개재되는 테프론 또는 폴리머와 같은 이연성(離緣性) 분리대(20)를 중심으로 서로 대칭되도록 금형(30)의 캐비티(미부호)에 삽입하고, 상기 금형(30)의 캐비티에 에폭시(10)를 주입하여 패키지 스트립(미부호)을 형성하도록 몰딩하며, 상기 에폭시가 응고된 이후에 금형(30)을 분리함과 아울러 이연성 분리대(20)의 양측면으로부터 패키지 스트립(미부호)을 각각 분리하고, 이어서 상기 리드프레임(3)의 노출면(3a)에 전기도금을 실시하며, 이러한 플래팅공정이 완료되면, 트리밍공정을 통해 각 패키지(미부호)를 상호 연결시키고 있는 아웃리드를 절단하여 단품의 비엘피 패키지를 완성하는 것이다.That is, the upper surface of one side of the lead frame 3 is attached to both sides of the bottom surface of the semiconductor chip 1 with the insulating adhesive 2 so as to face each other, and the bottom surface of the opposing portion of each lead frame 3 and the pad of the semiconductor chip 1. (1a) is bonded with a gold wire (4) and electrically connected, and then placed on a mold (6) of a predetermined shape and molded with epoxy to form an encapsulation portion (5), wherein the several semiconductor chips (1) are bonded together In addition, a plurality of lead frame strips (not shown) bonded to each of the gold wires 4 are formed so as to be symmetrical with respect to each other about a decoupling separator 20 such as Teflon or polymer interposed therebetween. 30 is inserted into a cavity (unsigned), and the epoxy 10 is injected into the cavity of the mold 30 to be molded to form a package strip (unsigned), and the mold 30 after the epoxy is solidified. The package from both sides of the flexible separator 20 Each trip (unsigned) is separated, and then electroplated on the exposed surface 3a of the lead frame 3, and when such a plating process is completed, each package (unsigned) is mutually processed through a trimming process. By cutting out the connecting leads, you can complete a single BLP package.

이때, 상기 리드프레임 스트립(미부호)을 금형(30)의 캐비티에 삽입하는 단계에서 각 리드프레임 스트립(미부호)의 반도체 칩(1) 일측면은 금형(30)의 캐비티 상,하 면에 밀착되는 반면, 각 리드프레임 스트립(미부호)의 리드프레임(3) 일측면은 이연성 분리대(20)의 상, 하면에 밀착되도록 삽입함이 바람직하다.At this time, in the step of inserting the lead frame strip (unsigned) into the cavity of the mold 30, one side of the semiconductor chip (1) of each lead frame strip (unsigned) on the upper and lower surfaces of the cavity of the mold (30) On the other hand, the one side of the lead frame 3 of each lead frame strip (unsigned) is preferably inserted in close contact with the upper and lower surfaces of the decoupling separator 20.

이로써, 한 번의 몰딩작업으로 두 개의 패키지 스트립(미부호)을 형성할 수 있으므로 생산성이 현저하게 향상되는 것은 물론, 리드프레임(3)과 칩(1)의 양측 배면이 상, 하로 눌리면서 몰딩되므로 리드프레임(3)의 배면에 플레쉬가 발생되지 않으며, 상기 칩(1)의 배면이 몰딩되지 않고 노출되므로 패키지의 경박단소화가 실현될 수 있다.As a result, since two package strips (unsigned) can be formed by one molding operation, productivity is remarkably improved, and both sides of the lead frame 3 and the chip 1 are molded while being pressed up and down, thereby leading to Since no flash is generated on the rear surface of the frame 3 and the rear surface of the chip 1 is exposed without being molded, light and small size reduction of the package can be realized.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 패키지의 제조방법은, 반도체 칩과 와이어를 에폭시로 보호하도록 몰딩하는 단계에서 그 몰딩하는 금형의 사이에 이연성 분리대를 대고, 그 이연성 분리대의 양측면에 각각 리드프레임 스트립을 밀착시킨 후에 에폭시를 주입하여 패키지 스트립을 형성함으로써, 한 번의 몰딩작업으로 두 개의 패키지 스트립을 형성할 수 있어 생산성이 현저하게 향상되는 것은 물론, 리드프레임과 칩의 양측 배면이 상, 하로 눌리면서 몰딩되므로 리드프레임의 배면에 플레쉬가 발생되지 않으며, 상기 칩의 배면이 몰딩되지 않고 노출되므로 패키지의 경박단소화가 실현될 수 있다.As described above, in the method of manufacturing a semiconductor package according to the present invention, in the step of molding the semiconductor chip and the wire with epoxy protection, a deformable separator is placed between the molds to be molded and lead frames are respectively provided on both sides of the deformable separator. By adhering the strips and then injecting epoxy to form the package strips, two package strips can be formed in one molding operation, which not only improves productivity, but also pushes both sides of the lead frame and chip up and down. Since molding does not cause flash on the rear surface of the lead frame, the back surface of the chip is exposed without being molded, thereby making it possible to reduce the thickness of the package.

Claims (2)

리드프레임 스트립에 수개의 반도체 칩을 접착시키고, 각 반도체 칩의 패드와 리드프레임을 금속와이어로 각각 본딩하는 단계와; 상기 수개의 반도체 칩을 접착함과 아울러 금속와이어가 각각 본딩된 복수개의 리드프레임 스트립이 그 사이에 개재되는 이연성(離緣性) 분리대를 중심으로 서로 대칭되도록 금형의 캐비티에 삽입하는 단계와; 상기 금형의 캐비티에 몰딩재를 주입하여 패키지 스트립을 형성하도록 몰딩하는 단계와; 상기 몰딩재가 응고된 이후에 금형을 분리하고, 이연성 분리대의 양측면으로부터 패키지 스트립을 각각 분리하는 단계와; 상기 리드프레임의 노출면에 전기도금을 실시하고, 트리밍(Trimming)공정을 통해 각 패키지를 상호 연결시키고 있는 아웃리드를 절단하여 단품의 패키지를 완성하는 단계로 진행함을 특징으로 하는 반도체 패키지의 제조방법.Bonding a plurality of semiconductor chips to a leadframe strip, and bonding pads and leadframes of each semiconductor chip with metal wires, respectively; Bonding the plurality of semiconductor chips and inserting the plurality of leadframe strips each of which is bonded with a metal wire into a cavity of the mold such that the plurality of leadframe strips are symmetrical with respect to a decoupled separator interposed therebetween; Molding to inject a molding material into the cavity of the mold to form a package strip; Separating the mold after the molding material is solidified, and separating the package strips from both sides of the flexible separator; Electroplating the exposed surface of the lead frame, and through the trimming process (Trimming) to cut the outread that interconnects each package to the step of completing a single package package manufacturing of a semiconductor package Way. 제1항에 있어서, 상기 리드프레임 스트립을 금형의 캐비티에 삽입하는 단계에서 각 리드프레임 스트립의 반도체 칩 일측면은 금형의 캐비티 상,하 면에 밀착되는 반면, 각 리드프레임 스트립의 리드프레임 일측면은 이연성 분리대의 상, 하면에 밀착되도록 삽입됨을 특징으로 하는 반도체 패키지의 제조방법.The method of claim 1, wherein in the step of inserting the lead frame strip into the cavity of the mold, one side of the semiconductor chip of each lead frame strip is in close contact with the upper and lower surfaces of the mold cavity, while the lead frame side of each lead frame strip The method of manufacturing a semiconductor package, characterized in that inserted into close contact with the upper and lower surfaces of the flexible separator.
KR1019970072868A 1997-12-24 1997-12-24 Method for fabricating semiconductor package KR100253388B1 (en)

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