KR20020053412A - Mold for semiconductor package - Google Patents

Mold for semiconductor package Download PDF

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Publication number
KR20020053412A
KR20020053412A KR1020000083044A KR20000083044A KR20020053412A KR 20020053412 A KR20020053412 A KR 20020053412A KR 1020000083044 A KR1020000083044 A KR 1020000083044A KR 20000083044 A KR20000083044 A KR 20000083044A KR 20020053412 A KR20020053412 A KR 20020053412A
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KR
South Korea
Prior art keywords
semiconductor package
mold
cavity
encapsulant
ram
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KR1020000083044A
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Korean (ko)
Inventor
손은숙
Original Assignee
마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Priority to KR1020000083044A priority Critical patent/KR20020053412A/en
Publication of KR20020053412A publication Critical patent/KR20020053412A/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Abstract

PURPOSE: A mold for a semiconductor package is provided to mold the semiconductor package at two times per one process as much as a conventional process by holding two or more packages in a cavity in the mold at the same time. CONSTITUTION: A ram port(111) is formed on an upper mold(100) in order to move a transfer ram(121) melting a molding material(300) of a solid state to up and down direction. A runner(112) and a gate(113) are formed on the both sides of the ram port by connecting to the ram port in order to pass the melted molding material. The first cavity(114) molding the first semiconductor package part(501) is formed on each gate. A runner(212) and a gate(213) are formed on a lower mold by connecting to the ram port in order to pass the molding material. The second cavity(214) is formed on the gate in order to mold the second semiconductor package part(502) in an upset state. The first and the second cavity are formed in order to closely contact the first and the second semiconductor package part each other.

Description

반도체패키지용 금형{Mold for semiconductor package}Mold for semiconductor package

본 발명은 반도체패키지용 금형에 관한 것으로, 더욱 상세하게 설명하면 반도체패키지 자재의 몰딩 속도 및 생산성을 대략 2배 이상 향상시킬 수 있는 반도체패키지용 금형에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mold for semiconductor packaging, and more particularly, to a mold for semiconductor packaging that can improve the molding speed and productivity of a semiconductor package material by approximately two or more times.

일반적인 반도체패키지의 제조 과정은 웨이퍼(Safer)상에 다수 형성되어 있는 반도체칩을 낱개로 자르고 검사하는 소잉(Sawing) 단계와, 접착제를 이용하여 인쇄회로기판 등에 상기 반도체칩을 접착하는 칩부착 단계와, 상기의 자재를 히터 블록(Heater Block)상에 안치시킨 후 도전성와이어(Wire)를 이용하여 반도체칩의 입출력패드와 인쇄회로기판의 본드핑거 끝단을 연결하는 와이어 본딩(Wire Bonding) 단계와, 상기 와이어 본딩이 끝난 자재를 상금형과 하금형 사이에 위치시키고, 봉지재를 충진하여 상기 반도체 칩, 도전성 와이어 등이 외부 환경으로부터 보호되고, 전기적으로 절연되며, 반도체칩의 작동시 발생되는 열이 효과적으로 방출되고, 마더보드(Mother Board)에 용이하게 실장되도록 일정한 모양으로 성형하는 몰딩(Molding) 단계 등으로 이루어진다.A general semiconductor package manufacturing process includes a sawing step of cutting and inspecting a plurality of semiconductor chips formed on a wafer, and a chip attaching step of adhering the semiconductor chips to a printed circuit board using an adhesive. A wire bonding step of placing the material on a heater block and connecting an input / output pad of a semiconductor chip and a bond finger end of a printed circuit board by using a conductive wire; The wire-bonded material is placed between the upper mold and the lower mold, and the encapsulant is filled to protect the semiconductor chip, the conductive wire, etc. from the external environment, electrically insulate, and effectively generate heat during operation of the semiconductor chip. Emission is made, such as a molding step (molding) step of molding to a certain shape so as to be easily mounted on the motherboard (Mother Board).

여기서 상기 금형 및 봉지재를 이용한 몰딩 방법은 반도체패키지 제조 단계의 핵심이라고도 볼 수 있으며, 다른 어떠한 가공법보다 간편하기 때문에 오늘날 반도체패키지의 몰딩 공정에 가장 많이 사용되고 있는 방법이다. 상기 봉지재는 보통 에폭시몰딩컴파운드(Epoxy Molding Compound)를 이용하는데 이는 세라믹(Ceramic)과 비교해서 열안정성이나 신뢰성면에서는 열등하지만 가격이 저렴하고 생산성이 월등히 높기 때문에 오늘날 반도체패키지에 사용되는 대부분의 봉지재는 상기 에폭시몰딩컴파운드이다.Here, the molding method using the mold and the encapsulant may be regarded as the core of the semiconductor package manufacturing step, and since it is simpler than any other processing method, it is the method most widely used in the molding process of the semiconductor package today. The encapsulant generally uses an epoxy molding compound, which is inferior in terms of thermal stability and reliability compared to ceramic, but is inexpensive and has a high productivity, so most encapsulants used in semiconductor packages today are The epoxy molding compound.

종래 이러한 봉지재를 이용하여 몰딩하는 방법은 도1에 도시된 바와 같이 상금형(10)과 하금형(20)으로 구성된 금형을 이용하게 되는데 그 구조 및 작용을 간단히 설명하면 다음과 같다.Conventionally, a method of molding using such an encapsulant uses a mold composed of an upper mold 10 and a lower mold 20 as shown in FIG. 1.

우선 소정의 프레스(도시되지 않음)로부터 힘을 전달받아 고융체 상태의 봉지재(40)를 소정 방향으로 밀어 넣을 수 있도록 하는 트랜스퍼 램(30)이 구비되어 있다.First, a transfer ram 30 is provided to receive a force from a predetermined press (not shown) and to push the encapsulant 40 in a high melt state in a predetermined direction.

한편, 상기 탑다이(10)에는 상기 트랜스퍼 램(30)이 삽입된 상태에서 하강하여 그 하부에 위치된 고융체의 봉지재(40)가 소정 방향으로 흐르도록 일정 공간의 램포트(11)가 형성되어 있다.On the other hand, the ram port 11 of a predetermined space is lowered in the state where the transfer ram 30 is inserted into the top die 10 so that the encapsulant 40 of the high-melting body located in the lower portion flows in a predetermined direction. Formed.

또한, 상기 탑다이(10)의 램포트(11)에 연결되어서는 상기 트랜스퍼 램(30)의 가압력에 의해 연화된 봉지재(40)가 일정 방향으로 흐를 수 있도록 다수의 런너(12) 및 게이트(13)가 형성되어 있다.In addition, the plurality of runners 12 and gates may be connected to the ram port 11 of the top die 10 so that the encapsulant 40 softened by the pressing force of the transfer ram 30 may flow in a predetermined direction. (13) is formed.

또한 상기 게이트(13)에 연통되어서는 탑다이(10) 및 바텀다이(20)에 반도체패키지 자재(50)가 위치할 수 있도록 일정한 공간을 갖는 다수의 캐비티(14,24)가 형성되어 있다.In addition, a plurality of cavities 14 and 24 having a predetermined space are formed in the top die 10 and the bottom die 20 so that the semiconductor package material 50 can be located in communication with the gate 13.

여기서 상기 상금형(10) 및 하금형(20)에는 상기 고융체상의 봉지재(40)가 용이하게 연화되도록 가열수단으로서 히트 카트리지(16) 등이 내장되어 있으며 또 다수의 에어벤트(15)가 형성되어 상기 흘러 들어오는 봉지재(40)의 가스 및 공기를 캐비티(14)의 외부로 용이하게 방출시킬 수 있도록 되어 있다.Here, the upper mold 10 and the lower mold 20 have a heat cartridge 16 or the like as a heating means so that the high-melting encapsulant 40 is softened, and a plurality of air vents 15 are provided. It is formed so that the gas and air of the encapsulant 40 flowing in can be easily released to the outside of the cavity 14.

그러나 이러한 종래의 반도체패키지용 금형은 하나의 캐비티에 하나의 반도체패키지 자재만이 위치됨으로써, 생산속도가 비교적 느리고 또한 이에 따라 생산성도 뛰어나지 않은 단점이 있다.However, such a mold for a semiconductor package has a disadvantage in that only one semiconductor package material is placed in one cavity, so that the production speed is relatively slow and the productivity is not excellent.

본 발명은 이와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 본 발명의 목적은 반도체패키지 자재를 몰딩하는 금형중 캐비티에 적어도 2개 이상의 자재를 동시에 안착시킴으로써, 한번의 공정으로 종래보다 대략 2배 많은 반도체패키지 자재를 몰딩할 수 있는 반도체패키지용 금형을 제공하는데 있다.The present invention has been made to solve such a conventional problem, an object of the present invention by placing at least two or more materials in the cavity of the mold for molding the semiconductor package material at the same time, approximately two times than conventional in one process To provide a mold for a semiconductor package capable of molding many semiconductor package materials.

도1은 종래의 반도체패키지용 금형을 도시한 단면도이다.1 is a cross-sectional view showing a mold for a conventional semiconductor package.

도2는 본 발명의 제1실시예인 반도체패키지용 금형을 도시한 단면도이다.2 is a cross-sectional view showing a mold for a semiconductor package which is a first embodiment of the present invention.

도3은 본 발명의 제2실시예인 반도체패키지용 금형을 도시한 단면도이다.3 is a cross-sectional view showing a mold for a semiconductor package as a second embodiment of the present invention.

도4는 도2와 도3에 의해 몰딩된 스트립을 도시한 평면도이다.Figure 4 is a plan view of the strip molded by Figures 2 and 3;

-도면의 주요부분에 대한 부호설명-Code descriptions for the main parts of the drawings

100;상금형 200; 하금형100; mold 200; Lower mold

111,211; 램포트(Ram Port), 제2램포트112, 212; 런너(Runner),111,211; Ram Ports, Second Ram Ports 112 and 212; Runner,

113,213; 게이트(Gate)113,213; Gate

114, 214; 제1캐비티, 제2캐비티(Cavity)114, 214; 1st cavity, 2nd cavity (Cavity)

121,221; 트랜스퍼램(Transfer Ram), 제2트랜스퍼램121,221; Transfer Ram, Second Transfer Ram

300; 봉지재300; Encapsulant

301; 컬(Cull)301; Cull

400; 플레이트(Plate)400; Plate

501,502; 제1반도체패키지 자재, 제2반도체패키지 자재501,502; 1st semiconductor package material, 2nd semiconductor package material

상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지용 금형은 봉지재를 고압상태로 제공하는 트랜스퍼램이 이동하도록 일정 직경의 램포트가 형성되어 있고, 상기 램포트의 일측에는 상기 램포트에 연통되어 상기 봉지재가 통과하도록 런너 및 게이트가 순차적으로 형성되어 있고, 상기 게이트에는 제1반도체패키지 자재가 위치되어 봉지재로 몰딩되도록 제1캐비티가 형성되어 있는 상금형과; 상기 상금형의 램포트 하부에는 상기 램포트에 연통되어 상기 봉지재가 통과하도록 런너 및 게이트가 순차적으로 형성되어 있고, 상기 게이트에는 제2반도체패키지 자재가 위치되어 봉지재로 몰딩되도록 제2캐비티가 형성되어 있는 하금형을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, a mold for a semiconductor package according to the present invention has a ramport having a predetermined diameter to move a transfer ram providing an encapsulant in a high pressure state, and one side of the ramport communicates with the ramport. And a runner and a gate are sequentially formed to pass the encapsulant, and the first mold having a first cavity formed at the gate so as to be molded into the encapsulant; Runners and gates are sequentially formed in the lower ramport of the upper mold to communicate with the ramport, and the encapsulant passes therethrough, and a second cavity is formed in the gate so that a second semiconductor package material is positioned and molded into the encapsulant. Characterized in that it is made, including the lower mold.

여기서, 상기 제1캐비티 및 제2캐비티는 상기 각각의 제1,2캐비티에 안착된 제1,2반도체패키지 자재가 상호 밀착되도록 형성되어 있다.Here, the first cavity and the second cavity are formed such that the first and second semiconductor package materials seated in the respective first and second cavities are in close contact with each other.

또한, 상기 제1캐비티 및 제2캐비티 사이에는 대략 판상의 플레이트가 위치되고, 상기 플레이트의 상,하면에는 제1,2반도체패키지 자재가 밀착되도록 할 수도 있다.In addition, a substantially plate-shaped plate is positioned between the first cavity and the second cavity, and the first and second semiconductor package materials may be in close contact with each other on the upper and lower surfaces of the plate.

더불어, 상기 하금형에는 상기 램포트와 연통된 제2램포트가 더 형성되어 있고, 제2램포트에는 별도의 제2트랜스퍼램이 상,하 이동 가능하게 더 결합되어 있을 수 있다.The lower die may further include a second ram port communicating with the ram port, and a second second ram may be further coupled to the second ram port to move up and down.

상기와 같이 하여 본 발명에 의한 반도체패키지용 금형은 상금형 및 하금형에 각각 제1캐비티 및 제2캐비티를 각각 형성하고, 상기 각각의 제1,2캐비티에는 제1,2반도체패키지 자재가 위치하도록 함으로써, 한번의 공정으로 종래에 비하여 2배의 몰딩된 반도체패키지 자재를 얻게 된다. 따라서, 종래에 비하여 생산성이 2배로 향상된다.As described above, in the mold for semiconductor package according to the present invention, the first cavity and the second cavity are respectively formed in the upper mold and the lower mold, and the first and second semiconductor package materials are positioned in the respective first and second cavities. By doing so, the molded semiconductor package material can be obtained twice as compared to the conventional one-step process. Therefore, productivity is doubled as compared with the prior art.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2는 본 발명의 제1실시예인 반도체패키지용 금형을 도시한 단면도로서, 도시된 바와 같이 크게 상금형(100)과 하금형(200)의 결합 구조를 하고 있다.FIG. 2 is a cross-sectional view illustrating a mold for a semiconductor package according to a first embodiment of the present invention. As shown in FIG. 2, the upper mold 100 and the lower mold 200 are combined.

먼저, 상금형(100)에는 고체상(固體狀)의 봉지재(300)를 고온, 고압 상태로 융용시키는 트랜스퍼램(121)이 상,하 방향으로 이동할 수 있도록, 일정 직경을 갖는 램포트(111)가 형성되어 있고, 상기 램포트(111)의 양측으로는 상기 램포트(111)에 연통되어 상기 융용된 봉지재(300)가 통과할 수 있도록 런너(112)및 게이트(113)가 순차적으로 형성되어 있다. 통상 상기 각 게이트(113)에는 일정 공간을 갖는 제1캐비티(114)가 연통되어 형성되어 있다. 상기 제1캐비티(114)는 제1반도체패키지 자재(501)가 안착되어 상기 융용된 봉지재(300)에 의해 몰딩되는 공간이다.First, in the upper mold 100, the ram pot 111 having a predetermined diameter so that the transfer ram 121 for fusing the solid encapsulant 300 in a high temperature and high pressure state can move in an up and down direction. And a runner 112 and a gate 113 are sequentially connected to both sides of the ram port 111 so that the melted encapsulant 300 can pass therethrough. Formed. In general, the first cavity 114 having a predetermined space communicates with each of the gates 113. The first cavity 114 is a space in which the first semiconductor package material 501 is seated and molded by the molten encapsulant 300.

한편, 상기 하금형(200)에는 상기 램포트(111)의 하부에 연통되어 상기 봉지재(300)가 통과하도록 런너(212) 및 게이트(213)가 순차적으로 형성되어 있고, 상기 게이트(213)에는 제2반도체패키지 자재(502)가 뒤집어진 상태로 위치되어 몰딩되도록 제2캐비티(214)가 연통되어 형성되어 있다.Meanwhile, a runner 212 and a gate 213 are sequentially formed in the lower die 200 so as to communicate with the lower portion of the ram port 111 so that the encapsulant 300 passes therethrough, and the gate 213. The second cavity 214 is formed in communication with the second semiconductor package material 502 so that the second semiconductor package material 502 is positioned and molded in an inverted state.

즉, 상기 제1캐비티(114) 및 제2캐비티(214)는 그것에 안착된 제1,2반도체패키지 자재(501,502)가 상호 밀착되도록 형성되어 있다. 더욱 상세하게는 상기 제1반도체패키지 자재(501)는 정위치로 위치되어 있고, 상기 제1반도체패키지 자재(501)의 하면에는 제2반도체패키지 자재(502)가 뒤집혀진 상태로 상기 제1반도체패키지 자재(501)의 하면에 밀착되어 있다.That is, the first cavity 114 and the second cavity 214 are formed such that the first and second semiconductor package materials 501 and 502 seated thereon are in close contact with each other. In more detail, the first semiconductor package material 501 is positioned in the correct position, and the first semiconductor package material 502 is turned upside down on the bottom surface of the first semiconductor package material 501. It adheres to the lower surface of the package material 501.

따라서, 상기 램포트(111)를 통한 봉지재(300)는 상금형(100) 및 하금형(200)의 각 런너(112,212) 및 게이트(113,213)를 통해 각각의 제1캐비티(114) 및 제2캐비티(214)에 충진되고, 이로 인해 상기 상금형(100)의 제1캐비티(114) 및 하금형(200)의 제2캐비티(214)에 각각 안착된 제1반도체패키지 자재(501) 및 제2반도체패키지 자재(502)는 한번의 공정으로 동시에 몰딩됨으로써, 종래에 비해 생산성이 대략 2배 정도 향상된다.Accordingly, the encapsulant 300 through the ramport 111 is formed through the first and second cavity 114 and the gates 113 and 213 of the upper mold 100 and the lower mold 200, respectively. A first semiconductor package material 501 filled in two cavities 214 and thus seated in the first cavity 114 of the upper mold 100 and the second cavity 214 of the lower mold 200, respectively; The second semiconductor package material 502 is molded at the same time in one process, thereby improving productivity by approximately two times as compared with the prior art.

도3은 본 발명의 제2실시예인 반도체패키지용 금형을 도시한 단면도이다.3 is a cross-sectional view showing a mold for a semiconductor package as a second embodiment of the present invention.

도시된 바와 같이 대부분의 구조는 상기 제1실시예와 유사하고, 다만 대략 판상의 플레이트(400)가 상기 상금형(100)의 제1캐비티(114)와 하금형(200)의 제2캐비티(214)에 삽입된 것이 상이하다.As shown, most of the structure is similar to that of the first embodiment, except that the substantially plate-shaped plate 400 is formed of the first cavity 114 of the upper mold 100 and the second cavity of the lower mold 200 ( Inserted in 214 is different.

즉, 상기 제1캐비티(114) 및 제2캐비티(214) 사이에는 대략 판상의 플레이트(400)가 더 위치되어 있고, 상기 각 플레이트(400)의 상,하면에는 제1반도체패키지 자재(501) 및 제2반도체패키지 자재(502)가 각각 밀착되어 있다. 물론, 램포트(111)에 연통된 런너(112,212) 및 게이트(113,213)는 모두 상기 플레이트(400)의 상,하면에 형성되어 있다.That is, a substantially plate-shaped plate 400 is further located between the first cavity 114 and the second cavity 214, and the first semiconductor package material 501 is disposed on the upper and lower surfaces of the plates 400. And the second semiconductor package material 502 are in close contact with each other. Of course, the runners 112 and 212 and the gates 113 and 213 communicating with the ram ports 111 are formed on the upper and lower surfaces of the plate 400.

또한, 상기 하금형(200)에는 상기 램포트(111)와 연통된 제2램포트(211)가 더 형성되어 있고, 제2램포트(211)에는 별도의 제2트랜스퍼램(221)이 상,하 이동 가능하게 결합되어 있을 수 있다. 이와 같이 상금형(100) 및 하금형(200)에 각각 램포트(111,211)가 구비될 경우에는 상기 봉지재(300)가 각 제1캐비티(114) 및 제2캐비티(214)에 충진되는 시간이 더욱 단축되며, 이러한 구조는 상기 제1실시예에도 그대로 적용 가능하다.In addition, the lower die 200 is further formed with a second ram port 211 in communication with the ram port 111, the second ram port 211 is a separate second transformer (221) is upper It may be coupled to move downward. As described above, when the ram ports 111 and 211 are provided in the upper mold 100 and the lower mold 200, the encapsulant 300 is filled in each of the first cavity 114 and the second cavity 214. This is further shortened, and this structure is also applicable to the first embodiment as it is.

한편, 상기한 구조 역시 상기 램포트(111)를 통한 봉지재(300)가 상금형(100) 및 하금형(200)의 각 런너(112,212) 및 게이트(113,213)를 통해 각각의 제1캐비티(114) 및 제2캐비티(214)에 충진되고, 이로 인해 상기 상금형(100)의 제1캐비티(114) 및 하금형(200)의 제2캐비티(214)에 각각 안착된 제1반도체패키지 자재(501) 및 제2반도체패키지 자재(502)는 한번의 공정으로 동시에 몰딩됨으로써, 종래에 비해 생산성이 대략 2배 정도 향상된다.On the other hand, the above-described structure also the encapsulant 300 through the ram port 111, each of the first cavity through the runners 112 and 212 and the gates 113 and 213 of the upper mold 100 and the lower mold 200, respectively. 114 and the second cavity 214, and thus the first semiconductor package material seated in the first cavity 114 of the upper mold 100 and the second cavity 214 of the lower mold 200, respectively The 501 and the second semiconductor package material 502 are molded at the same time in one process, whereby the productivity is approximately doubled compared to the conventional one.

이러한 반도체패키지 자재는 도4에 도시된 바와 같이 봉지재(300)의 열을 식힌 후 상,하금형(100)(200)으로부터 상기 반도체패키지 자재(501,502)를 분리하고 불필요한 부위인 컬(301)(Cull)을 절단수단으로 절단하는 것에 의해, 반도체패키지 자재의 몰딩을 완료하게 된다.The semiconductor package material is separated from the semiconductor package material (501, 502) from the upper and lower molds (100, 200) after cooling the heat of the encapsulant 300, as shown in Figure 4 curl (301) By cutting the (Cull) by the cutting means, the molding of the semiconductor package material is completed.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기예만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications may be made without departing from the scope and spirit of the present invention.

따라서, 본 발명에 의한 반도체패키지용 금형은 상금형 및 하금형에 각각 제1캐비티 및 제2캐비티를 각각 형성하고, 상기 각각의 제1,2캐비티에는 제1,2반도체패키지 자재가 위치하도록 함으로써, 한번의 공정으로 종래에 비하여 2배의 몰딩된 반도체패키지 자재를 얻게 된다. 따라서, 종래에 비하여 생산성이 2배로 향상되는 효과가 있다.Therefore, in the mold for semiconductor package according to the present invention, the first cavity and the second cavity are respectively formed in the upper mold and the lower mold, and the first and second semiconductor package materials are positioned in the respective first and second cavities. In one process, the molded semiconductor package material is twice as large as the conventional one. Therefore, there is an effect that the productivity is improved twice as compared with the conventional.

Claims (4)

봉지재를 고압상태로 제공하는 트랜스퍼램이 이동하도록 일정 직경의 램포트가 형성되어 있고, 상기 램포트에 연통되어 상기 봉지재가 통과하도록 런너 및 게이트가 순차적으로 형성되어 있고, 상기 게이트에는 제1반도체패키지 자재가 위치되어 봉지재로 몰딩되도록 제1캐비티가 형성되어 있는 상금형과;Ramports having a predetermined diameter are formed to move the transfer ram providing the encapsulant in a high pressure state, and a runner and a gate are sequentially formed to communicate with the ramport so that the encapsulant passes, and the first semiconductor is formed on the gate. An upper mold having a first cavity formed so that the package material is positioned and molded into the encapsulant; 상기 상금형의 램포트 하부에는 상기 램포트에 연통되어 상기 봉지재가 통과하도록 런너 및 게이트가 순차적으로 형성되어 있고, 상기 게이트에는 제2반도체패키지 자재가 위치되어 봉지재로 몰딩되도록 제2캐비티가 형성되어 있는 하금형을 포함하여 이루어진 반도체패키지용 금형.Runners and gates are sequentially formed in the lower ramport of the upper mold to communicate with the ramport, and the encapsulant passes therethrough, and a second cavity is formed in the gate so that a second semiconductor package material is positioned and molded into the encapsulant. Mold for semiconductor package, including the lower die. 제1항에 있어서, 상기 제1캐비티 및 제2캐비티는 상기 각각의 제1,2캐비티에 안착된 제1,2반도체패키지 자재가 상호 밀착되도록 형성됨을 특징으로 하는 반도체패키지용 금형.The mold of claim 1, wherein the first cavity and the second cavity are formed to closely adhere to the first and second semiconductor package materials seated on the respective first and second cavities. 제1항에 있어서, 상기 제1캐비티 및 제2캐비티 사이에는 대략 판상의 플레이트가 위치되고, 상기 플레이트의 상,하면에는 제1,2반도체패키지 자재가 밀착됨을 특징으로 하는 반도체패키지용 금형.2. The semiconductor package mold as claimed in claim 1, wherein a substantially plate-shaped plate is positioned between the first cavity and the second cavity, and first and second semiconductor package materials adhere to the upper and lower surfaces of the plate. 제1항에 있어서, 상기 하금형은 상기 램포트와 연통된 제2램포트가 더 형성되어 있고, 제2램포트에는 별도의 제2트랜스퍼램이 상,하 이동 가능하게 결합된 것을 특징으로 하는 반도체패키지용 금형.According to claim 1, wherein the lower die is further formed with a second ram port in communication with the ram port, the second ram port is characterized in that a separate second transfer ram is coupled to move up, down Mold for semiconductor package.
KR1020000083044A 2000-12-27 2000-12-27 Mold for semiconductor package KR20020053412A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990053262A (en) * 1997-12-24 1999-07-15 구본준 Manufacturing method of semiconductor package
JPH11340263A (en) * 1998-05-25 1999-12-10 Towa Corp Method for resin-encapsulating electronic component
KR20010028388A (en) * 1999-09-21 2001-04-06 윤종용 Molding apparatus for semiconductor chip package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990053262A (en) * 1997-12-24 1999-07-15 구본준 Manufacturing method of semiconductor package
JPH11340263A (en) * 1998-05-25 1999-12-10 Towa Corp Method for resin-encapsulating electronic component
KR20010028388A (en) * 1999-09-21 2001-04-06 윤종용 Molding apparatus for semiconductor chip package

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