sH2S〇 A7 ____B7 五、發明説明（/ ) 本發明係關於一種單晶積體電路之封裝製程，尤指一 種包含有特殊封裝步驟，以有效降低製作成本及縮小成品 體積之積體電路製作方法。 按，積體電路相較於傳統電子電路的最大優點在於： 電路體積的大幅縮小及效率提高，因此長久以來，小型化 一直仍是積體電路業界不斷追求的目標，因此如何有效縮 小積體電路，並同時擴充其功能或處理速度，爲目前開發 積體電路所要求的主要重點。 然而在既有的製作技術上，由於牽涉製程上的若干限 制，在力求小型化的過程中存在無法突破的瓶頸，如既有 單晶積體電路的封裝方式即爲一顯著實例，目前單晶積體 .電路製程係於一金屬花架上安裝裸晶後，打金線以連接裸 晶及金屬花架，隨後進行封裝步驟，目前普遍的封裝方式 係利用模具於金屬花架表底面灌入膠液，俟凝結脫模後於 基板外形成封裝層。 由於前述封裝方式係以模具形成封裝層，限於既有模 具製作技術，其於體積上即有所限制，因此造成小型化之 障礙。 經濟部中央揉準局貝工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 又不同規格的單晶積體電路必須事先製作不同大小的 模具，以配合不同的金屬花架形成封裝層，故其實施成本 所費不貲。 由上述可知，既有積體電路製程因封裝技術存在技術 瓶頸，而無法提高小型化的規模及工作效率，故有進一步 檢討改進之必要。 3 本紙张尺度適用中國國家標隼（CNS ) Λ4坭格（210X297公釐） 31!25〇 A7 B7 五、發明説明（ 經濟部中央標準局員工消費合作社印^ 因此，本發明主要目的乃在提供一種可有效縮小積體 電路體積之製程，其包括有基板製作、裝晶、打線、封膠 及切割等步驟，其中： 該封膠步驟係於基板周邊以高黏度樹脂形成適當高 度、厚度之側壁，又於側壁內之基板上灌入低黏度樹脂， 俟凝結爲固態後，即構成平整之封裝表層。 藉該等封裝步驟可有效降低製程成本、縮小成品體積 及提高工作效率。 本發明次一目的在於：前述基板上形成有多數導通 孔，導通孔內分別以高溫錫料塡實，錫料係與基板表面佈 設線路連接，並露出於基板底面，可供植佈錫球。 爲使貴審査委員進一步瞭解前述目的及本發明之結 構特徵，茲附以圖式詳細說明如后： (一） 圖式部分： 第一圖：係本發明之流程方塊圖。 第二圖：係本發明之平面結構圖。 第三圖：係本發明一較佳實施例之成品剖視圖。 第四圖：係本發明另一較佳實施例之成品剖視圖 (二） 圖號部分： 1 0 )基板 1 2 )金線 1 4 )封裝層 16)錫料導體 (1 1 )晶片 (1 3 )側壁 (15)接著劑 (1 7 )錫球 有關本發明之製作流程，請參閱第一圖所示 4 其包括 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 本紙张尺度適用中國國家標車（CNS > Λ4規格（210X297公釐） S11250 at B7 五、發明説明（J ) 有：「基板製作」、「裝晶」、「打線」、「封膠」、「錫 料塡實」、「出料」、「切割」等步驟；其中： 該「基板製作」步驟：其係利用陶瓷構成基板，以承 載I C晶片，又於基板上鑽設多數導通孔，並以電鍍方式 於基板表面構成連接線路。 「裝晶」步驟：直接將裸晶（bare CHIP )放置於 基板上，或將晶片放置於基板表面，以打金線或鋁線使晶 片與基板表面線路連接。 「封膠」步驟：請參閱第二圖所示，當於一未經切割 成單片之整片基板（1 0)表面設以多數晶片（1 1 )， 並經由打上金線（1 2 )使各晶片（1 1 )分別與基板（1 .0 )表面線路連接後，即可進行封膠。 該封膠步驟主要係利用不同黏度的樹脂以保護基板 (1 0 )上之晶片（1 1 )及金線（1 2 )。 經濟部中央標準局貝工消费合作社印製sH2S〇 A7 ____B7 V. Description of the invention (/) The present invention relates to a packaging process of a single crystal integrated circuit, in particular to a method of manufacturing an integrated circuit that includes special packaging steps to effectively reduce the manufacturing cost and reduce the volume of the finished product. According to the press, the biggest advantage of the integrated circuit compared with the traditional electronic circuit is: The circuit size is greatly reduced and the efficiency is improved. Therefore, for a long time, miniaturization has always been the goal pursued by the integrated circuit industry, so how to effectively reduce the integrated circuit , And at the same time expand its function or processing speed, is the main focus required for the development of integrated circuits. However, in the existing manufacturing technology, due to several limitations involved in the manufacturing process, there are bottlenecks that cannot be broken through in the process of striving for miniaturization. For example, the packaging method of the existing single crystal integrated circuit is a remarkable example. The current single crystal Integrated circuit. After the die is installed on a metal flower stand, a gold wire is connected to connect the die and the metal flower stand, and then the packaging step is carried out. The current general packaging method is to use a mold to fill the bottom surface of the metal flower stand with glue. After coagulation and demolding, an encapsulation layer is formed outside the substrate. Since the aforementioned packaging method uses a mold to form the packaging layer, which is limited to the existing mold manufacturing technology, it is limited in volume, thus causing an obstacle to miniaturization. Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Different sizes of single crystal integrated circuits must be made with different sizes of molds in advance to match different metal flower frames to form packages Layer, so the cost of its implementation is costly. It can be seen from the above that the existing integrated circuit manufacturing process has a technical bottleneck due to packaging technology, which cannot improve the scale and work efficiency of miniaturization, so it is necessary to further review and improve. 3 This paper scale is applicable to the Chinese National Standard Falcon (CNS) Λ4 nigger (210X297 mm) 31! 25〇A7 B7 V. Description of the invention (printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ Therefore, the main purpose of this invention is to provide A process capable of effectively reducing the volume of an integrated circuit, which includes the steps of substrate manufacturing, crystal mounting, wire bonding, encapsulation and cutting, etc .: The encapsulation step is to form a side wall of appropriate height and thickness with high viscosity resin around the substrate Then, low-viscosity resin is poured on the substrate in the side wall to form a flat package surface layer after it is solidified. These packaging steps can effectively reduce the manufacturing cost, reduce the volume of the finished product and improve the work efficiency. The purpose is: a plurality of via holes are formed on the substrate, the via holes are respectively solidified with high-temperature tin material, the tin material is connected to the surface of the substrate, and is exposed on the bottom surface of the substrate, which can be used to plant solder balls. The members further understand the aforementioned objectives and the structural features of the present invention, and the drawings are described in detail as follows: (1) The part of the drawing: the first drawing It is the process block diagram of the present invention. The second picture: is the plane structure diagram of the present invention. The third picture: is the sectional view of the finished product of a preferred embodiment of the present invention. The fourth picture: is the preferred embodiment of the present invention. Sectional view of the finished product (2) Part of the drawing number: 1 0) Substrate 1 2) Gold wire 1 4) Encapsulation layer 16) Tin material conductor (1 1) Wafer (1 3) Side wall (15) Adhesive (1 7) Related to solder balls For the production process of the present invention, please refer to the first picture shown in Figure 4. It includes (please read the precautions on the back before filling in this page). The size of the paper is applicable to China National Standard Vehicle (CNS > Λ4 specification (210X297mm ) S11250 at B7 Fifth, the description of invention (J) includes: "substrate fabrication", "mounting crystal", "bonding", "sealing glue", "tin material", "discharge", "cutting" and other steps; Among them: The "substrate fabrication" step: it uses ceramics to construct the substrate to carry the IC chip, and drills a large number of via holes on the substrate, and forms a connection circuit on the surface of the substrate by electroplating. The "mounting crystal" step: directly Bare CHIP is placed on the substrate, or the wafer is placed Place it on the surface of the substrate and connect the chip to the surface of the substrate with gold wires or aluminum wires. The step of "sealing": refer to the second figure, when a whole substrate is not cut into single pieces (1 0 ) The surface is provided with a large number of chips (1 1), and each chip (1 1) is connected to the surface circuit of the substrate (1.0) respectively by applying a gold wire (1 2), and then the sealing can be performed. The sealing step It mainly uses resins with different viscosities to protect the chip (1 1) and gold wire (1 2) on the substrate (1 0). Printed by Beigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs
In ^^^1 f i m nn n ^^^1 m ^^1 ^^4 一 (請先閲讀背面之注意事項再填寫本頁) 具體的方法係先以高黏度的樹脂於基板（1 0 )周邊 圍設形成一圈連續側壁（1 3 )，該側壁（1 3 )具有適 當厚度、高度，其中側壁（1 3 )高度恆高於基板（1 0) 上之晶片（1 1 )及金線（1 2 )，以便於基板（1 0 ) 表面灌入低黏度樹脂時，得將晶片（1 1 )及金線（1 2 ) 完全覆蓋。 當基板（1 0 )於周邊以高黏度樹脂形成以連續側壁 (1 3 )後，隨後即於側壁（1 3 )內灌入樹脂，其灌入 之樹脂係爲形成封裝層（1 4 )，爲考慮其樹脂灌入後之 表面張力，使其構成之封裝層（1 4 )表面平整，乃選用 5 本紙悵尺度適用中國國家標皁（CNS ) Λ4规格（210X 297公釐） Α7 Β7 五、發明説明（冷） 低黏度樹脂。 該低黏度樹脂灌入厚度係以可完全覆蓋基板（10) 表面之晶片（11)及金線（12)，且於其上形成相當 覆蓋厚度爲原則，於本實施例中，該低黏度樹脂之厚度與 側壁（1 ·3 )等高。 俟側壁（1 3 )灌入之樹脂凝結後，即構成一適當厚 度之封裝層（14)，而完成封膠步驟。 「錫料塡實」步驟：在完成前述步驟後，即以高溫錫 料將基板上之導通孔塡實。 「出腳」步驟：經完成前述「錫料塡實」步驟後，即 於錫料導體露出基板底面之一端分別植設以錫球或錫柱、 .錫塊，以作爲積體電路封裝完成後之出腳。 「切割」步驟：在完成前述步驟後，即將半成品送至 晶片切割機上進行切割，其切割方式係如第二圖所示，依 晶片（1 1 )之分佈區隔等分，經切割後即分別構成單晶 積體電路。 經濟部中央標準局貝工消费合作社印製 —^n m ^ϋ· n^— m n HI ^^^1 > l^i ^^^1 ^^^1 ^^^1 ml In— 一 V i -53 (請先聞讀背面之注意事項再填寫本頁) 以前述製程步驟完成之單晶積體電路，其一較佳實施 例結構係如第三圖所示，其以電鍍銅陶瓷基板（1 0 )爲 基底，表面線路及其上所設晶片（11)、金線（12) 等由低黏度樹脂構成之封裝層（1 4 )所封裝包覆，並構 成防護。 由圖中可進一步看出，該晶片（1 1 )係以接著劑（1 5 )接著於基板（1 0 )表面，又基板（1 0 )上各導通 孔內所塡實錫料導體（1 6 )露出基板（1 0 )底面之一 6 本紙张尺度適用中國國家標隼（CNS > Λ4现格（2丨0X 297公釐〉 A7 B7 五、發明説明（厂） 端具較大面積’以利於接線作業。 又如第四圖所示，係本創作另一較佳實施例之平面結 構圖，其基本架構與前一實施例完全相同，不同處係在於： 基板（1 0 )上所設各錫料導體（1 6 )於露出底面之一 端分別植設有錫球（1 7 )’作爲黏著接線之用。 由上述可知，本創作係透過一特殊的封裝步驟，直接 於基板表面形成封裝層，以封裝防護基板表面之佈線及所 設晶片、金線（鋁線）’其經切割後，即可完成一單晶積 體電路之製作.，而以該等製程步驟至少可獲致下列優點： 1 ·利於小型化：由於本發明係以前述樹脂封裝步驟 取代規行之模造封裝方式，故不受模具製造技術限制，而 .可有效縮小製成積體電路之體積，以符合產業硏發趨勢。 2 ·降低成本：由於不需使用模具，故無須事先因應 不同的積體電路規格製造不同的模具，如此即可有效減少 製造成本。 3 ·具理想的電氣特性：藉由前述設計，可縮短、縮 小單晶積體電路之連接路徑，而提髙其工作效率。 經濟部中央橾準局貝工消费合作社印装 I I -I —^^1 —^1 I - 1 In 1 --- n^i -,J i 0¾-彡 {請先閱讀背面之注意事項再填寫本筲) 4 ·具理想的散熱特性：由於本發明於基板各導通孔 內分別以高溫錫料塡實，故可加強封裝體之氣密性及提高 晶的導熱能力，同時電鍍銅陶瓷基板本身亦具有良好之導 熱能力，因此以前述製程所構成單晶積體電路將具備理想 之散熱特性。 綜上所述，本發明確可獲致如前揭所述之各項優點， 其可突破此產業之現存瓶頸、障礙，故已兼具產業上利用 7 本紙浪尺度適用中國囤家標羋（CNS ) Λ4規格（210X297公釐)In ^^^ 1 fim nn n ^^^ 1 m ^^ 1 ^^ 4 1 (please read the notes on the back before filling in this page) The specific method is to use a high viscosity resin around the substrate (1 0) Surrounding to form a circle of continuous side walls (1 3), the side walls (1 3) having appropriate thickness and height, wherein the height of the side walls (1 3) is constantly higher than the wafer (1 1) and the gold wire (1 1) on the substrate (1 0) 1 2), so that when the low viscosity resin is poured into the surface of the substrate (1 0), the wafer (1 1) and the gold wire (1 2) must be completely covered. After the substrate (1 0) is formed with a high-viscosity resin on the periphery with continuous side walls (1 3), resin is then poured into the side walls (1 3), and the resin poured into it forms the encapsulation layer (1 4), In order to consider the surface tension after the resin is poured, and to make the surface of the encapsulation layer (1 4) formed flat, 5 paper sheets are used, which are applicable to the Chinese National Standard Soap (CNS) Λ4 specification (210X 297mm) Α7 Β7 5. Description of the invention (cold) Low viscosity resin. The low-viscosity resin filling thickness is based on the principle that the wafer (11) and the gold wire (12) can completely cover the surface of the substrate (10), and a considerable covering thickness is formed thereon. In this embodiment, the low-viscosity resin The thickness is equal to the height of the side wall (1.3). Once the resin poured into the side wall (1 3) is coagulated, an encapsulation layer (14) of appropriate thickness is formed, and the sealing step is completed. "Tin material solidification" step: After completing the above steps, the via holes on the substrate are solidified with high-temperature tin material. "Foot-out" step: After completing the aforementioned "tin material solidification" step, tin balls or tin pillars, .tin blocks are respectively planted on the end of the tin conductor exposed from the bottom surface of the substrate, which is used as an integrated circuit package. Foothold. "Cutting" step: After completing the above steps, the semi-finished product is sent to the wafer cutting machine for cutting. The cutting method is as shown in the second figure, which is divided equally according to the distribution of the wafer (1 1). Each constitutes a single crystal integrated circuit. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs— ^ nm ^ ϋ · n ^ — mn HI ^^^ 1 > l ^ i ^^^ 1 ^^^ 1 ^^^ 1 ml In— One V i- 53 (please read the precautions on the back before filling in this page) The single crystal integrated circuit completed in the above process steps, a preferred embodiment of the structure is shown in the third figure, which uses an electroplated copper ceramic substrate (1 0) is the substrate, the surface circuit and the chip (11), gold wire (12), etc. on the surface circuit and the packaging layer (1 4) made of low-viscosity resin are encapsulated and protected. It can be further seen from the figure that the wafer (1 1) is adhered to the surface of the substrate (1 0) with an adhesive (1 5), and the solid tin material conductor (1) in each via hole on the substrate (1 0) 6) One of the bottom surfaces of the exposed substrate (1 0) 6 This paper scale is applicable to the Chinese national standard falcon (CNS > Λ4 present grid (2 丨 0X 297mm> A7 B7) 5. Description of the invention (factory) with large area In order to facilitate the wiring operation. As shown in the fourth figure, it is a plan structure diagram of another preferred embodiment of the present invention, the basic structure is exactly the same as the previous embodiment, the difference is that: the substrate (1 0) Let each tin conductor (16) be implanted with tin balls (17) on one end of the exposed bottom surface for adhesive bonding. From the above, we can see that this creation is formed directly on the surface of the substrate through a special packaging step The encapsulation layer is used to encapsulate the wiring on the surface of the protective substrate and the provided chips and gold wires (aluminum wires) '. After cutting, you can complete the production of a single crystal integrated circuit. These process steps can at least achieve the following Advantages: 1 · Conducive to miniaturization: Because the present invention is based on the aforementioned resin The assembly step replaces the conventional molding packaging method, so it is not limited by the mold manufacturing technology, and the volume of the integrated circuit can be effectively reduced to meet the trend of industrial development. 2 · Cost reduction: Because no mold is used, there is no need to use Manufacture different molds according to different integrated circuit specifications in advance, so that the manufacturing cost can be effectively reduced. 3 · With ideal electrical characteristics: through the foregoing design, the connection path of the single crystal integrated circuit can be shortened and narrowed, and improved Its work efficiency. Printed and printed II-I — ^^ 1 — ^ 1 I-1 In 1 --- n ^ i-, J i 0¾- 彡 {Please read the back side first Note: fill in this 筲) 4 · With ideal heat dissipation characteristics: Since the present invention is solidified with high-temperature tin material in each via hole of the substrate, it can enhance the airtightness of the package and improve the thermal conductivity of the crystal, while electroplating The copper ceramic substrate itself also has good thermal conductivity, so the single crystal integrated circuit formed by the foregoing process will have ideal heat dissipation characteristics. In summary, the present invention can indeed achieve the advantages described above It may break the existing bottleneck of this industry, barriers, it has both wave-scale use of seven paper suitable for Chinese home hoard standard Mi (CNS) Λ4 size (210X297 mm) on industry
Sil25Q A7 B7 五、發明説明（厶） 性與進步性，並符合發明專利之要件，爰依法提起申請。 經濟部中央標準局貝工消費合作社印製 8 (請先閱讀背面之注意事項再填寫本頁) 本紙伕尺度適用中國國家榡準（CNS ) A4規格（210X 297公釐）Sil25Q A7 B7 Fifth, the description of the invention (厶) and progress, and meet the requirements of the invention patent, file an application according to law. Printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 8 (Please read the precautions on the back before filling out this page) This paper is applicable to China National Standard (CNS) A4 (210X 297mm)