CN115332224A - 3D packaging structure and manufacturing method thereof - Google Patents
3D packaging structure and manufacturing method thereof Download PDFInfo
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- CN115332224A CN115332224A CN202211261020.5A CN202211261020A CN115332224A CN 115332224 A CN115332224 A CN 115332224A CN 202211261020 A CN202211261020 A CN 202211261020A CN 115332224 A CN115332224 A CN 115332224A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Abstract
The embodiment of the invention provides a 3D packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductor packaging. This 3D packaging structure includes first group chip, second group chip, base plate and external solder ball, the base plate has relative first surface and second surface, and all has the tie point on this first surface and the second surface, the tie point basis connecting wire in the base plate arranges, and first group chip and second group chip are the flip chip, and first group chip passes through the first surface of tie point connection base plate, the second group chip passes through the tie point and connects the second surface of base plate, the first surface of external solder ball connection base plate, between the inside chip of first group chip, between the inside chip of second group chip and between first group chip and the second group chip communicate through the connecting wire in the base plate. The first group of chips and the second group of chips are vertically connected, and signals are transmitted through the shortest distance, so that signal delay and distortion can be reduced, and the bandwidth is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a 3D packaging structure and a manufacturing method thereof.
Background
The 3D wafer level package (also referred to as 3D package) refers to a package technology of stacking more than two chips in a vertical direction in the same package without changing the size of the package, and it is derived from a stacked package of a flash memory (NOR/NAND) and an SDRAM. The main characteristics include: multiple functions, high efficiency, large capacity, high density, multiple functions and applications in unit volume, low cost and the like.
The 3D package improves many properties of the chip, such as size, weight, speed, yield, and power consumption, but there are many structures and processes that need to be improved in the current 3D package.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a 3D package structure, which can improve the structure and process of the existing package.
In order to achieve the above object, an embodiment of the present invention provides a 3D package structure, where the 3D package structure includes a first group of chips, a second group of chips, a substrate, and external solder balls, where the substrate has a first surface and a second surface opposite to each other, and the first surface and the second surface have connection points thereon, the connection points are arranged according to connection lines in the substrate, the first group of chips and the second group of chips are flip chips, the first group of chips are connected to the first surface of the substrate through the connection points, the second group of chips are connected to the second surface of the substrate through the connection points, the external solder balls are connected to the first surface of the substrate, and communication among internal chips of the first group of chips, among internal chips of the second group of chips, and between the first group of chips and the second group of chips is performed through the connection lines in the substrate.
Optionally, the connection point is a solder ball or a copper core solder ball.
Optionally, the melting point of the connection point of the first surface is higher than the melting point of the connection point of the second surface.
Optionally, the external solder ball is a copper core solder ball.
Optionally, the height of the external solder balls is set according to the thickness of the first group of chips.
The embodiment of the present invention further provides a method for manufacturing a 3D package structure, where a substrate of the 3D package structure has a first surface and a second surface opposite to each other, and the first surface and the second surface both have connection points, the connection points are arranged according to connection lines in the substrate, the first group of chips and the second group of chips are flip chips, and the method for manufacturing the 3D package structure includes: connecting a first group of chips to the first surface of the substrate through the connecting points; connecting a second group of chips to the second surface of the substrate through the connecting points; and connecting external solder balls on the first surface of the substrate, wherein communication is performed among the internal chips of the first group of chips, among the internal chips of the second group of chips, and between the first group of chips and the second group of chips through connecting lines in the substrate.
Optionally, the first group of chips is connected to the first surface of the substrate and the second group of chips is connected to the second surface of the substrate by a thermocompression bonding or copper pillar and solder cap process.
Optionally, after the second group of chips is connected to the second surface of the substrate through the connection points, the method for manufacturing the 3D package structure further includes: and performing underfill or mold coating between the second group of chips and the second surface.
Optionally, the external solder ball is a copper core solder ball.
Optionally, the height of the external solder balls is set according to the thickness of the first group of chips.
Through the technical scheme, in the 3D packaging structure provided by the embodiment of the invention, the substrate is provided with the double-sided connection points, so that the first group of chips and the second group of chips can be vertically connected, signals are transmitted through the shortest distance, the signal delay and distortion can be reduced, and the bandwidth is improved; the chips are not directly stacked, and heat dissipation cannot interfere with each other.
Additional features and advantages of embodiments of the present invention will be described in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention and not to limit the embodiments of the invention. In the drawings:
fig. 1 is a schematic cross-sectional structure diagram of a 3D package structure according to an embodiment of the invention;
fig. 2 is a schematic top view of a 3D package structure provided in an embodiment of the invention;
fig. 3A is a schematic view of a cross-sectional structure of an example 3D package structure;
fig. 3B is a schematic top view of an example 3D package structure;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a 3D package structure according to an embodiment of the present invention;
fig. 5A-5C are schematic diagrams illustrating steps of fabricating an example 3D package structure.
Description of the reference numerals
1-a first set of chips; 2-a second set of chips; 3-a substrate; 4-external solder balls.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic cross-sectional structure diagram of a 3D package structure according to an embodiment of the present invention; fig. 2 is a schematic top view of a 3D package structure provided in an embodiment of the present invention, please refer to fig. 1 and fig. 2, where the 3D package structure includes a first group of chips 1, a second group of chips 2, a substrate 3, and external solder balls 4, where the substrate 3 has a first surface and a second surface opposite to each other, and the first surface and the second surface both have connection points, the connection points are arranged according to connection lines in the substrate 3, the first group of chips and the second group of chips are flip chips, the first group of chips 1 is connected to the first surface of the substrate 3 through the connection points, the second group of chips 2 is connected to the second surface of the substrate 3 through the connection points, and the external solder balls 4 are connected to the first surface of the substrate 3.
There are many structures and processes that need improvement in current 3D packaging. For example, in the existing 3D packaging technology, two chips are adjacent to each other and connected side by side, the wiring of the side-to-side connection is greatly limited by the line width and the line distance, the number of wiring layers needs to be increased to increase the density of the wiring, and a relatively long wire connection is needed. The increase in wire length reduces transmission bandwidth. The embodiment of the invention reduces the distance between the chips and improves the bandwidth by the surface interconnection in the vertical direction between the chips, and the mode does not need too much wiring. The surface-to-surface interconnection can also dissipate heat through two surfaces, and the heat dissipation efficiency is high.
The first group of chips 1 may include one or more chips, and the second group of chips 3 may also include one or more chips, and the internal chips of the first group of chips 1, the internal chips of the second group of chips 2, and the first group of chips 1 and the second group of chips 2 communicate with each other through a connection line (e.g., a wire) in the substrate 3.
The connecting wires (such as wires) are arranged in the substrate instead of external connecting wires (such as wire-bonding), so that the communication distance can be further shortened, the arrangement of the wires can be flexibly designed according to communication among multiple chips, the complexity of the circuit design of the 3D packaging structure can be enhanced, and the packaging structure is more suitable for high-end products.
In the 3D packaging structure of the embodiment of the invention, the substrate 3 is provided with double-sided connection points, so that the first group of chips 1 and the second group of chips 2 can be vertically connected, signals are transmitted through the shortest distance, signal delay and distortion can be reduced, and the bandwidth is improved; the chips are not directly stacked, and heat dissipation cannot interfere with each other.
Further, the first set of chips and the second set of chips are flip chips. Flip chip (Flip chip) is a leadless structure that deposits connection points (e.g., solder balls) on I/O pads, and then turns the chip over and heats it to bond the melted connection points to the substrate, replacing conventional wire bonding. The chip structure and the I/O end of the packaging form are downward, face-to-face connection is realized, the number of I/O channels is increased, the length of a lead of the I/O is shortened, and the bandwidth of information transmission is greatly improved. In addition, the chips are positioned on two sides of the substrate, so that the heat dissipation of the chips is facilitated.
Substrate materials (substrates) are basic materials for manufacturing semiconductor devices and printed circuit boards, for example, silicon, gallium arsenide, silicon epitaxial needle garnet, etc., which are materials used in the semiconductor industry. From the viewpoint of materials, the substrate may include an inorganic substrate and an organic substrate. Inorganic substrates (e.g., ceramic substrates) are generally made of high-purity alumina (alumina) as a main raw material by high-pressure molding, high-temperature firing, cutting, and polishing, and ceramic substrates are basic materials for manufacturing thin-film circuits such as radio frequency circuits, optical devices, and high-heat dissipation devices. The organic substrate is an important component of modern chips such as a Central Processing Unit (CPU), an image processing unit (GPU) and artificial intelligence, and is a bridge between the chips and external circuits. The substrate plays the following roles in the package: 1) The transmission of current and signals between the chip and the outside is realized; 2) Mechanically protecting and supporting the chip; 3) The method is a main way for radiating heat from the chip to the outside; 4) Is a spatial transition between the chip and the external circuitry.
The preferred connection point of the embodiment of the invention is a solder ball or a copper core solder ball.
Preferably, the melting point of the point of attachment of the first surface may be higher than the melting point of the point of attachment of the second surface.
By way of example, the first and second sets of chips 1 and 2 may be bonded to both surfaces of the substrate 3 using a high melting point Solder or 100% metal Compound (IMC) with Copper stud and Solder Cap (C2). If the connection point is a solder ball, if the first group of chips 1 are manufactured and connected and then the second group of chips 2 are manufactured and connected in the process of manufacturing the 3D packaging structure, the melting point of the connection point of the first surface is higher than that of the connection point of the second surface so as to prevent the connection of the first group of chips 1 from being influenced when the second group of chips 2 are manufactured; however, if the second group of chips 2 is manufactured and connected first group of chips 1 is manufactured and connected first group of chips 2, the melting point of the connection point of the second surface is higher than that of the connection point of the first surface, so that the connection of the second group of chips 2 is prevented from being affected when the first group of chips 1 are manufactured.
The external solder ball 4 is preferably a copper core solder ball, so that the problem of short circuit caused by excessive collapse when the substrate is connected with the external solder ball 4 can be solved.
The height of the external solder balls 4 is preferably set according to the thickness of the first group of chips 1.
By way of example, when the external solder balls 4 are manufactured on the substrate 3, the external solder balls 4 have a preset interval therebetween, so as to prevent short circuit caused by solder between the external solder balls during melting. The height is preferably controlled using solder balls of copper core, which is set according to the thickness of the first set of chips 1.
Fig. 3A, 3B show that the first set of chips 1 comprises one chip and the second set of chips 2 comprises a stack of 4 chips. The chip 2, the chip 3, the chip 4 and the chip 5 can be directly connected with the chip 1 through a short distance, the chip 1 is, for example, a CPU or a GPU, and the chip 2, the chip 3, the chip 4 and the chip 5 are, for example, a memory chip, a peripheral chip of a north-south bridge, an artificial intelligence chip for machine learning, a chip for power management, a chip for communication, and the like.
Fig. 4 is a schematic flow chart of a manufacturing method of a 3D package structure according to an embodiment of the present invention, please refer to fig. 4, where a substrate 3 of the 3D package structure has a first surface and a second surface opposite to each other, and the first surface and the second surface both have connection points, the first group of chips and the second group of chips are flip chips, and the connection points are arranged according to connection lines in the substrate, and the manufacturing method of the 3D package structure may include the following steps:
step S110: a first set of chips 1 is attached to a first surface of the substrate 3 via the connection points.
Preferably, the first group of chips 1 is attached to the first surface of the substrate 3 by Thermal Compression Bonding (TCB) or a copper-stud-and-solder cap C2 process.
Referring to fig. 5A, taking the first group of chips 1 as an example, connecting wires are arranged inside the substrate 3, if the substrate 3 is warped too much, the substrate 3 can be fixed on a carrier through the second surface, and the first group of chips 1 are connected to the first surface of the substrate 3 through the high melting point solder of the TCB or C2 process.
The connecting wires (such as wires) are arranged in the substrate instead of external connecting wires (such as wire-bonding), so that the communication distance can be further shortened, the arrangement of the wires can be flexibly designed according to communication among multiple chips, the complexity of the circuit design of the 3D packaging structure can be enhanced, and the packaging structure is more suitable for high-end products.
Further, the first group of chips and the second group of chips are flip chips. Flip chip (Flip chip) is a leadless structure that deposits connection points (e.g., solder balls) on I/O pads, and then turns the chip over and heats it to bond the melted connection points to the substrate, replacing conventional wire bonding. The chip structure and the I/O end of the packaging form are downward, so that the heat dissipation of the chip is facilitated.
Step S120: a second set of chips 2 is attached to a second surface of the substrate 3 via the connection points.
Preferably, the second group of chips are connected to the second surface of the substrate by a thermocompression bonding or copper pillar and solder cap process.
Referring to fig. 5A and 5B, in accordance with the above example, the carrier on the second surface is removed, and the first group of chips 1 are connected to the first surface of the substrate 3 through the high melting point solder of TCB or C2 process, wherein the melting point of the connection point on the first surface is higher than that of the connection point on the second surface, so as to prevent the connection of the first group of chips 1 from being affected when the second group of chips 2 are manufactured.
It should be noted that, in the embodiment of the present invention, the sequence of step S110 and step S120 may be changed, that is, the second group of chips 2 may be manufactured and connected first, and then the first group of chips 1 may be manufactured and connected, so that the melting point of the connection point on the second surface is higher than the melting point of the connection point on the first surface, so as to prevent the connection of the second group of chips 2 from being affected when the first group of chips 1 is manufactured.
Preferably, in the embodiment of the present invention, after step S120, the method for manufacturing a 3D package structure further includes: an underfill or mold compound is applied between the second set of chips 2 and the second surface.
Step S130: and connecting external solder balls to the first surface of the substrate.
The internal chips of the first group of chips, the internal chips of the second group of chips and the first group of chips and the second group of chips are communicated through connecting lines in the substrate.
The external solder ball is preferably a copper core solder ball.
Preferably, the height of the external solder balls is set according to the thickness of the first group of chips 1.
Referring to fig. 5C, to support the above example, when the external solder balls 4 are formed on the substrate 3, a predetermined interval is formed between the external solder balls 4 to prevent short circuit caused by melting solder between the external solder balls. The height is preferably controlled using solder balls of copper core, which is set according to the thickness of the first group of chips 1.
Accordingly, the substrate 3 has double-sided connection points, so that the first group of chips 1 and the second group of chips 2 can be vertically connected, signals can be transmitted through the shortest distance, signal delay and distortion can be reduced, and the bandwidth is improved; the chips are not directly stacked, and heat dissipation cannot interfere with each other.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A3D package structure is characterized in that the 3D package structure comprises a first group of chips, a second group of chips, a substrate and an external solder ball,
wherein the substrate has a first surface and a second surface opposite to each other, and the first surface and the second surface are both provided with connection points which are arranged according to connection lines in the substrate,
the first group of chips with the second group of chips is the flip chip, first group of chips passes through the tie point is connected the first surface of base plate, the second group of chips passes through the tie point is connected the second surface of base plate, external solder ball is connected the first surface of base plate, communicate between the inside chip of first group of chips, between the inside chip of second group of chips and between first group of chips with between the second group of chips through connecting wire in the base plate.
2. The 3D package structure of claim 1, wherein the connection points are solder balls or copper core solder balls.
3. The 3D package structure of claim 1, wherein a melting point of the connection point of the first surface is higher than a melting point of the connection point of the second surface.
4. The 3D package structure of claim 1, wherein the external solder ball is a copper core solder ball.
5. The 3D packaging structure according to claim 4, wherein the height of the external solder balls is set according to the thickness of the first group of chips.
6. A manufacturing method of a 3D packaging structure is characterized in that a substrate of the 3D packaging structure is provided with a first surface and a second surface which are opposite, connecting points are arranged on the first surface and the second surface according to connecting lines in the substrate, the first group of chips and the second group of chips are flip chips, and the manufacturing method of the 3D packaging structure comprises the following steps:
connecting a first group of chips to the first surface of the substrate through the connecting points;
connecting a second group of chips to the second surface of the substrate through the connecting points; and
connecting an external solder ball on the first surface of the substrate,
the internal chips of the first group of chips, the internal chips of the second group of chips and the first group of chips and the second group of chips are communicated through connecting wires in the substrate.
7. The method of claim 6, wherein the first group of chips are connected to the first surface of the substrate and the second group of chips are connected to the second surface of the substrate by thermocompression bonding or copper pillar and solder cap process.
8. The method for manufacturing a 3D package structure according to claim 6 or 7, wherein after the connecting the second group of chips to the second surface of the substrate through the connecting points, the method for manufacturing a 3D package structure further comprises:
and performing underfill or mold-coating between the second group of chips and the second surface.
9. The method of claim 6, wherein the external solder ball is a copper core solder ball.
10. The method for manufacturing a 3D package structure according to claim 9, wherein a height of the external solder balls is set according to a thickness of the first group of chips.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116093075A (en) * | 2023-04-10 | 2023-05-09 | 北京华封集芯电子有限公司 | Chip and design method for realizing interconnection of various chips |
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