KR20010036834A - Charge pump voltage multiplier circuit - Google Patents

Abstract

PURPOSE: A charge pump voltage multiplier is provided whose pumping capacitor is replaced by a MOS capacitor to minimize the number of masks used in the fabrication process, reducing manufacturing cost and time. CONSTITUTION: A charge pump voltage multiplier(100) receives the complimentary first and second pulse signals to generate a boosted voltage higher than the power supply voltage. The multiplier includes the first pumping capacitor connected between the first pulse signal and the first node, and the second pumping capacitor connected between the second pulse signal and the second node. The multiplier further has the first MOS transistor having a current path formed between the power supply and the first node, the second MOS transistor having a current path formed between the power supply and the second node, the third MOS transistor having a current path formed between the first node and a boosted voltage output node, and the fourth MOS transistor having a current path formed between the second node and the boosted voltage output node. The gates of the first and third transistors are connected to the second node, and the gates of the second and fourth transistors are connected to the first node. The multiplier also has the first pre-charge unit for pre-charging the first node when the power supply voltage is initially provided, and the second pre-charge unit for pre-charging the second node when the power supply voltage is initially supplied.

Description

Charge Pump Voltage Multiplier Circuit {CHARGE PUMP VOLTAGE MULTIPLIER CIRCUIT}

TECHNICAL FIELD The present invention relates to semiconductor integrated circuits and, more particularly, to voltage multiplier circuits.

As is well known, many applications for semiconductor integrated circuits require a voltage higher than the supply voltage. For example, nonvolatile memories such as EEPROM or flash EEPROM require a read voltage higher than the supply voltage. This high voltage is typically generated by a voltage multiplier (or booster) circuit integrated with the memory circuit.

1 is a circuit diagram showing a conventional charge pump voltage multiplier.

Referring to FIG. 1, a conventional charge pump voltage multiplier circuit includes a voltage multiplier 10 and a ring oscillator 20. The ring oscillator 20 includes a NAND gate ND1 and 14 inverters I3 to I16. The NAND gate ND1 receives a start signal START input from the outside and an output signal of the last inverter I16 to perform a NAND operation. The inverters I3 to I16 are sequentially arranged in series between the output terminal of the NAND gate ND1 and the one input terminal of the NAND gate ND1. By adjusting the number of the inverters and the size of the transistors constituting the inverter can be obtained a pulse signal having a desired oscillation frequency. In addition, the desired charge pumping speed can be achieved regardless of the clock speed of other circuits. First and second pulse signals CK and CKB, which are output signals of the inverters I3 and I4, are provided to the voltage multiplier 10. The first and second pulse signals CK and CKB are complementary signals.

The voltage multiplier 10 receives inverters I1 and I2 and inverts the first and second pulse signals CK and CKB output from the ring oscillator 20, respectively, and the inverters I1 and I2. NMOS transistors MN1 and MN2 connected between the capacitors C1 and C2, the power supply voltage VDD and the nodes N1 and N2 which are one end of the capacitors, respectively. PMOS transistors MP1 and MP2 connected between N1 and N2 and the boosted voltage Vboost output terminal, and a capacitor C3.

Gates of the NMOS transistor MN1 and the PMOS transistor MP1 are connected to the second node N2, respectively, and are controlled by the first pulse signal CK, and the NMOS transistor MN2 and the PMOS transistor MP2 are respectively connected to the second node N2. Gates are respectively connected to the first node N1 and controlled by the second pulse signal CKB.

MOS capacitors not only have a larger capacitor capacity per unit area than conventional capacitors, but also minimize the number of masks in the production process, thereby reducing production time and cost. However, the voltage multiplier 10 having the configuration as described above cannot configure the pumping capacitors C1 and C2 as MOS capacitors. This is because the MOS capacitor may operate as a capacitor by forming a channel between the source and drain terminals when the gate voltage is higher than the threshold voltage Vth. When the supply of the power voltage VDD is started, the nodes N1 N2) maintains the ground voltage level.

Accordingly, an object of the present invention is to provide a charge pumping voltage multiplier circuit comprising a charge pumping capacitor as a MOS capacitor.

1 is a circuit diagram of a conventional charge pump voltage multiplier; And

2 is a circuit diagram of a charge pump voltage multiplier according to a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: voltage multiplier 200: ring oscillator

According to a feature of the present invention for achieving the object of the present invention as described above, a charge pump voltage multiplier circuit which receives complementary first and second pulse signals to generate a boosted voltage higher than the power supply voltage comprises: And a first pumping capacitor connected between the pulse signal and the first node and a second pumping capacitor connected between the second pulse signal and the second node. The first MOS transistor has a current path formed between the power supply voltage and the first node and a gate connected to the second node. The second MOS transistor has a current path formed between the power supply voltage and the second node and a gate connected to the first node. The third MOS transistor has a current path formed between the first node and the boosted voltage output node and a gate connected to the second node. The fourth MOS transistor has a current path formed between the second node and the boosted voltage output node and a gate connected to the first node. Moreover, the charge pump voltage multiplier circuit includes first precharge means for precharging the first node when the power supply voltage is started and a second precharge for precharging the second node when the power supply voltage supply is started. Charging means.

In a preferred embodiment, the first and second pumping capacitors each consist of a MOS capacitor.

In a preferred embodiment, the first precharge means comprises a fifth MOS transistor having a current path formed between the power supply voltage and the first node and a gate connected to the power supply voltage, wherein the second precharge means And a sixth MOS transistor having a current path formed between the power supply voltage and the second node and a gate connected to the power supply voltage.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 shows a charge pump voltage multiplier circuit according to a preferred embodiment of the present invention.

2, a charge pump voltage multiplier circuit according to a preferred embodiment of the present invention includes a voltage multiplier 100 and a ring oscillator 200. The ring oscillator 200 includes a NAND gate ND1 and 14 inverters I3 to I16. The NAND gate ND1 receives a start signal START input from the outside and an output signal of the last inverter I16 to perform a NAND operation. The inverters I3 to I16 are sequentially arranged in series between the output terminal of the NAND gate ND1 and the one input terminal of the NAND gate ND1.

The ring oscillator 200 operates while the start signal START is at a high level. When the start signal START is high level and the output signal of the last inverter I16 is high level, the NAND gate ND1 outputs a low level signal. After the output signal of the NAND gate ND1 passes through the inverters I3 to I16, the signal output from the last inverter I16 becomes low level. Therefore, the NAND gate ND1 outputs a high level signal. That is, the first and second pulse signals CK and CKB respectively output from the inverters I3 and I4 alternate between high level and low level every predetermined time while the start signal START is at the high level. Becomes a pulse signal.

The frequency of the first and second pulse signals CK and CKB may be changed by adjusting the number of the inverters and the size of a transistor constituting the inverter. First and second pulse signals CK and CKB, which are output signals of the inverters I3 and I4, are provided to the voltage multiplier 10. The first and second pulse signals CK and CKB are complementary signals.

The voltage multiplier 10 receives inverters I1 and I2 and inverts the first and second pulse signals CK and CKB output from the ring oscillator 20, respectively, and the inverters I1 and I2. NMOS transistors MN1 and MN2 connected between the pumping capacitors C1 and C2, the power supply voltage VDD, and the nodes N1 and N2 which are one end of the capacitors, respectively. NMOS transistors MN3 and MN4 connected between VDD and the nodes N1 and N2, and PMOS transistors MP1 connected between the nodes N1 and N2 and a boosted voltage output terminal, respectively. MP2), and capacitor C3. In this embodiment, the pumping capacitors C1 and C2 are composed of MOS capacitors.

Gates of the NMOS transistor MN1 and the PMOS transistor MP1 are connected to the second node N2, respectively, and are controlled by the first pulse signal CK, and the NMOS transistor MN2 and the PMOS transistor MP2 are respectively connected to the second node N2. Gates are respectively connected to the first node N1 and controlled by the second pulse signal CKB. Gates of the NMOS transistors MN3 and MN4 are connected to the power supply voltage VDD, respectively.

The voltage multiplier 100 having the configuration as described above operates as follows. When power is initially supplied to the voltage multiplier 100, the first and second nodes N1 and N2 are precharged to the level of (VDD-Vth) by the NMOS transistors MN3 and MN4. Therefore, a channel is formed between the source and drain terminals of the pumping capacitors C1 and C2 composed of MOS capacitors. Since the NMOS transistors MN3 and MN4 are initially used to precharge the first and second nodes N1 and N2, very small transistors may be used. Therefore, the configuration of the NMOS transistors MN3 and MN4 does not cause a problem of increasing the overall size of the voltage multiplier 100.

As the start signal START is activated from a low level to a high level, the ring oscillator 200 starts an oscillation operation. When the first pulse signal CK output from the inverter I3 is at a high level (logical '1'), the second pulse signal CKB output from the inverter I4 is at a low level (logical '0'). do.

As the output signal of the inverter I1 becomes high in response to the first pulse signal CK, the first node N1 is set to a level of (VDD-Vth + VDD) so that the NMOS transistor MN2 Is turned on, and the PMOS transistor MP2 is turned off. The voltage of the first node N1 is output as a boosted voltage Vboost through the PMOS transistor MP1.

On the other hand, in response to the second pulse signal CKB, the output signal of the inverter I2 becomes low level, and the second node N2 is set to the power supply voltage VDD level.

Subsequently, when the first pulse signal CK and the second pulse signal CKB transition to the high level and the low level, respectively, the first node N1 becomes the (VDD) level and the second node ( N2) is set to the (2VDD) level. Therefore, the PMOS transistor MP1 is turned on so that the voltage 2VDD of the second node N2 is output as the boosted voltage Vboost. As the second node N2 is boosted to the (2VDD) level, the first NMOS transistor MN1 is turned on and the first node N1 is precharged to the (VDD) level.

When the first pulse signal CK and the second pulse signal CKB transition to the low level and the high level, respectively, the second node N2 becomes the (VDD) level, and the first node N1 Is stepped up to the ground voltage (2VDD) level. Accordingly, the PMOS transistor MP1 is turned on so that the voltage 2VDD of the first node N1 is output as the boosted voltage Vboost.

As the first pulse signal CK and the second pulse signal CKB transition to the high level and the low level, the above-described processes are repeated, and thus the first node N1 and the second node N2 The voltage is alternately output as a boosted voltage Vboost. Therefore, the boosted voltage Vboost maintains the (2VDD-Vth) level.

As described above, the charge pump voltage multiplier circuit of the present invention can replace the pumping capacitors C1 and C2 with MOS capacitors by adding the precharge transistors MN3 and MN4. MOS capacitors not only have a larger capacitor capacity per unit area than conventional capacitors, but also minimize the number of masks in the production process, thereby reducing production time and cost.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, the pumping capacitor configured in the charge pump voltage multiplier circuit can be replaced by the MOS capacitor. Therefore, it is possible to minimize the number of masks in the production process has the effect of reducing the production cost and production time.

Claims (3)

In a charge pump voltage multiplier circuit that accepts complementary first and second pulse signals and generates a boost voltage higher than the supply voltage: A first pumping capacitor coupled between the first pulse signal and a first node; A second pumping capacitor coupled between the second pulse signal and a second node; A first MOS transistor having a current path formed between the power supply voltage and the first node and a gate connected to the second node; A second MOS transistor having a current path formed between the power supply voltage and the second node and a gate connected to the first node; A third MOS transistor having a current path formed between the first node and a boosted voltage output node and a gate connected to the second node; A fourth MOS transistor having a current path formed between the second node and the boosted voltage output node and a gate connected to the first node; First precharge means for precharging the first node when the power supply voltage is started; And And a second precharge means for precharging said second node when said supply voltage supply is initiated. The method of claim 1, And the first and second pumping capacitors are each MOS capacitors. The method of claim 1, The first precharge means includes a fifth MOS transistor having a current path formed between the power supply voltage and the first node and a gate connected to the power supply voltage, and the second precharge means includes the power supply voltage and the first voltage. A charge pump voltage multiplier circuit comprising a sixth MOS transistor having a current path formed between two nodes and a gate connected to the power supply voltage.