JPH05234390A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To operate an internal circuit within the wide range of an external power-supply voltage regarding an internal power-supply circuit wherein, when the external power-supply voltage is a predetermined voltage or higher, the external power-supply voltage as it is applied to the internal circuit as an internal power-supply voltage and, when the external power-supply voltage is lower than the predetermined voltage, it is boosted and the internal power-supply voltage is generated. CONSTITUTION:A voltage detection circuit 11 detects whether an external power-supply voltage VE applied from the outside of a semiconductor chip is lower than a predetermined reference voltage VR or not. A boosting circuit 12 generates a boosted-voltage VSU which has boosted the external power- supply voltage VE when the external power-supply voltage VE is lower than the reference voltage VR. A changeover circuit 13 uses the boosted voltage VSU as an internal power-supply voltage VI and supplied it to individual internal circuits inside the semiconductor chip when the external power-supply voltage VE is lower than the reference voltage VR; it supplies the external power- supply voltage VE to the individual internal circuits when the internal power- supply voltage VE is equal to or higher than the reference voltage VR.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more specifically, when the external power supply voltage is equal to or higher than a predetermined voltage, the external power supply voltage is directly supplied to the internal circuit as the internal power supply voltage. The present invention relates to an internal power supply circuit that boosts a voltage when the voltage is lower than a predetermined voltage to generate an internal power supply voltage.

In recent years, in semiconductor integrated circuit devices, it has been required to widen the range of operable external power supply voltage. In particular, low voltage operation is required in the address decoder of EPROM.

[0003]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit device capable of operating in a wide external power supply voltage range is manufactured by a special process different from a manufacturing process of a normal semiconductor integrated circuit device capable of operating only at a constant external power supply voltage. It was manufactured.

[0004]

However, since a special manufacturing process complicates the manufacturing process and increases the number of steps, there is a problem that the manufacturing cost increases and the yield deteriorates.

The present invention has been made to solve the above problems, and an object thereof is to provide an internal power supply circuit capable of operating an internal circuit of a semiconductor integrated circuit device in a wide external power supply voltage range. To do.

[0006]

In order to solve the above problems, the present invention provides a voltage detection circuit for detecting whether an external power supply voltage applied from outside the semiconductor chip is lower than a predetermined reference voltage, and an external voltage detection circuit. When the power supply voltage is lower than the reference voltage, the booster circuit that generates the boosted voltage by boosting the external power supply voltage, and when the external power supply voltage is lower than the reference voltage, supplies the boosted voltage to each internal circuit in the semiconductor chip as the internal power supply voltage. However, the gist of the invention is to include a switching circuit that supplies the external power supply voltage to each internal circuit as the internal power supply voltage when the external power supply voltage is equal to or higher than the reference voltage.

[0007]

Therefore, according to the present invention, since the desired internal power supply voltage can be supplied to each internal circuit even when the external power supply voltage is low, the internal circuit can be operated in a wide external power supply voltage range.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. As shown in FIG. 1, the voltage detection circuit 11 detects the voltage VE of the external power supply VE and outputs a low level detection signal S when the external power supply voltage VE is equal to or higher than a predetermined reference voltage VR, When the power supply voltage VE is lower than a predetermined reference voltage VR, a high level detection signal S is output.

The booster circuit 12 has a high level detection signal S.
The boosted voltage VSU is generated by boosting the external power supply voltage VE based on the above. The switching circuit 13 supplies the boosted voltage VSU as the internal power supply voltage VI to each internal circuit based on the high level detection signal S, and supplies the external power supply voltage VE as the internal power supply voltage VI as the internal power supply voltage VI based on the low level detection signal S. Supply to internal circuit.

FIG. 2 is a circuit diagram of the voltage detection circuit 11.
The diode-connected P-channel MOS transistors 21 to 23 are connected in series between the external power supply VE and the ground. That is, the MOS transistor 23
Of the MOS transistor 2 is connected to the ground
The gate of 2 is connected to the source of the MOS transistor 23, and the gate of the MOS transistor 21 is connected to the source of the MOS transistor 22.

Further, the P-channel MOS transistor 2
Reference numerals 4 and 25 are connected in series between the external power source VE and the ground, the gate of the MOS transistor 24 is connected to the node a between the MOS transistors 22 and 23, and the gate of the MOS transistor 25 is connected to the ground.

Then, the detection signal S is output from the node b between the MOS transistors 24 and 25. Each MOS
The transistors 21 to 25 are formed with the same transistor size.

Therefore, each MOS transistor 23, 25
Is always on. Then, the MOS transistor 21
When the total value (= 3Vth) of the threshold voltages Vth of (3) to (23) is less than or equal to the external power supply voltage VE (3Vth≤VE), each MOS
Since the transistors 21 to 23 are turned on, the node a becomes a high level (a voltage higher than the total value (= 2Vth) of the threshold voltages Vth of the MOS transistors 24 and 25).
Then, the MOS transistor 24 is turned off, the node b becomes low level, and the low level detection signal S is output.

When the external power supply voltage VE is lower than the total value (= 3Vth) of the threshold voltages Vth of the MOS transistors 21 to 23 (3Vth> VE), the MOS transistor 21 is turned off. Then, the MOS transistor 2
Since node 2 is cut off from the external power supply VE, the node a becomes low level (a voltage lower than the total value (= 2Vth) of the threshold voltages Vth of the MOS transistors 24 and 25). Therefore, the MOS transistor 24 is turned on, the node b becomes high level, and the high level detection signal S is output.

As described above, the voltage detection circuit 11 detects the low level signal when the external power supply voltage VE is equal to or higher than the predetermined reference voltage VR (the total value of the threshold voltages Vth of the MOS transistors 21 to 23). S is output, and when the external power supply voltage VE is lower than a predetermined reference voltage VR (total value of threshold voltages Vth of the MOS transistors 21 to 23), a high level detection signal S is output.

Since all the MOS transistors 21 to 25 constituting the voltage detection circuit 11 are P-channel and have the same transistor size, they are manufactured in the same process, so that the threshold voltage V of each of the MOS transistors 21 to 25 is reduced.
It is extremely easy to make all th equal. Therefore, the reference voltage VR can be set accurately.

FIG. 3 is a circuit diagram of the booster circuit 12. The drains of the N-channel MOS transistors 31 to 34 and the gates of the MOS transistors 31 and 34 are connected to the external power supply VE. Also, the MOS transistor 3
The sources of 1 and 32 are connected to each other, and the sources of the MOS transistors 33 and 34 are connected to each other.

One input terminal of the NAND circuit 35 is connected to the clock generation circuit 36 to receive the clock signal CL, and the other input terminal is connected to the node b of the voltage detection circuit 11 to receive the detection signal S. There is. The output of the NAND circuit 35 is input to the inverter circuit 38 via the inverter circuit 37.

A capacitor 39 is connected between the output terminal (node c) of the inverter circuit 37 and each source (node d) of the MOS transistors 31 and 32, and the output terminal (node e) of the inverter circuit 38 and the MOS transistor. A capacitor 40 is connected between each of the sources 33 and 34 (node f).

A diode-connected P channel M is connected between the node g and the node f which are output terminals of the booster circuit 12.
The OS transistor 41 is connected, and the capacitor 42 is connected between the node g and the ground. Then, the boosted voltage VSU is output from the node g.

Therefore, when the high-level detection signal S is input from the voltage detection circuit 11, the output of the NAND circuit 35 is inverted every time the clock signal CL of the clock generation circuit 36 is inverted, and accordingly, each node c. , E are also alternately inverted. Further, since the MOS transistors 31 and 34 are always on, the voltage of the node d becomes higher than the voltage reduced from the external power supply voltage VE by the threshold voltage of the MOS transistor 31, and the MOS transistor 34 from the external power supply voltage VE. The voltage of the node f becomes higher than the voltage lowered by the threshold voltage of. Therefore, as the levels of the nodes c and e are alternately inverted, the respective capacitors 39 and 4 are
By charging / discharging 0, the levels of the nodes d and f are alternately inverted, and the MOS transistors 32 and 33 are alternately turned on / off.
Repeat off. Therefore, the level of the node f rises above the external power supply voltage VE, and the charging current flows into the capacitor 42. Incidentally, the diode-connected MOS transistor 4
Since the current does not flow from the capacitor 42 to the node f due to 1, the potential of the node g, which is the charging voltage of the capacitor 42, that is, the boosted voltage VSU is the external power supply voltage VE.
Rise more.

On the other hand, when the low-level detection signal S is input from the voltage detection circuit 11, even if the clock signal CL of the clock generation circuit 36 is inverted, the output of the NAND circuit 35 is not inverted, and each node c, e. Does not reverse the level of. Therefore,
The above boosting operation does not occur, and the boosted voltage VSU does not rise above the voltage which is lower than the external power supply voltage VE by the threshold voltage of the MOS transistor 34. Therefore, when the detection signal S is low level, the booster circuit 12 does not consume power.

FIG. 4 is a circuit diagram of the switching circuit 13.
The source of the P-channel MOS transistor 51 is connected to the external power supply VE, the source of the P-channel MOS transistor 52 is connected to the node g of the booster circuit 12, and the boosted voltage VSU is input. The gate of the MOS transistor 51 is connected to the node b of the voltage detection circuit 11 to receive the detection signal S, and the gate of the MOS transistor 52 is connected to the node b via the inverter circuit 53 to invert the signal S of the detection signal S. Has been entered. And MOS
The internal power supply voltage VI is output from the connection point (node h) of the drains of the transistors 51 and 52.

Therefore, when the high-level detection signal S is input from the voltage detection circuit 11, the MOS transistor 52
Turns on and the MOS transistor 51 turns off. Therefore, the boosted voltage VSU input from the booster circuit 12 is output as the internal power supply voltage VI. When the low-level detection signal S is input, the MOS transistor 51 turns on and the MOS transistor 52 turns off. Therefore, the external power supply voltage VE is output as the internal power supply voltage VI.

As described above, in this embodiment, when the external power supply voltage VE is equal to or higher than the predetermined reference voltage VR, the external power supply voltage VE is directly supplied to the internal circuit as the internal power supply voltage VI, and the external power supply voltage VE is When it is lower than a predetermined reference voltage VR, the voltage is boosted to generate the internal power supply voltage VI.

Therefore, the desired internal power supply voltage VI can be supplied to the internal circuit even when the external power supply voltage VE is low.
The internal circuit can be operated in a wide range of the external power supply voltage VE.

The present invention is not limited to the above embodiment, and for example, in the voltage detection circuit 11, the P channel MOS transistors 21 to 25 may have different transistor sizes. Further, each P-channel MOS transistor 21-23 is composed of two P-channel MOS transistors having different transistor sizes,
Alternatively, four or more P-channel MOS transistors having the same or different transistor sizes may be replaced for implementation.

[0028]

As described in detail above, according to the present invention, there is an excellent effect that an internal circuit can be operated in a wide range of external power supply voltage.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment embodying the present invention.

FIG. 2 is a circuit diagram of a voltage detection circuit according to an embodiment.

FIG. 3 is a circuit diagram of a booster circuit according to an embodiment.

FIG. 4 is a circuit diagram of a switching circuit according to an embodiment.

[Explanation of symbols]

 11 voltage detection circuit 12 booster circuit 13 switching circuit VE external power supply voltage VR reference voltage VSU boosted voltage VI internal power supply voltage

Claims (1)

[Claims] 1. A voltage detection circuit (11) for detecting whether an external power supply voltage (VE) applied from outside the semiconductor chip is lower than a predetermined reference voltage (VR), and an external power supply voltage (VE). When it is lower than the reference voltage (VR), the boosted voltage (VSU) is the external power supply voltage (VE) boosted.
And a step-up circuit (12) for generating an internal power source voltage (VI) when the external power source voltage (VE) is lower than the reference voltage (VR). External power supply voltage (VE
) Is higher than the reference voltage (VR), the external power supply voltage (VE
) Is supplied as an internal power supply voltage (VI) to each internal circuit, and a switching circuit (13) is provided for the semiconductor integrated circuit device.