WO2011118119A1 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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Publication number
WO2011118119A1
WO2011118119A1 PCT/JP2011/000773 JP2011000773W WO2011118119A1 WO 2011118119 A1 WO2011118119 A1 WO 2011118119A1 JP 2011000773 W JP2011000773 W JP 2011000773W WO 2011118119 A1 WO2011118119 A1 WO 2011118119A1
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power supply
internal
voltage
semiconductor integrated
integrated circuit
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PCT/JP2011/000773
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French (fr)
Japanese (ja)
Inventor
中村敏宏
山崎裕之
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パナソニック株式会社
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Publication of WO2011118119A1 publication Critical patent/WO2011118119A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor

Definitions

  • the present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a memory.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • an internal power supply circuit in which an internal power supply voltage that is lower or higher than the external power supply voltage based on an external power supply is installed in the memory, more specifically, an internal step-down power supply block
  • an internal boost power supply block It is widely known that the voltage is generated by an internal boost power supply block and supplied to a memory. This is because it is difficult to directly supply the high voltage required inside the memory from the outside as the external power supply voltage is lowered, and the resistance to fluctuations in the power supply voltage inside and outside the SoC is improved. It is aimed.
  • Patent Document 1 As a publicly known example in which an internal power supply circuit is mounted in a memory, for example, according to Patent Document 1, there is a semiconductor integrated circuit in which a plurality of internal boost power supply blocks are mounted, and a plurality of internal boost power supply blocks according to the level of an external power supply voltage. An example is disclosed that realizes stable supply of the internal power supply voltage even when the external power supply voltage is lowered by selectively operating.
  • FIG. 5 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit having a conventional internal power supply circuit. The configuration and operation of the memory internal power supply circuit will be described below with reference to FIG.
  • the conventional internal power supply circuit includes an external power supply 501, an internal power supply 502, an internal step-down power supply 503, a first internal boost power supply block 504, a second internal boost power supply block 505, and an internal step-down power supply.
  • the block 506 includes a control signal generation circuit 507, a first internal boost power supply control circuit 508, and a second internal boost power supply control circuit 509.
  • the first internal boosting power supply block 504 performs a boosting operation based on the external power supply 501 and outputs the internal power supply 502.
  • the second internal boost power supply block 505 performs a boost operation based on the internal step-down power supply 503 and outputs the internal power supply 502.
  • the control signal generation circuit 507 when the external power source 501 is in the normal voltage range of about 3.3V, the control signal generation circuit 507 is at the L level.
  • 1 logic signal 510 is output and input to the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509.
  • the first internal boost power supply control circuit 508 is composed of a two-input NOR circuit, and the first logic signal 510 is input to one input, and the ground is input to the other input.
  • the second internal boost power supply control circuit 509 includes a two-input NAND circuit and an inverter circuit.
  • the first logic signal 510 is input to one of the two inputs of the NAND circuit, and the other input.
  • the external power source 501 is input to each.
  • the second logic signal 511 is sent from the first internal boost power supply control circuit 508 to the first internal boost power supply block 504, and the third logic signal is sent from the second internal boost power supply control circuit 509 to the second internal boost power supply block 505.
  • the logic signals 512 are respectively input. Both the first internal boost power supply block 504 and the second internal boost power supply block 505 are configured to perform a boost operation when the second logic signal 511 and the third logic signal 512 that are inputs are at the H level. .
  • the external power supply 501 is, for example, a voltage of 3.3 V
  • the internal power supply 502 supplied to the memory (not shown) is supplied to a row decoder (not shown) or a word driver (not shown) in the memory.
  • the supplied voltage is, for example, 3.6 V
  • the internal step-down power supply 503 is, for example, 2.3 V.
  • the control signal generation circuit 507 outputs an L level signal to the first logic signal 510.
  • the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509 respectively send an H level signal to the second logic signal 511.
  • an L level signal is output as the third logic signal 512.
  • the first internal boost power supply block 504 starts the boost operation based on the external power supply 501 and outputs the internal power supply 502.
  • the second internal boost power supply block 505 does not perform the boost operation based on the internal step-down power supply 503 because the third logic signal 512 that is the input signal from the previous stage is at the L level.
  • the first internal boost power supply block 504 performs a boost operation to supply the internal power supply 502 to the memory, and the second internal boost power supply block 505 boosts the voltage. Operation and current supply to the internal power supply 502 are not performed.
  • an H level signal is output from the control signal generation circuit 507 to the first logic signal 510.
  • the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509 respectively send an L level signal to the second logic signal 511.
  • an H level signal is output to the third logic signal 512.
  • the second internal boost power supply block 505 starts the boost operation based on the internal step-down power supply 503 and outputs the internal power supply 502.
  • the first internal boost power supply block 504 does not perform the boost operation because the second logic signal 511 that is the input signal from the previous stage is at the L level.
  • the second internal boost power source block 505 performs a boost operation to supply the internal power source 502 to the memory, and the first internal boost power source block 504 boosts the voltage. Operation and current supply to the internal power supply 502 are not performed.
  • the internal boost power supply block according to the voltage level of the original power supply that performs the boost operation If the external power supply is lowered to a predetermined voltage or lower and the internal step-down power supply block is used, the internal power generation is performed in two stages by stepping down the external power supply and then boosting it again Action is required.
  • the internal boost power supply block is generally equipped with an oscillator circuit or a pump circuit, as described above, it requires a very large circuit area as compared with the internal step-down power supply block.
  • the required circuit area is greatly increased, which greatly affects the increase in the chip area of the SoC as a whole.
  • the power consumed is smaller than when the internal power supply is generated only with the internal step-down power supply block.
  • the present invention has been made in view of such problems, and reduces the chip area and consumes power when generating internal power by an internal power supply circuit based on the external power and supplying the internal power to the memory.
  • An object of the present invention is to supply a stable internal power supply to a memory while suppressing an increase in power.
  • a first semiconductor integrated circuit includes an internal step-down power supply block that performs a step-down operation based on an external power supply, and an internal step-up operation that performs a step-up operation based on the external power supply.
  • a power supply block wherein when the external power supply is in a first voltage range, an internal power supply having a desired voltage is generated using only the internal step-down power supply block, and the external power supply is lower than the first voltage range.
  • the internal power supply of the desired voltage is generated using the internal boost power supply block in addition to or instead of the internal buck power supply block.
  • the second semiconductor integrated circuit of the present invention includes an internal step-down power supply block that performs a step-down operation based on a selected power supply, and an internal step-up power supply block that generates an internal boost power supply based on an external power supply.
  • the internal step-down power supply block When the external power supply is in the first voltage range, the internal step-down power supply block generates an internal power supply having a desired voltage from the external power supply, and the external power supply is lower than the first voltage range. Then, the internal step-down power supply block generates the internal power supply of the desired voltage from the internal boost power supply generated by the internal boost power supply block.
  • the present invention is an effective technique for a semiconductor integrated circuit that generates an internal power supply using an internal power supply circuit mounted inside based on an external power supply, while reducing the chip area and suppressing an increase in power consumption. It makes it possible to generate a stable internal power supply. Furthermore, the chip area can be further reduced by sharing a circuit to be used by a plurality of internal power supply blocks.
  • FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
  • FIG. 5 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.
  • FIG. 6 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. It is a block diagram of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. It is a block diagram of the conventional semiconductor integrated circuit.
  • FIG. 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the first embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.
  • the semiconductor integrated circuit according to the first embodiment of the present invention includes an internal step-down power supply block 101, an internal step-up power supply block 112, and a reference generation circuit 104.
  • the internal step-down power supply block 101 includes a 3.3V external power supply 102, an internal power supply 103 that requires 2.6V, a reference voltage 105 that is a 1.3V constant voltage generated from a constant voltage source or the like in the reference circuit 104, A first amplifier circuit 106 and a first amplifier circuit which output a detection signal L level when a reference voltage 105 and an internal power supply feedback voltage 111 described later are input and the internal power supply feedback voltage 111 becomes lower than the reference voltage 105.
  • a step-down PMOS (P-typePMetal Oxide Semiconductor) transistor 108 for generating the internal power supply 103 from the external power supply 102, and the voltage of the internal power supply 103.
  • the first resistance element 1 for outputting a half voltage of the internal power supply 103 to 9.
  • the second resistance element 110 having the same resistance value as that of the first resistance element 109, and an internal voltage output from the internal power supply 103 via the first resistance element 109 as a half voltage value of the internal power supply 103. It is composed of a power supply feedback voltage 111.
  • the internal boost power supply block 112 is automatically boosted when an external power supply 102 that requires 3.3V, an internal power supply 103 that requires 2.6V, a pump circuit 113 that boosts the external power supply 102, and the external power supply 102 are supplied.
  • An oscillator circuit 114 that generates a reference signal for operation and controls whether or not to output this reference signal according to the level of the input control signal, and a half of the external power supply 102 based on the external power supply 102
  • the third resistance element 115 for outputting the voltage of the second power source, the fourth resistance element 116 having the same resistance value as the third resistance element 115, and the half of the external power supply 102 via the third resistance element 115.
  • the external power supply feedback voltage 117, the reference voltage 105, and the external power supply feedback voltage 117 are input as the voltage value of the external power supply feedback voltage 1
  • the second amplifier circuit 118 that outputs the detection signal H level when 7 becomes lower than the reference voltage 105, the second detection signal 119 that is a detection signal generated by the second amplifier circuit 118, and the first detection signal
  • a first logic circuit 120 which is an inverter circuit for inverting the signal polarity of the signal 107; a third detection signal 121 obtained by inverting the signal polarity of the first detection signal 107 via the first logic circuit 120;
  • the second detection signal 119 and the third detection signal 121 are input and output from the second logic circuit 122 and the second logic circuit 122 for taking a NAND (NAND) and input to the oscillator circuit 114.
  • NAND NAND
  • the internal step-down power supply block 101 supplies current to the memory (not shown) as the internal power supply 103 by supplying current from the external power supply 102 to the internal power supply 103 via the step-down PMOS transistor 108.
  • the internal boost power supply block 112 when the external power supply 102 is supplied to the pump circuit 113 and the second logic signal 124 for operating the pump circuit 113 is input from the oscillator circuit 114, the external power supply 102 is boosted. Then, the internal power supply 103 is generated and supplied to a memory (not shown).
  • the oscillator circuit 114 outputs a reference signal that is automatically generated internally with the supply of the external power supply 102 as the second logic signal 124 when the input first logic signal 123 is at the L level.
  • the circuit configuration is such that nothing is output when the logic signal 123 is at the H level.
  • the external power source 102 has a normal voltage range (first voltage range) of about 3.3 V, and the external power source 102 has 3.3 V as an example.
  • first voltage range first voltage range
  • the power supply 103 is 2.6 V
  • the internal power supply 103 when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 ( ⁇ 1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111.
  • the reference voltage 105 which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two.
  • the gate input of the step-down PMOS transistor 108 becomes L level
  • the step-down PMOS transistor 108 is turned on to supply current from the external power supply 102 to the internal power supply 103
  • the internal power supply 103 has a desired voltage of 2 Raise to 6V.
  • the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and is thus set to 1.3 V.
  • the first detection signal 107 is switched from the L level to the H level.
  • the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.
  • the internal step-down power supply block 101 performs a step-down operation and supplies current from the external power supply 102 to the internal power supply 103. Operates to maintain 2.6V.
  • the internal boost power supply block 112 has an external voltage that is half the voltage of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 in order to monitor the voltage of the external power supply 102.
  • the power supply feedback voltage 117 is always generated.
  • an operation of the internal step-down power supply block 101 causes an L level signal from the first amplifier circuit 106, and the internal power supply 103 decreases 2.6V.
  • an H level signal is output as the first detection signal 107, respectively.
  • the first detection signal 107 is input to the gate of the step-down PMOS transistor 108 and simultaneously to the internal boost power supply block 112, more specifically, the first logic circuit 120 that is an inverter circuit.
  • the first detection signal 107 is inverted through the first logic circuit 120 to be the third detection signal 121.
  • the first detection signal 107 is H level
  • the internal power supply 103 is 2
  • it exceeds .6V it is inputted to the second logic circuit 122 which is a NAND circuit as an L level logic signal.
  • the second logic circuit 122 when the internal power supply 103 is lower than 2.6V, the second detection signal 119 at L level and the third detection signal 121 at H level are set to 2.
  • the voltage exceeds 6 V the L-level second detection signal 119 and the L-level third detection signal 121 are input, and the third detection signal 121 is either the H level or the L level.
  • the first logic signal 123 that is an H level logic signal is output.
  • the oscillator circuit 114 does not output a reference signal generated internally because the first logic signal 123 that is an input is at an H level, and nothing is input to the pump circuit 113 in the subsequent stage. Not implemented.
  • the internal boosting power supply block 112 does not perform the boosting operation regardless of the voltage level of the internal power supply 103 when the external power supply 102 holds a voltage of 3.3 V which is the normal voltage range.
  • the external power supply 102 when the external power supply 102 is in a low voltage range of about 2.5V (second voltage range lower than the first voltage range), for example, the external power supply 102 is 2.5V and the internal power supply 103 is 2.6V. Will be described as an example.
  • the internal power supply 103 when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 ( ⁇ 1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111.
  • the reference voltage 105 which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two.
  • the gate input of the step-down PMOS transistor 108 becomes L level, the step-down PMOS transistor 108 is turned on to supply current from the external power supply 102 to the internal power supply 103, and the internal power supply 103 has a desired voltage of 2 It operates to increase to .6V, but since the voltage 2.5V of the external power supply 102 is lower than the desired voltage 2.6V of the internal power supply 103, the internal power supply 103 is increased only to 2.5V at the maximum. I can't. Since the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103, the internal power supply feedback voltage 111 rises only to a maximum of 1.25V. In the first amplifier circuit 106, the internal power supply feedback voltage 111 is the reference voltage.
  • the internal step-down power supply block 101 continues to operate and continues to supply current from the external power supply 102 to the internal power supply 103.
  • the other internal booster power supply block 112 operates simultaneously (described later) and supplies current to the internal power supply 103 so that the internal power supply 103 can maintain 2.6 V.
  • the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and thus reaches 1.3V.
  • the internal power supply feedback voltage 111 is set to the reference voltage. Since the voltage is higher than the voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.
  • the internal boost power supply block 112 has an external voltage that is half the voltage of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 in order to monitor the voltage of the external power supply 102.
  • the power supply feedback voltage 117 is always generated.
  • the second amplifier circuit 118 outputs an H level signal as the second detection signal 119.
  • an operation of the internal step-down power supply block 101 causes an L level signal from the first amplifier circuit 106, and the internal power supply 103 decreases 2.6V.
  • an H level signal is output as the first detection signal 107, respectively.
  • the first detection signal 107 is input to the gate of the step-down PMOS transistor 108 and simultaneously to the internal boost power supply block 112, more specifically, the first logic circuit 120 that is an inverter circuit.
  • the first detection signal 107 is inverted through the first logic circuit 120 to be the third detection signal 121.
  • the first detection signal 107 is H level
  • the internal power supply 103 is 2
  • it exceeds .6V it is inputted to the second logic circuit 122 which is a NAND circuit as an L level logic signal.
  • the second logic circuit 122 when the internal power supply 103 is lower than 2.6V, the second detection signal 119 at H level and the third detection signal 121 at H level are set to 2.
  • an H level second detection signal 119 and an L level third detection signal 121 are input.
  • the second logic circuit 122 When the internal power supply 103 is less than 2.6 V, that is, in a state where current supply is necessary, the second logic circuit 122 is generated from the second detection signal 119 at H level and the third detection signal 121 at H level. Outputs an L level signal to the first logic signal 123, and the oscillator circuit 114 outputs an internally generated reference signal to the pump circuit 113 as the second logic signal 124. Since the second logic signal 124 is input, the pump circuit 113 performs a boost operation, boosts the external power supply 102, supplies current to the internal power supply 103, and operates until the internal power supply 103 reaches 2.6V. .
  • the third detection signal 121 is at the L level. Therefore, from the second detection signal 119 at the H level, the second logic circuit 122 outputs an H level signal to the first logic signal 123, and the oscillator circuit 114 outputs an internally generated reference signal. do not do.
  • the pump circuit 113 does not perform the boosting operation because the second logic signal 124 is not input.
  • the internal boost power supply block 112 is controlled to perform the boost operation according to the voltage level of the internal power supply 103, and the internal power supply 103 is set to a desired voltage.
  • the voltage boosting operation is not performed.
  • the internal power supply 103 is lower than 2.6V, the voltage boosting operation is performed until the voltage reaches 2.6V, and when the voltage reaches 2.6V, the voltage boosting operation is performed. Take action to stop.
  • the internal step-down power supply block 101 when the external power supply 102 is in the low voltage range and the voltage level of the internal power supply 103 decreases, current is supplied from the internal step-down power supply block 101 to increase the voltage of the internal power supply 103 to 2.6V.
  • the internal step-up power supply block 112 when sufficient current cannot be supplied only by the operation of the internal step-down power supply block 101 (the voltage cannot be increased to 2.6 V), the internal step-up power supply block 112 is also operated to connect the external power supply 102. Then, the boosting operation is performed to maintain the internal power supply 103 at 2.6V.
  • the internal step-down power supply block 101 can be stably supplied to the memory by performing the current supply by the operation of the internal boosting power supply block 112. From the viewpoint of circuit area and power efficiency, Compared to the case where a plurality of internal booster circuits are mounted as in the conventional example, a large area reduction and power reduction can be realized simultaneously.
  • the voltage fluctuation noise of the internal power supply 103 due to the boost pump operation becomes large, and the power supply supplied to the memory varies.
  • the voltage fluctuation noise of the internal power supply 103 due to the pumping operation in the internal boost power supply block 112 performs voltage feedback in the internal buck power supply block 101, and the current from the internal buck power supply block 101 is also current. It is suppressed by taking the structure which supplies.
  • the circuit area can be reduced as compared with the case where each circuit is configured individually. Can be greatly reduced.
  • an internal power supply feedback voltage 111 for detecting whether or not the internal power supply 103 is lowered, and an external power supply feedback voltage 117 for detecting whether or not the external power supply 102 is lowered are respectively connected to the first resistance elements.
  • the second resistance element 110, the third resistance element 115, and the fourth resistance element 116 are used to detect the voltage after being converted to a half voltage, so that the external power supply 102 is lower than the internal power supply 103.
  • the same level of voltage (about 1.3 V) as the internal power supply feedback voltage 111 can be supplied to the first amplifier circuit 106 and the second amplifier circuit 118, a stable detection operation can be realized.
  • the reference voltage 105 generated by the reference generation circuit 104 is 2.6 V
  • the internal power supply 103 is input to the first amplifier circuit 106 as it is without voltage conversion and is detected.
  • the external power supply 102 drops to 2.5V, that is, when the voltage falls below 2.6V, which is the desired voltage of the internal power supply 103
  • the reference generation circuit 104 has a reference voltage 105 up to 2.5V. Therefore, even if the internal step-down power supply block 101 and the internal step-up power supply block 112 operate, the problem that the internal power supply 103 can only be raised to 2.5V can be solved.
  • the external power supply feedback voltage 117 is also set to a half voltage of the external power supply 102 in accordance with the generation of the reference voltage 105 at a constant voltage of 1.3V.
  • the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103
  • the external power supply feedback voltage 117 is set to a half voltage of the external power supply 102
  • the reference voltage 105 is set to 1.3V.
  • the present invention is not limited to this, and the same effect can be obtained if the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are lower than the internal power supply 103. realizable.
  • the present invention is not limited to this, and is shown as an example. Even if a higher voltage is set using a voltage conversion circuit such as a resistance element or a booster circuit, the reference voltage 105 can be externally supplied as a higher voltage using a voltage conversion circuit such as a resistance element or a booster circuit. Even when the power supply 102 has a low voltage, a sufficient operation as a power supply circuit can be realized, so that the same effect can be realized.
  • both the internal step-down power supply block 101 and the internal step-up power supply block 112 are operated when the external power supply 102 is in a low voltage range.
  • the present invention is not limited to this.
  • the operation of the internal step-down power supply block 101 can be stopped and only the internal step-up power supply block 112 can be operated to supply the internal power supply 103.
  • a logic circuit in which the first detection signal 107 and the second detection signal 119 are input to the gate input of the step-down PMOS transistor 108 in the internal step-down power supply block 101 more specifically an OR circuit or the like.
  • the gate input of the step-down PMOS transistor 108 may be set to the H level.
  • the reference voltage 105 is set to a constant voltage of 1.3 V.
  • the present invention is not limited to this, and the same voltage may be set in the reference generation circuit 104.
  • the effect can be realized.
  • the internal power supply feedback voltage 111 By setting the internal power supply feedback voltage 111 to an arbitrary voltage, the voltage of the internal power supply 103 supplied to the memory can be freely set. Therefore, the memory requires the internal power supply 103 having a plurality of voltages. It is possible to cope with even cases.
  • the internal boost power supply block 112 is operated when the external power supply 102 falls below 2.6 V, which is the voltage of the internal power supply 103.
  • the present invention is not limited to this.
  • the voltage difference between the internal power supply 103 and the internal power supply 103 becomes small, even if the internal boost power supply block 112 is operated when the external power supply 102 drops to a voltage of about 2.7 V, for example, the same effect can be obtained. realizable.
  • the voltage difference between the external power supply 102 and the internal power supply 103 is reduced before power efficiency when current is supplied from the external power supply 102 to the internal power supply 103 via the step-down PMOS transistor 108 is reduced.
  • By operating the internal boost power supply block 112 at the same time it is possible to suppress a reduction in power efficiency when the internal power supply 103 is supplied.
  • FIG. 2 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the second embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.
  • the semiconductor integrated circuit according to the second embodiment of the present invention includes an internal step-down power supply block 200, an internal step-up power supply block 201, and a reference generation circuit 104.
  • the internal step-down power supply block 200 includes a 3.3V external power supply 102, an internal power supply 103 that requires 2.6V, a reference voltage 105 that is a 1.3V constant voltage generated from a constant voltage source or the like in the reference circuit 104, A first amplifier circuit 106 and a first amplifier circuit which output a detection signal L level when a reference voltage 105 and an internal power supply feedback voltage 111 described later are input and the internal power supply feedback voltage 111 becomes lower than the reference voltage 105.
  • the second resistance element 110 having the same resistance value as that of the first resistance element 109, and an internal voltage output from the internal power supply 103 via the first resistance element 109 as a half voltage value of the internal power supply 103.
  • First logic circuit 205, third detection signal 206 which is a signal obtained by inverting the signal logic of the second detection signal 119 by the first logic circuit 205, the source of the external power supply 102 and the step-down PMOS transistor 108 The connection between the nodes is controlled by the third detection signal 206, and the nodes at both ends are connected when the third detection signal 206 is at the H level.
  • the first detection switch 202 that is disconnected when it is at the L level, the connection between the internal boosting power supply 204 described later and the source node of the step-down PMOS transistor 108 are controlled by the second detection signal 119, and the second detection signal 119 is
  • the second switch 203 is configured to connect the nodes at both ends when the level is H and to disconnect when the level is the L level.
  • the internal boost power supply block 201 includes a 3.3 V external power supply 102, an internal boost power supply 204 generated by performing a boost operation, a pump circuit 113 for boosting the external power supply 102 to generate the internal boost power supply 204, and the external power supply 102. Is automatically generated, and an oscillator circuit 114 for controlling whether or not to output this reference signal according to the level of the input control signal is generated based on the external power supply 102.
  • the third resistance element 115 for outputting a half voltage of the external power supply 102, the fourth resistance element 116 having the same resistance value as the third resistance element 115, and the third resistance element 115.
  • the external power supply feedback voltage 117, the reference voltage 105, and the external power supply feedback voltage 117 are output as a half voltage value of the external power supply 102.
  • the second amplifier circuit 118 that outputs a detection signal H level when the external power supply feedback voltage 117 is lower than the reference voltage 105, and is a detection signal generated by the second amplifier circuit 118 and an internal step-down power supply block
  • the second detection signal 119 input also to the second detection signal 119, the second logic circuit 207 configured by an inverter circuit for inverting the signal logic of the second detection signal 119, and the second logic circuit 207 via the second logic circuit 207.
  • the 2 is a signal obtained by inverting the signal logic of the detection signal 119, the first logic signal 208 for controlling whether or not to output the reference signal generated by the oscillator circuit 114, and output from the oscillator circuit 114 to the pump circuit 113. It is composed of a second logic signal 124 that is an input oscillator signal for performing an internal boosting operation.
  • the external power supply 102 passes through the first switch 202, or the internal booster power supply 204, which will be described later, passes through the second switch 203, and then passes through the step-down PMOS transistor 108.
  • Current is supplied to the memory (not shown) as the internal power supply 103.
  • the connection between the first switch 202 and the second switch 203 is switched by a second detection signal 119 generated by an internal boosting power supply block 201 described later according to the voltage level of the external power supply 102.
  • the external power supply 102 is supplied to the pump circuit 113, and when the second logic signal 124 for operating the pump circuit 113 is input from the oscillator circuit 114, the external power supply 102 is boosted.
  • an internal boost power supply 204 is generated and supplied to the internal step-down power supply block 200.
  • the oscillator circuit 114 generates a reference signal that is automatically generated internally with the supply of the external power supply 102 when the first logic signal 208, which is an inverted signal of the second detection signal 119, is at the L level.
  • the circuit configuration is such that the signal 124 is output and nothing is output when the first logic signal 208 is at the H level.
  • the external power source 102 has a normal voltage range of about 3.3V (first voltage range).
  • the external power source 102 has 3.3V
  • a case where the power supply 103 is 2.6 V will be described as an example.
  • the internal power supply 103 when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 ( ⁇ 1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111.
  • the reference voltage 105 which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two.
  • the gate input of the step-down PMOS transistor 108 becomes L level, and the step-down PMOS transistor 108 is turned on.
  • the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are externally connected.
  • the external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118.
  • the first switch 202 is connected, the second switch 203 is turned off, and the step-down PMOS transistor 108 is turned on, so that the external power supply 102 is stepped down with the first switch 202 to the internal power supply 103.
  • a current is supplied through the PMOS transistor 108 to raise the internal power supply 103 to a desired voltage of 2.6V.
  • the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and is thus set to 1.3 V.
  • the first detection signal 107 is switched from the L level to the H level.
  • the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.
  • the internal step-down power supply block 200 performs the step-down operation when the internal power supply 103 falls below the desired voltage of 2.6 V, and supplies current from the external power supply 102 to the internal power supply 103. Operates to maintain 2.6V.
  • the internal boost power supply block 201 is half of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 as described above.
  • the external power supply feedback voltage 117 that is a voltage is constantly generated.
  • an H level signal is output to the first logic signal 208 that is the input of the oscillator circuit 114 via the second logic circuit 207. Since the first logic signal 208 that is an input is input at the H level, the oscillator circuit 114 does not output the internally generated reference signal and does not input anything to the pump circuit 113 in the subsequent stage, so that the voltage is boosted. The action is not performed.
  • the internal boost power supply block 201 does not perform the boost operation regardless of the voltage level of the internal power supply 103 when the external power supply 102 holds a voltage of 3.3 V that is the normal voltage range.
  • the internal boost power supply 204 is not supplied with current.
  • the external power supply 102 when the external power supply 102 is in a low voltage range of about 2.5V (second voltage range lower than the first voltage range), for example, the external power supply 102 is 2.5V and the internal power supply 103 is 2.6V. Will be described as an example.
  • the internal power supply 103 when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 ( ⁇ 1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111.
  • the reference voltage 105 which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two.
  • the gate input of the step-down PMOS transistor 108 becomes L level, and the step-down PMOS transistor 108 is turned on.
  • the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are externally connected.
  • the external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118.
  • the second amplifier circuit 118 outputs an H level signal as the second detection signal 119.
  • the third detection signal 206 that is an inverted signal of the second detection signal 119 is an L level signal. The L level is applied to the first switch 202, and the first switch 202 is opened.
  • the second detection signal 119 is applied as the H level to the second switch 203, the second switch 203 is connected, and the internal boosting power source 204 and the step-down PMOS transistor 108 are connected. It becomes the state. That is, since the internal boost power supply 204 boosted by the internal boost power supply block 201 described later is supplied to the internal step-down power supply block 200, the internal boost power supply 204 internally passes through the second switch 203 and the step-down PMOS transistor 108. A current is supplied to the power supply 103 to raise the internal power supply 103 to a desired voltage of 2.6V.
  • the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and thus reaches 1.3 V.
  • the first detection signal 107 is switched from the L level to the H level.
  • the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off, and the current supply from the internal boost power supply 204 to the internal power supply 103 is stopped.
  • the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are external voltages that are half the voltage of the external power supply 102.
  • the second amplifier circuit 118 outputs an H level signal as the second detection signal 119.
  • an L level signal is output to the first logic signal 208 that is the input of the oscillator circuit 114 via the second logic circuit 207. Since the first logic signal 208 as an input is input at the L level, the oscillator circuit 114 outputs the internally generated reference signal to the pump circuit 113 as the second logic signal 124.
  • the pump circuit 113 In response to this, a boosting operation is performed.
  • the internal boost power supply 204 boosted by the pump circuit 113 is supplied to the internal step-down power supply block 200, and becomes the current source for supplying current to the internal power supply 103 by the operation of the internal step-down power supply block 200 described above.
  • the operation at 200 supplies current until the internal power supply 103 reaches a desired voltage of 2.6V.
  • the external power supply 102 again exceeds the desired voltage of 2.6 V, which is the internal power supply 103
  • the external power supply feedback voltage 117 exceeds 1.3 V, so that the second output that is the output of the second amplifier circuit 118 is output.
  • the detection signal 119 is switched from the H level to the L level
  • the first logic signal 208 that is an input signal to the oscillator circuit 114 is switched from the L level to the H level via the second logic circuit 207 that is an inverter circuit.
  • the oscillator circuit 114 stops outputting the internally generated reference signal to the pump circuit 113, and the pump circuit 113 stops the boosting operation.
  • the internal boost power supply block 201 is controlled to perform the boost operation according to the voltage level of the external power supply 102, and the external power supply 102 is connected to the internal power supply 103.
  • the boost operation is not performed.
  • the voltage boost operation is performed.
  • the voltage boost operation is stopped. Take action to do.
  • the internal step-down power supply block 200 cannot supply sufficient current from the external power supply 102 to the internal power supply 103.
  • a current is supplied to the internal step-down power supply block 200 instead of the external power supply 102 using the internal step-up power supply 204 boosted in the step-up power supply block 201 as a power source, and the internal boost power supply 204 passes through the second switch 203 and the step-down PMOS transistor 108.
  • the current is supplied to the internal power supply 103 to maintain the internal power supply 103 at a desired voltage of 2.6V.
  • the internal step-down power supply block 200 By switching the power supply for supplying current to the internal power supply 103 from the external power supply 102 to the internal boost power supply 204 and supplying the current to the internal power supply 103, it becomes possible to supply a stable internal power supply 103 to the memory. Also from the viewpoint of power efficiency, a large area reduction and power reduction can be realized at the same time as in the case where a plurality of internal booster circuits are mounted as in the conventional example.
  • the circuit area can be reduced compared to the case where each circuit is individually configured. Can be greatly reduced.
  • an internal power supply feedback voltage 111 for detecting whether or not the internal power supply 103 is lowered, and an external power supply feedback voltage 117 for detecting whether or not the external power supply 102 is lowered are respectively connected to the first resistance elements.
  • the second resistance element 110, the third resistance element 115, and the fourth resistance element 116 are used to detect the voltage after being converted to a half voltage, so that the external power supply 102 is lower than the internal power supply 103.
  • the same level of voltage (about 1.3 V) as the internal power supply feedback voltage 111 can be supplied to the first amplifier circuit 106 and the second amplifier circuit 118, a stable detection operation can be realized.
  • the reference voltage 105 generated by the reference generation circuit 104 is 2.6 V
  • the internal power supply 103 is input to the first amplifier circuit 106 as it is without voltage conversion and is detected.
  • the external power supply 102 drops to 2.5V, that is, when the voltage falls below 2.6V, which is the desired voltage of the internal power supply 103
  • the reference generation circuit 104 has a reference voltage 105 up to 2.5V. Therefore, even if the internal step-down power supply block 200 and the internal step-up power supply block 201 are operated, the problem that the internal power supply 103 can only be raised to 2.5V can be solved.
  • the external power supply feedback voltage 117 is also set to a half voltage of the external power supply 102 in accordance with the generation of the reference voltage 105 at a constant voltage of 1.3V.
  • the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103
  • the external power supply feedback voltage 117 is set to a half voltage of the external power supply 102
  • the reference voltage 105 is set to 1.3V.
  • the present invention is not limited to this, and the same effect can be obtained if the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are lower than the internal power supply 103. realizable.
  • the present invention is not limited to this, and is shown as an example. Even if a higher voltage is set using a voltage conversion circuit such as a resistance element or a booster circuit, the reference voltage 105 can be externally supplied as a higher voltage using a voltage conversion circuit such as a resistance element or a booster circuit. Even when the power supply 102 has a low voltage, a sufficient operation as a power supply circuit can be realized, so that the same effect can be realized.
  • the reference voltage 105 is set to a constant voltage of 1.3 V.
  • the present invention is not limited to this, and the same voltage may be set in the reference generation circuit 104.
  • the effect can be realized.
  • the internal power supply feedback voltage 111 By setting the internal power supply feedback voltage 111 to an arbitrary voltage, the voltage of the internal power supply 103 supplied to the memory can be freely set. Therefore, the memory requires the internal power supply 103 having a plurality of voltages. It is possible to cope with even cases.
  • the internal booster power supply block 201 is operated when the external power supply 102 falls below 2.6 V, which is the voltage of the internal power supply 103.
  • the present invention is not limited to this.
  • the voltage difference between the internal power supply 103 and the internal power supply 103 becomes small, even if the internal boost power supply block 201 is operated when the external power supply 102 drops to a voltage of about 2.7 V, for example, the same effect can be obtained. realizable.
  • the voltage difference between the external power supply 102 and the internal power supply 103 is reduced, a current is supplied from the external power supply 102 to the internal power supply 103 via the first switch 202 and the step-down PMOS transistor 108.
  • FIG. 3 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the third embodiment of the present invention.
  • FIG. 3 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the third embodiment of the present invention.
  • the internal boost power supply block 300 includes a circuit in which a filter composed of a fifth resistance element 301 and a capacitive element 302 is added on the output path of the pump circuit 113.
  • the operation of the internal step-down power supply block 101 is the same as that of the first embodiment of the present invention.
  • the pump by adding the fifth resistance element 301 and the capacitive element 302 to the output part of the internal power supply 103 in the internal boost power supply block 300, the pump The voltage fluctuation noise of the internal power supply 103 caused by the boosting operation in the circuit 113 is suppressed via the fifth resistance element 301 and the capacitive element 302, and the voltage fluctuation noise to the internal power supply 103 supplied to the memory is filtered. It becomes possible to supply as a more stable power supply.
  • a configuration in which a resistance element and a capacitance element are added to the internal power supply 103 is shown as an example.
  • the present invention is not limited to this, and other means for suppressing voltage fluctuation, a clamp circuit, and protection The same effect can be realized by using a circuit or the like having a similar function for suppressing voltage fluctuation noise and current backflow.
  • FIG. 4 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the fourth embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.
  • a step-down NMOS (N-type Metal Oxide Semiconductor) transistor 401 is used instead of the step-down PMOS transistor 108.
  • a third logic circuit 402 which is an inverter circuit for inverting the signal logic of the first detection signal 107, and a fourth detection signal 403 output from the third logic circuit 402. .
  • the operation of the internal boost power supply block 112 is the same as that of the first embodiment of the present invention.
  • the first amplifier circuit 106 An L level first detection signal 107 is output.
  • the first detection signal 107 becomes an inverted H level signal via the third logic circuit 402 that is an inverter circuit, and is input to the gate of the step-down NMOS transistor 401 as the fourth detection signal 403. .
  • the step-down NMOS transistor 401 is turned on when an H level is applied to the gate, supplies current from the external power supply 102 to the internal power supply 103, and operates to maintain the internal power supply 103 at 2.6V.
  • the internal power supply 103 can be stably supplied, and the internal power supply 103 can be supplied. Even if the voltage exceeds the voltage of the external power supply 102, the back-down current can be prevented because the step-down transistor is composed of the NMOS transistor 401.
  • the internal power supply 103 generated by the step-up / step-down operation is made more stable without changing the circuit area simply by changing the step-down transistor configuration with respect to the configuration of the first embodiment of the present invention. It is possible to prevent reverse current flow by supplying.
  • the semiconductor integrated circuit according to the present invention is effective in stabilizing the generation of internal power, improving the operating voltage range, and reducing the circuit area with respect to lowering the SoC power supply specifications and lowering the external power supply voltage due to power supply voltage fluctuations.
  • it is useful as a semiconductor integrated circuit having an internal power supply circuit.
  • Second resistance element 101 Internal power supply block 102 External power supply 103 Internal power supply 104 Reference generation circuit 105 Reference voltage 106 First amplifier circuit 107 First detection signal 108 Step-down PMOS transistor 109 First resistance element 110 Second resistance element 111 Internal power supply Feedback voltage 112 Internal boost power supply block 113 Pump circuit 114 Oscillator circuit 115 Third resistance element 116 Fourth resistance element 117 External power supply feedback voltage 118 Second amplifier circuit 119 Second detection signal 120 First logic circuit 121 3 detection signal 122 second logic circuit 123 first logic signal 124 second logic signal 200 internal step-down power supply block 201 internal boost power supply block 202 first switch 203 second switch 204 internal boost power supply 205 first Logic circuit 206 Third detection signal 207 Second logic circuit 208 First logic signal 300 Internal boost power supply block 301 Fifth resistance element 302 Capacitance element 400 Internal step-down power supply block 401 Step-down NMOS transistor 402 Third logic circuit 403 Fourth detection signal

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  • Semiconductor Integrated Circuits (AREA)
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Abstract

Disclosed is memory having an internal power supply circuit mounted therein wherein at the time of supplying power to the memory by generating an internal power supply on the basis of an external power supply, power is stably supplied from the internal power supply, while reducing the circuit area and suppressing an increase of power consumption. In the memory, when the external power supply (102) is within a first voltage range, the internal power supply (103) is generated using only an internal step-down power supply block (101), and when the external power supply (102) is within a second voltage range, which is lower than the first voltage range, the internal power supply (103) is generated using an internal step-up power supply block (112) in addition to the internal step-down power supply block (101).

Description

半導体集積回路Semiconductor integrated circuit
　本発明は、半導体集積回路に関し、特にメモリを備えた半導体集積回路に関するものである。 The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a memory.
　近年の半導体製造技術の進展に伴い素子がますます微細化され、ダイナミック・ランダム・アクセス・メモリ（以下、ＤＲＡＭと称す）やスタティック・ランダム・アクセス・メモリ（以下、ＳＲＡＭと称す）に代表されるメモリの集積度が向上している。また、半導体製造技術の微細化に伴い、１個の半導体チップ、例えばシステム・オン・チップ（以下、ＳｏＣと称す）に供給する電源電圧の低電圧化も進み、より低い電源電圧で動作するＳｏＣが求められている。 As semiconductor manufacturing technology has advanced in recent years, devices have become increasingly finer and are typified by dynamic random access memory (hereinafter referred to as DRAM) and static random access memory (hereinafter referred to as SRAM). Memory integration has been improved. In addition, with the miniaturization of semiconductor manufacturing technology, the power supply voltage supplied to one semiconductor chip, for example, a system-on-chip (hereinafter referred to as SoC) has been lowered, and the SoC that operates at a lower power supply voltage. Is required.
　メモリを搭載するＳｏＣとしては、外部電源をもとに、外部電源電圧よりも低電圧、あるいは高電圧である内部電源電圧を、メモリ内部に搭載した内部電源回路、より詳細には内部降圧電源ブロックや内部昇圧電源ブロックで生成してメモリに供給することが広く知られている。これは、外部電源電圧の低電圧化に伴いメモリ内部で必要とする高電圧を外部から直接供給することが困難になっていることや、ＳｏＣ内外での電源電圧の変動に対する耐性の向上等を目的としている。 As an SoC equipped with a memory, an internal power supply circuit in which an internal power supply voltage that is lower or higher than the external power supply voltage based on an external power supply is installed in the memory, more specifically, an internal step-down power supply block It is widely known that the voltage is generated by an internal boost power supply block and supplied to a memory. This is because it is difficult to directly supply the high voltage required inside the memory from the outside as the external power supply voltage is lowered, and the resistance to fluctuations in the power supply voltage inside and outside the SoC is improved. It is aimed.
　メモリ内部に内部電源回路を搭載した公知例として、例えば特許文献１によれば、複数の内部昇圧電源ブロックを搭載した半導体集積回路があり、外部電源電圧の高低に応じて複数の内部昇圧電源ブロックを選択的に動作させることにより、外部電源電圧が低下しても安定した内部電源電圧の供給を実現する例が開示されている。 As a publicly known example in which an internal power supply circuit is mounted in a memory, for example, according to Patent Document 1, there is a semiconductor integrated circuit in which a plurality of internal boost power supply blocks are mounted, and a plurality of internal boost power supply blocks according to the level of an external power supply voltage. An example is disclosed that realizes stable supply of the internal power supply voltage even when the external power supply voltage is lowered by selectively operating.
　図５は、従来の内部電源回路を備えた半導体集積回路の概略構成を示す回路図である。以下、図５を参照しながらメモリ内部電源回路の構成と動作を説明する。 FIG. 5 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit having a conventional internal power supply circuit. The configuration and operation of the memory internal power supply circuit will be described below with reference to FIG.
　図５において、従来の内部電源回路は、外部電源５０１と、内部電源５０２と、内部降圧電源５０３と、第１の内部昇圧電源ブロック５０４と、第２の内部昇圧電源ブロック５０５と、内部降圧電源ブロック５０６と、制御信号生成回路５０７と、第１の内部昇圧電源制御回路５０８と、第２の内部昇圧電源制御回路５０９とから構成されている。 5, the conventional internal power supply circuit includes an external power supply 501, an internal power supply 502, an internal step-down power supply 503, a first internal boost power supply block 504, a second internal boost power supply block 505, and an internal step-down power supply. The block 506 includes a control signal generation circuit 507, a first internal boost power supply control circuit 508, and a second internal boost power supply control circuit 509.
　第１の内部昇圧電源ブロック５０４は、外部電源５０１をもとに昇圧動作を実施して内部電源５０２を出力する。第２の内部昇圧電源ブロック５０５は、内部降圧電源５０３をもとに昇圧動作を実施して内部電源５０２を出力する。 The first internal boosting power supply block 504 performs a boosting operation based on the external power supply 501 and outputs the internal power supply 502. The second internal boost power supply block 505 performs a boost operation based on the internal step-down power supply 503 and outputs the internal power supply 502.
　制御信号生成回路５０７からは、外部電源５０１が３．３Ｖ程度の通常電圧範囲である場合にはＬレベル、外部電源５０１が例えば２．３Ｖ程度の低電圧範囲である場合にはＨレベルの第１の論理信号５１０が出力されて第１の内部昇圧電源制御回路５０８と第２の内部昇圧電源制御回路５０９とに入力されている。第１の内部昇圧電源制御回路５０８は、２入力のＮＯＲ回路で構成されており、一方の入力には第１の論理信号５１０が、もう一方の入力にはグランドがそれぞれ入力されている。第２の内部昇圧電源制御回路５０９は、２入力のＮＡＮＤ回路とインバータ回路とから構成されており、ＮＡＮＤ回路の２入力のうち一方の入力には第１の論理信号５１０が、もう一方の入力には外部電源５０１がそれぞれ入力されている。第１の内部昇圧電源制御回路５０８から第１の内部昇圧電源ブロック５０４へは第２の論理信号５１１が、第２の内部昇圧電源制御回路５０９から第２の内部昇圧電源ブロック５０５へは第３の論理信号５１２がそれぞれ入力されている。第１の内部昇圧電源ブロック５０４、第２の内部昇圧電源ブロック５０５はともに、入力である第２の論理信号５１１、第３の論理信号５１２がＨレベルのときに昇圧動作を実施する構成としている。 From the control signal generation circuit 507, when the external power source 501 is in the normal voltage range of about 3.3V, the control signal generation circuit 507 is at the L level. 1 logic signal 510 is output and input to the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509. The first internal boost power supply control circuit 508 is composed of a two-input NOR circuit, and the first logic signal 510 is input to one input, and the ground is input to the other input. The second internal boost power supply control circuit 509 includes a two-input NAND circuit and an inverter circuit. The first logic signal 510 is input to one of the two inputs of the NAND circuit, and the other input. The external power source 501 is input to each. The second logic signal 511 is sent from the first internal boost power supply control circuit 508 to the first internal boost power supply block 504, and the third logic signal is sent from the second internal boost power supply control circuit 509 to the second internal boost power supply block 505. The logic signals 512 are respectively input. Both the first internal boost power supply block 504 and the second internal boost power supply block 505 are configured to perform a boost operation when the second logic signal 511 and the third logic signal 512 that are inputs are at the H level. .
　外部電源５０１は、例えば３．３Ｖの電圧であり、メモリ（図示していない）に供給される内部電源５０２はメモリ内のロウデコーダ（図示していない）やワードドライバ（図示していない）に供給される例えば３．６Ｖの電圧であり、内部降圧電源５０３は例えば２．３Ｖの電圧である。 The external power supply 501 is, for example, a voltage of 3.3 V, and the internal power supply 502 supplied to the memory (not shown) is supplied to a row decoder (not shown) or a word driver (not shown) in the memory. The supplied voltage is, for example, 3.6 V, and the internal step-down power supply 503 is, for example, 2.3 V.
　まず、外部電源５０１が通常電圧範囲、例えば３．３Ｖの電圧を保持している場合には、制御信号生成回路５０７から第１の論理信号５１０にＬレベルの信号を出力する。第１の論理信号５１０がＬレベルとなったことを受けて、第１の内部昇圧電源制御回路５０８及び第２の内部昇圧電源制御回路５０９はそれぞれ第２の論理信号５１１にＨレベルの信号を、第３の論理信号５１２にＬレベルの信号を出力する。これを受けて、第１の内部昇圧電源ブロック５０４は外部電源５０１をもとに昇圧動作を開始して内部電源５０２を出力する。一方、第２の内部昇圧電源ブロック５０５は、前段からの入力信号である第３の論理信号５１２がＬレベルであるため、内部降圧電源５０３をもとにした昇圧動作を実施しない。 First, when the external power supply 501 holds a normal voltage range, for example, a voltage of 3.3 V, the control signal generation circuit 507 outputs an L level signal to the first logic signal 510. In response to the first logic signal 510 becoming L level, the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509 respectively send an H level signal to the second logic signal 511. Then, an L level signal is output as the third logic signal 512. In response to this, the first internal boost power supply block 504 starts the boost operation based on the external power supply 501 and outputs the internal power supply 502. On the other hand, the second internal boost power supply block 505 does not perform the boost operation based on the internal step-down power supply 503 because the third logic signal 512 that is the input signal from the previous stage is at the L level.
　このように外部電源５０１が通常電圧範囲である場合には、第１の内部昇圧電源ブロック５０４で昇圧動作を実施して内部電源５０２をメモリに供給し、第２の内部昇圧電源ブロック５０５では昇圧動作、及び内部電源５０２への電流供給は実施しない。 As described above, when the external power supply 501 is in the normal voltage range, the first internal boost power supply block 504 performs a boost operation to supply the internal power supply 502 to the memory, and the second internal boost power supply block 505 boosts the voltage. Operation and current supply to the internal power supply 502 are not performed.
　一方、外部電源５０１が低電圧範囲、例えば２．３Ｖ程度の電圧である場合には、制御信号生成回路５０７から第１の論理信号５１０にＨレベルの信号を出力する。第１の論理信号５１０がＨレベルとなったことを受けて、第１の内部昇圧電源制御回路５０８及び第２の内部昇圧電源制御回路５０９はそれぞれ第２の論理信号５１１にＬレベルの信号を、第３の論理信号５１２にＨレベルの信号を出力する。これを受けて、第２の内部昇圧電源ブロック５０５は内部降圧電源５０３をもとに昇圧動作を開始して内部電源５０２を出力する。一方、第１の内部昇圧電源ブロック５０４は、前段からの入力信号である第２の論理信号５１１がＬレベルであるため昇圧動作を実施しない。 On the other hand, when the external power source 501 is in a low voltage range, for example, a voltage of about 2.3 V, an H level signal is output from the control signal generation circuit 507 to the first logic signal 510. In response to the first logic signal 510 becoming H level, the first internal boost power supply control circuit 508 and the second internal boost power supply control circuit 509 respectively send an L level signal to the second logic signal 511. Then, an H level signal is output to the third logic signal 512. In response to this, the second internal boost power supply block 505 starts the boost operation based on the internal step-down power supply 503 and outputs the internal power supply 502. On the other hand, the first internal boost power supply block 504 does not perform the boost operation because the second logic signal 511 that is the input signal from the previous stage is at the L level.
　このように外部電源５０１が低電圧範囲である場合には、第２の内部昇圧電源ブロック５０５で昇圧動作を実施して内部電源５０２をメモリに供給し、第１の内部昇圧電源ブロック５０４では昇圧動作、及び内部電源５０２への電流供給は実施しない。 As described above, when the external power source 501 is in the low voltage range, the second internal boost power source block 505 performs a boost operation to supply the internal power source 502 to the memory, and the first internal boost power source block 504 boosts the voltage. Operation and current supply to the internal power supply 502 are not performed.
特開２０００－０５７７６５号公報JP 2000-057765 A
　近年のＳｏＣ全体の外部電源の低電圧化と電源変動とに伴う課題としてはまず、外部電源のメモリへの直接供給が低電圧化やピン数削減等のために困難になってきている点が挙げられ、また外部電源の低電圧化によって、外部電源とメモリに供給するべき内部電源との電圧が逆転（内部電源の方が高くなる）してしまう場合には、内部降圧電源ブロックを用いて外部電源を降圧して内部電源を生成することが不可能になるという背景がある。また、外部電源が内部電源の電圧よりも高い電圧であっても、両者の間の電圧差が小さくなってきているために内部降圧電源ブロックを用いても十分な電流供給が行えずに、電力効率が悪い、あるいは内部電源生成が不十分になってしまい、結果として安定した内部電源を供給できないことになるという状況も起こりうる。これに加えて、外部電源に何らかの要因（一例としてはＳｏＣ内部での電源配線インピーダンスに起因する電圧降下や、ＳｏＣ内部回路での瞬間的な過渡電流の発生による電圧降下等）による電源変動が生じた場合には、その影響はより一層顕著になってくる。そのため、内部降圧電源ブロックの代わりに内部昇圧電源ブロックを用いて外部電源よりも高い電圧である内部電源を生成するという方式が一般的であるが、回路の特性上、内部昇圧電源ブロックは内部降圧電源ブロックに比べて電力効率が下がる、また必要とする回路素子数や回路面積が大きくなるという課題がある。 As a problem associated with the recent decrease in the voltage of the external power supply and the fluctuation of the power supply of the entire SoC, first of all, direct supply to the memory of the external power supply has become difficult due to a reduction in voltage and a reduction in the number of pins. If the voltage between the external power supply and the internal power supply to be supplied to the memory is reversed (the internal power supply becomes higher) due to the low voltage of the external power supply, use the internal step-down power supply block. There is a background that it is impossible to generate an internal power supply by stepping down the external power supply. Even if the external power supply is higher than the voltage of the internal power supply, the voltage difference between the two is getting smaller, so even if the internal step-down power supply block is used, sufficient current cannot be supplied. There may be situations where efficiency is poor or internal power generation is insufficient, resulting in failure to supply stable internal power. In addition to this, the power supply fluctuates due to some factor in the external power supply (for example, a voltage drop due to the power supply wiring impedance inside the SoC, a voltage drop due to instantaneous transient current generation in the SoC internal circuit, etc.) If this happens, the effect becomes even more pronounced. For this reason, it is common to use an internal boost power supply block instead of the internal step-down power supply block to generate an internal power supply that is higher in voltage than the external power supply. There are problems in that the power efficiency is lower than that of the power supply block, and the number of circuit elements and the circuit area required are increased.
　また、前述の従来例や特許文献１によれば、外部電源が十分な電圧を保持している通常状態では、搭載している複数の内部昇圧電源ブロックのうちの一部を動作させて外部電源を内部で昇圧してメモリに内部電源として供給し、外部電源が所定の電圧以下まで低くなってしまった場合には、内部に搭載している内部降圧電源ブロックに外部電源を入力して一旦内部降圧電源を生成し、搭載している複数の内部昇圧電源ブロックのうち、前述の内部昇圧電源ブロックとは異なる他の内部昇圧電源ブロックにこの内部降圧電源を供給して昇圧動作を実施してメモリに内部電源を供給する構成が開示されている。この構成では、外部電源の電圧が低下した場合でもメモリに安定した内部電源を供給することは可能となるが、その一方で昇圧動作を実施する元の電源の電圧レベルに応じた内部昇圧電源ブロックを複数種類搭載する必要があり、また外部電源が所定の電圧以下まで低くなって内部降圧電源ブロックを使用する場合には、外部電源を一旦降圧してから再度昇圧するという２段階の内部電源生成動作が必要となる。 Further, according to the above-described conventional example and Patent Document 1, in a normal state where the external power supply holds a sufficient voltage, a part of the plurality of internal boost power supply blocks mounted is operated to operate the external power supply. Is boosted internally and supplied to the memory as an internal power supply. If the external power supply drops below a specified voltage, the external power supply is input to the internal step-down power supply block and the internal power supply is temporarily A step-down power supply is generated, and the internal step-down power supply block is supplied to another internal step-up power supply block that is different from the above-described internal step-up power supply block among the plurality of internal step-up power supply blocks that are mounted. A configuration for supplying an internal power source is disclosed. In this configuration, it is possible to supply a stable internal power supply to the memory even when the voltage of the external power supply drops, but on the other hand, the internal boost power supply block according to the voltage level of the original power supply that performs the boost operation If the external power supply is lowered to a predetermined voltage or lower and the internal step-down power supply block is used, the internal power generation is performed in two stages by stepping down the external power supply and then boosting it again Action is required.
　内部昇圧電源ブロックは、オシレータ回路やポンプ回路を搭載することが一般的であるため、前述のように、内部降圧電源ブロックと比較すると単体でも非常に大きな回路面積を必要とし、従来例の構成等では更にこの内部昇圧電源ブロックを複数種類搭載しているため、必要となる回路面積も大幅に増加してしまい、ＳｏＣ全体としてのチップ面積増加に大きな影響を与えてしまうという課題があった。また、外部電源を一旦降圧してから再度昇圧動作を実施するという２段階の内部電源生成動作を実施する場合には、内部降圧電源ブロックのみで内部電源を生成した場合と比べて消費する電力が大幅に増加してしまい、結果としてＳｏＣ全体での消費電力が増加することによって、外部電源電圧を下げてもＳｏＣとして所望の電力削減効果が得られない等の懸念が容易に想定しうる。このことから、内部電源回路を有する半導体集積回路として、外部電源電圧が低電圧化した場合でも、面積増加や消費電力の増大を抑制しつつ安定した内部電源をメモリに供給することが非常に困難であった。 Since the internal boost power supply block is generally equipped with an oscillator circuit or a pump circuit, as described above, it requires a very large circuit area as compared with the internal step-down power supply block. However, since a plurality of types of internal boosting power supply blocks are mounted, the required circuit area is greatly increased, which greatly affects the increase in the chip area of the SoC as a whole. In addition, when performing a two-stage internal power generation operation in which the external power supply is stepped down and then boosted again, the power consumed is smaller than when the internal power supply is generated only with the internal step-down power supply block. As the power consumption of the entire SoC increases as a result, the concern that the desired power reduction effect cannot be obtained as the SoC even if the external power supply voltage is lowered can be easily assumed. Therefore, as a semiconductor integrated circuit having an internal power supply circuit, even when the external power supply voltage is lowered, it is very difficult to supply a stable internal power supply to the memory while suppressing an increase in area and power consumption. Met.
　本発明は、このような課題に鑑みてなされたものであり、外部電源をもとに内部電源回路で内部電源を生成してメモリに内部電源を供給する際に、チップ面積を削減し、消費電力の増大を抑制しつつ安定した内部電源をメモリに供給することを目的とするものである。 The present invention has been made in view of such problems, and reduces the chip area and consumes power when generating internal power by an internal power supply circuit based on the external power and supplying the internal power to the memory. An object of the present invention is to supply a stable internal power supply to a memory while suppressing an increase in power.
　上記課題を解決するために、本発明の第１の半導体集積回路は、外部電源をもとに降圧動作を実施する内部降圧電源ブロックと、前記外部電源をもとに昇圧動作を実施する内部昇圧電源ブロックとを備え、前記外部電源が第１の電圧範囲では、前記内部降圧電源ブロックのみを使用して所望の電圧の内部電源を生成し、前記外部電源が前記第１の電圧範囲より低い第２の電圧範囲では、前記内部降圧電源ブロックに加えて又は前記内部降圧電源ブロックに代えて前記内部昇圧電源ブロックを使用して前記所望の電圧の内部電源を生成することを特徴とする。 In order to solve the above problem, a first semiconductor integrated circuit according to the present invention includes an internal step-down power supply block that performs a step-down operation based on an external power supply, and an internal step-up operation that performs a step-up operation based on the external power supply. A power supply block, wherein when the external power supply is in a first voltage range, an internal power supply having a desired voltage is generated using only the internal step-down power supply block, and the external power supply is lower than the first voltage range. In the voltage range of 2, the internal power supply of the desired voltage is generated using the internal boost power supply block in addition to or instead of the internal buck power supply block.
　また、本発明の第２の半導体集積回路は、選択された電源をもとに降圧動作を実施する内部降圧電源ブロックと、外部電源をもとに内部昇圧電源を生成する内部昇圧電源ブロックとを備え、前記外部電源が第１の電圧範囲では、前記内部降圧電源ブロックが前記外部電源から所望の電圧の内部電源を生成し、前記外部電源が前記第１の電圧範囲より低い第２の電圧範囲では、前記内部昇圧電源ブロックが生成した前記内部昇圧電源から前記内部降圧電源ブロックが前記所望の電圧の内部電源を生成することを特徴とする。 The second semiconductor integrated circuit of the present invention includes an internal step-down power supply block that performs a step-down operation based on a selected power supply, and an internal step-up power supply block that generates an internal boost power supply based on an external power supply. When the external power supply is in the first voltage range, the internal step-down power supply block generates an internal power supply having a desired voltage from the external power supply, and the external power supply is lower than the first voltage range. Then, the internal step-down power supply block generates the internal power supply of the desired voltage from the internal boost power supply generated by the internal boost power supply block.
　本発明は、外部電源をもとに内部に搭載する内部電源回路を使用して内部電源を生成する半導体集積回路に関して有効な技術であり、チップ面積を削減し、消費電力の増大を抑制しつつ安定した内部電源を生成することを可能にする。更には、使用する回路を複数の内部電源ブロックで共用することにより更なるチップ面積の削減を実現するものである。 The present invention is an effective technique for a semiconductor integrated circuit that generates an internal power supply using an internal power supply circuit mounted inside based on an external power supply, while reducing the chip area and suppressing an increase in power consumption. It makes it possible to generate a stable internal power supply. Furthermore, the chip area can be further reduced by sharing a circuit to be used by a plurality of internal power supply blocks.
本発明の第１の実施形態に係る半導体集積回路のブロック図である。1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. 本発明の第２の実施形態に係る半導体集積回路のブロック図である。FIG. 5 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. 本発明の第３の実施形態に係る半導体集積回路のブロック図である。FIG. 6 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. 本発明の第４の実施形態に係る半導体集積回路のブロック図である。It is a block diagram of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. 従来の半導体集積回路のブロック図である。It is a block diagram of the conventional semiconductor integrated circuit.
　以下、本発明の実施の形態について、図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　《第１の実施形態》
　図１は、本発明の第１の実施形態による内部電源回路を備えた半導体集積回路の概略構成を示す図である。以下、内部電源回路を備えた半導体集積回路の代表的な内部電源生成の動作における本発明の実施の形態を説明する。 << First Embodiment >>
FIG. 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the first embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.
　本発明の第１の実施形態での半導体集積回路は、内部降圧電源ブロック１０１と、内部昇圧電源ブロック１１２と、リファレンス生成回路１０４とから構成される。 The semiconductor integrated circuit according to the first embodiment of the present invention includes an internal step-down power supply block 101, an internal step-up power supply block 112, and a reference generation circuit 104.
　内部降圧電源ブロック１０１は、３．３Ｖの外部電源１０２、２．６Ｖが必要となる内部電源１０３、リファレンス回路１０４において定電圧源等から生成される１．３Ｖの定電圧であるリファレンス電圧１０５、リファレンス電圧１０５と後述の内部電源フィードバック電圧１１１とが入力され、内部電源フィードバック電圧１１１がリファレンス電圧１０５より低くなった場合に検知信号Ｌレベルを出力する第１のアンプ回路１０６、第１のアンプ回路１０６で生成される検知信号である第１の検知信号１０７、外部電源１０２から内部電源１０３を生成するための降圧用ＰＭＯＳ（P-type Metal Oxide Semiconductor）トランジスタ１０８、内部電源１０３の電圧をもとに内部電源１０３の２分の１の電圧を出力するための第１の抵抗素子１０９、第１の抵抗素子１０９と同じ抵抗値を持つ第２の抵抗素子１１０、内部電源１０３から第１の抵抗素子１０９を介して内部電源１０３の２分の１の電圧値として出力される内部電源フィードバック電圧１１１から構成されている。 The internal step-down power supply block 101 includes a 3.3V external power supply 102, an internal power supply 103 that requires 2.6V, a reference voltage 105 that is a 1.3V constant voltage generated from a constant voltage source or the like in the reference circuit 104, A first amplifier circuit 106 and a first amplifier circuit which output a detection signal L level when a reference voltage 105 and an internal power supply feedback voltage 111 described later are input and the internal power supply feedback voltage 111 becomes lower than the reference voltage 105. Based on the first detection signal 107 which is a detection signal generated at 106, a step-down PMOS (P-typePMetal Oxide Semiconductor) transistor 108 for generating the internal power supply 103 from the external power supply 102, and the voltage of the internal power supply 103. The first resistance element 1 for outputting a half voltage of the internal power supply 103 to 9. The second resistance element 110 having the same resistance value as that of the first resistance element 109, and an internal voltage output from the internal power supply 103 via the first resistance element 109 as a half voltage value of the internal power supply 103. It is composed of a power supply feedback voltage 111.
　内部昇圧電源ブロック１１２は、３．３Ｖの外部電源１０２、２．６Ｖが必要となる内部電源１０３、外部電源１０２を昇圧するためのポンプ回路１１３、外部電源１０２が供給されると自動的に昇圧動作のための基準信号を生成し、入力される制御信号のレベルに応じてこの基準信号を出力するかどうかを制御するオシレータ回路１１４、外部電源１０２をもとに外部電源１０２の２分の１の電圧を出力するための第３の抵抗素子１１５、第３の抵抗素子１１５と同じ抵抗値を持つ第４の抵抗素子１１６、第３の抵抗素子１１５を介して外部電源１０２の２分の１の電圧値として出力される外部電源フィードバック電圧１１７、リファレンス電圧１０５と外部電源フィードバック電圧１１７とが入力され、外部電源フィードバック電圧１１７がリファレンス電圧１０５より低くなった場合に検知信号Ｈレベルを出力する第２のアンプ回路１１８、第２のアンプ回路１１８で生成される検知信号である第２の検知信号１１９、第１の検知信号１０７の信号極性を反転するためのインバータ回路である第１の論理回路１２０、第１の検知信号１０７の信号極性を第１の論理回路１２０を介して反転させた第３の検知信号１２１、第２の検知信号１１９と第３の検知信号１２１とを入力して否定論理積（ＮＡＮＤ）をとるための第２の論理回路１２２、第２の論理回路１２２から出力されてオシレータ回路１１４に入力され、オシレータ回路１１４で生成される基準信号を出力するかどうかを制御するための第１の論理信号１２３、オシレータ回路１１４から出力されてポンプ回路１１３に入力される、内部昇圧動作を実施するためのオシレータ信号である第２の論理信号１２４から構成されている。 The internal boost power supply block 112 is automatically boosted when an external power supply 102 that requires 3.3V, an internal power supply 103 that requires 2.6V, a pump circuit 113 that boosts the external power supply 102, and the external power supply 102 are supplied. An oscillator circuit 114 that generates a reference signal for operation and controls whether or not to output this reference signal according to the level of the input control signal, and a half of the external power supply 102 based on the external power supply 102 The third resistance element 115 for outputting the voltage of the second power source, the fourth resistance element 116 having the same resistance value as the third resistance element 115, and the half of the external power supply 102 via the third resistance element 115. The external power supply feedback voltage 117, the reference voltage 105, and the external power supply feedback voltage 117 are input as the voltage value of the external power supply feedback voltage 1 The second amplifier circuit 118 that outputs the detection signal H level when 7 becomes lower than the reference voltage 105, the second detection signal 119 that is a detection signal generated by the second amplifier circuit 118, and the first detection signal A first logic circuit 120 which is an inverter circuit for inverting the signal polarity of the signal 107; a third detection signal 121 obtained by inverting the signal polarity of the first detection signal 107 via the first logic circuit 120; The second detection signal 119 and the third detection signal 121 are input and output from the second logic circuit 122 and the second logic circuit 122 for taking a NAND (NAND) and input to the oscillator circuit 114. The first logic signal 123 for controlling whether or not to output the reference signal generated by the oscillator circuit 114 is output from the oscillator circuit 114 and the pump circuit 1 3 is input to, and a second logic signal 124 is oscillator signal for carrying out an internal step-up operation.
　内部降圧電源ブロック１０１では、外部電源１０２から、降圧用ＰＭＯＳトランジスタ１０８を介して内部電源１０３に電流を供給することにより、内部電源１０３としてメモリ（図示していない）に電流を供給する。 The internal step-down power supply block 101 supplies current to the memory (not shown) as the internal power supply 103 by supplying current from the external power supply 102 to the internal power supply 103 via the step-down PMOS transistor 108.
　一方、内部昇圧電源ブロック１１２では、外部電源１０２をポンプ回路１１３に供給し、オシレータ回路１１４からポンプ回路１１３を動作させるための第２の論理信号１２４が入力された場合に、外部電源１０２を昇圧して内部電源１０３を生成してメモリ（図示していない）に供給する。オシレータ回路１１４は、外部電源１０２の供給とともに内部で自動で生成している基準信号を、入力である第１の論理信号１２３がＬレベルのときに第２の論理信号１２４として出力し、第１の論理信号１２３がＨレベルのときには何も出力しない回路構成をとっている。 On the other hand, in the internal boost power supply block 112, when the external power supply 102 is supplied to the pump circuit 113 and the second logic signal 124 for operating the pump circuit 113 is input from the oscillator circuit 114, the external power supply 102 is boosted. Then, the internal power supply 103 is generated and supplied to a memory (not shown). The oscillator circuit 114 outputs a reference signal that is automatically generated internally with the supply of the external power supply 102 as the second logic signal 124 when the input first logic signal 123 is at the L level. The circuit configuration is such that nothing is output when the logic signal 123 is at the H level.
　以上のように構成された本発明の第１の実施形態に関して、最初に外部電源１０２が３．３Ｖ程度の通常電圧範囲（第１の電圧範囲）、一例として外部電源１０２が３．３Ｖ、内部電源１０３が２．６Ｖの場合を例として説明する。 Regarding the first embodiment of the present invention configured as described above, first, the external power source 102 has a normal voltage range (first voltage range) of about 3.3 V, and the external power source 102 has 3.3 V as an example. A case where the power supply 103 is 2.6 V will be described as an example.
　まず、内部降圧電源ブロック１０１では、内部電源１０３が所望の電圧である２．６Ｖを下回った場合、第１の抵抗素子１０９と第２の抵抗素子１１０とを介して内部電源１０３の２分の１の電圧（＜１．３Ｖ）が内部電源フィードバック電圧１１１として第１のアンプ回路１０６に入力される。一方、リファレンス生成回路１０４で生成された定電圧１．３Ｖであるリファレンス電圧１０５も第１のアンプ回路１０６に入力され、両者の間で電圧比較が行われる。この場合には、内部電源フィードバック電圧１１１（＜１．３Ｖ）の方がリファレンス電圧１０５（＝１．３Ｖ）よりも低いため、第１のアンプ回路１０６は検知信号として第１の検知信号１０７にＬレベルの信号を出力する。これを受けて、降圧用ＰＭＯＳトランジスタ１０８のゲート入力がＬレベルとなり、降圧用ＰＭＯＳトランジスタ１０８はオンして外部電源１０２から内部電源１０３へ電流を供給し、内部電源１０３を所望の電圧である２．６Ｖまで上昇させる。内部電源１０３に十分な電流が供給され、所望の電圧である２．６Ｖまで達すると、内部電源フィードバック電圧１１１は内部電源１０３の２分の１の電圧と設定しているために１．３Ｖに達し、第１のアンプ回路１０６では、内部電源フィードバック電圧１１１がリファレンス電圧１０５よりも高くなるため、第１の検知信号１０７はＬレベルからＨレベルへと切り替わる。これを受けて、降圧用ＰＭＯＳトランジスタ１０８のゲート入力がＬレベルからＨレベルへと切り替わるために降圧用ＰＭＯＳトランジスタ１０８はオフし、外部電源１０２から内部電源１０３への電流供給は止まる。 First, in the internal step-down power supply block 101, when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 (<1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111. On the other hand, the reference voltage 105, which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two. In this case, since the internal power supply feedback voltage 111 (<1.3 V) is lower than the reference voltage 105 (= 1.3 V), the first amplifier circuit 106 outputs the first detection signal 107 as a detection signal. An L level signal is output. In response to this, the gate input of the step-down PMOS transistor 108 becomes L level, the step-down PMOS transistor 108 is turned on to supply current from the external power supply 102 to the internal power supply 103, and the internal power supply 103 has a desired voltage of 2 Raise to 6V. When a sufficient current is supplied to the internal power supply 103 and reaches the desired voltage of 2.6 V, the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and is thus set to 1.3 V. In the first amplifier circuit 106, since the internal power supply feedback voltage 111 becomes higher than the reference voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.
　このようにして、内部降圧電源ブロック１０１は、内部電源１０３が所望の電圧である２．６Ｖを下回ると降圧動作を実施して外部電源１０２から内部電源１０３へ電流を供給して内部電源１０３が２．６Ｖを維持するよう動作する。 In this way, when the internal power supply 103 falls below the desired voltage of 2.6 V, the internal step-down power supply block 101 performs a step-down operation and supplies current from the external power supply 102 to the internal power supply 103. Operates to maintain 2.6V.
　一方、このとき、内部昇圧電源ブロック１１２は、外部電源１０２の電圧をモニターするために第３の抵抗素子１１５と第４の抵抗素子１１６とによって外部電源１０２の２分の１の電圧である外部電源フィードバック電圧１１７を常時生成している。外部電源フィードバック電圧１１７と、前述のリファレンス生成回路１０４で生成した定電圧１．３Ｖであるリファレンス電圧１０５とを、第２のアンプ回路１１８に入力する。外部電源１０２は通常電圧範囲であり３．３Ｖの電圧を保持しているため、外部電源フィードバック電圧１１７（＝１．６５Ｖ）はリファレンス電圧１０５（＝１．３Ｖ）を上回っており、両者を比較して第２のアンプ回路１１８はＬレベルの信号を第２の検知信号１１９として出力する。次に、内部電源１０３が２．６Ｖを下回っている場合には前述の内部降圧電源ブロック１０１での動作によって第１のアンプ回路１０６からはＬレベルの信号が、内部電源１０３が２．６Ｖを上回っている場合にはＨレベルの信号がそれぞれ第１の検知信号１０７として出力される。この第１の検知信号１０７は、降圧用ＰＭＯＳトランジスタ１０８のゲートに入力されると同時に内部昇圧電源ブロック１１２、より詳細にはインバータ回路である第１の論理回路１２０にも入力される。この第１の論理回路１２０を介して第１の検知信号１０７は反転して第３の検知信号１２１として、内部電源１０３が２．６Ｖを下回っている場合にはＨレベル、内部電源１０３が２．６Ｖを上回っている場合にはＬレベルの論理信号としてＮＡＮＤ回路である第２の論理回路１２２に入力される。第２の論理回路１２２では、内部電源１０３が２．６Ｖを下回っている場合にはＬレベルの第２の検知信号１１９とＨレベルの第３の検知信号１２１とが、内部電源１０３が２．６Ｖを上回っている場合にはＬレベルの第２の検知信号１１９とＬレベルの第３の検知信号１２１とがそれぞれ入力され、第３の検知信号１２１がＨレベル、Ｌレベルのいずれであっても、第２の検知信号１１９がＬレベルであるためにＨレベルの論理信号である第１の論理信号１２３を出力する。オシレータ回路１１４は、入力である第１の論理信号１２３がＨレベルであるために内部で生成している基準信号を出力せず、後段のポンプ回路１１３へは何も入力されないために昇圧動作は実施されない。 On the other hand, at this time, the internal boost power supply block 112 has an external voltage that is half the voltage of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 in order to monitor the voltage of the external power supply 102. The power supply feedback voltage 117 is always generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is in the normal voltage range and holds a voltage of 3.3 V, the external power supply feedback voltage 117 (= 1.65 V) exceeds the reference voltage 105 (= 1.3 V). Then, the second amplifier circuit 118 outputs an L level signal as the second detection signal 119. Next, when the internal power supply 103 is lower than 2.6V, an operation of the internal step-down power supply block 101 causes an L level signal from the first amplifier circuit 106, and the internal power supply 103 decreases 2.6V. In the case where it exceeds the upper limit, an H level signal is output as the first detection signal 107, respectively. The first detection signal 107 is input to the gate of the step-down PMOS transistor 108 and simultaneously to the internal boost power supply block 112, more specifically, the first logic circuit 120 that is an inverter circuit. The first detection signal 107 is inverted through the first logic circuit 120 to be the third detection signal 121. When the internal power supply 103 is lower than 2.6V, the first detection signal 107 is H level, and the internal power supply 103 is 2 When it exceeds .6V, it is inputted to the second logic circuit 122 which is a NAND circuit as an L level logic signal. In the second logic circuit 122, when the internal power supply 103 is lower than 2.6V, the second detection signal 119 at L level and the third detection signal 121 at H level are set to 2. When the voltage exceeds 6 V, the L-level second detection signal 119 and the L-level third detection signal 121 are input, and the third detection signal 121 is either the H level or the L level. Also, since the second detection signal 119 is at the L level, the first logic signal 123 that is an H level logic signal is output. The oscillator circuit 114 does not output a reference signal generated internally because the first logic signal 123 that is an input is at an H level, and nothing is input to the pump circuit 113 in the subsequent stage. Not implemented.
　このため、内部昇圧電源ブロック１１２は、外部電源１０２が通常電圧範囲である３．３Ｖの電圧を保持している場合には、内部電源１０３の電圧レベルによらずに昇圧動作を実施しない。 For this reason, the internal boosting power supply block 112 does not perform the boosting operation regardless of the voltage level of the internal power supply 103 when the external power supply 102 holds a voltage of 3.3 V which is the normal voltage range.
　よって、外部電源１０２が通常電圧範囲である場合に、内部電源１０３の電圧レベルが低下したときには内部降圧電源ブロック１０１からのみ電流供給を実施して内部電源１０３の電圧を２．６Ｖに維持するように動作する。 Therefore, when the external power supply 102 is in the normal voltage range, when the voltage level of the internal power supply 103 decreases, current is supplied only from the internal step-down power supply block 101 so that the voltage of the internal power supply 103 is maintained at 2.6V. To work.
　次に、外部電源１０２が２．５Ｖ程度の低電圧範囲（前記第１の電圧範囲より低い第２の電圧範囲）、一例として外部電源１０２が２．５Ｖ、内部電源１０３が２．６Ｖの場合を例として説明する。 Next, when the external power supply 102 is in a low voltage range of about 2.5V (second voltage range lower than the first voltage range), for example, the external power supply 102 is 2.5V and the internal power supply 103 is 2.6V. Will be described as an example.
　まず、内部降圧電源ブロック１０１では、内部電源１０３が所望の電圧である２．６Ｖを下回った場合、第１の抵抗素子１０９と第２の抵抗素子１１０とを介して内部電源１０３の２分の１の電圧（＜１．３Ｖ）が内部電源フィードバック電圧１１１として第１のアンプ回路１０６に入力される。一方、リファレンス生成回路１０４で生成された定電圧１．３Ｖであるリファレンス電圧１０５も第１のアンプ回路１０６に入力され、両者の間で電圧比較が行われる。この場合には、内部電源フィードバック電圧１１１（＜１．３Ｖ）の方がリファレンス電圧１０５（＝１．３Ｖ）よりも低いため、第１のアンプ回路１０６は検知信号として第１の検知信号１０７にＬレベルの信号を出力する。これを受けて、降圧用ＰＭＯＳトランジスタ１０８のゲート入力がＬレベルとなり、降圧用ＰＭＯＳトランジスタ１０８はオンして外部電源１０２から内部電源１０３へ電流を供給し、内部電源１０３を所望の電圧である２．６Ｖまで上昇させるよう動作するが、外部電源１０２の電圧２．５Ｖが内部電源１０３の所望の電圧である２．６Ｖよりも低いため、最大でも２．５Ｖまでしか内部電源１０３を上昇させることができない。内部電源フィードバック電圧１１１は内部電源１０３の２分の１の電圧と設定しているために最大でも１．２５Ｖまでしか上昇せず、第１のアンプ回路１０６では、内部電源フィードバック電圧１１１がリファレンス電圧１０５よりも高くなることはなく、常にリファレンス電圧１０５の方が高くなるために第１のアンプ回路１０６の出力である第１の検知信号１０７はＬレベルのままとなり、降圧用ＰＭＯＳトランジスタ１０８のゲート入力もＬレベルのままであるために内部降圧電源ブロック１０１は動作し続け、外部電源１０２から内部電源１０３へ電流を供給し続けることになる。ここで、他方の内部昇圧電源ブロック１１２も同時に動作（後述）して内部電源１０３に電流を供給することによって内部電源１０３が２．６Ｖを維持できるように動作するため、内部電源１０３が２．６Ｖに達した時点で内部電源フィードバック電圧１１１は内部電源１０３の２分の１の電圧と設定しているために１．３Ｖに達し、第１のアンプ回路１０６では、内部電源フィードバック電圧１１１がリファレンス電圧１０５よりも高くなるため、第１の検知信号１０７はＬレベルからＨレベルへと切り替わる。これを受けて、降圧用ＰＭＯＳトランジスタ１０８のゲート入力がＬレベルからＨレベルへと切り替わるために降圧用ＰＭＯＳトランジスタ１０８はオフし、外部電源１０２から内部電源１０３への電流供給は止まる。 First, in the internal step-down power supply block 101, when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 (<1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111. On the other hand, the reference voltage 105, which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two. In this case, since the internal power supply feedback voltage 111 (<1.3 V) is lower than the reference voltage 105 (= 1.3 V), the first amplifier circuit 106 outputs the first detection signal 107 as a detection signal. An L level signal is output. In response to this, the gate input of the step-down PMOS transistor 108 becomes L level, the step-down PMOS transistor 108 is turned on to supply current from the external power supply 102 to the internal power supply 103, and the internal power supply 103 has a desired voltage of 2 It operates to increase to .6V, but since the voltage 2.5V of the external power supply 102 is lower than the desired voltage 2.6V of the internal power supply 103, the internal power supply 103 is increased only to 2.5V at the maximum. I can't. Since the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103, the internal power supply feedback voltage 111 rises only to a maximum of 1.25V. In the first amplifier circuit 106, the internal power supply feedback voltage 111 is the reference voltage. 105, and the reference voltage 105 is always higher, so the first detection signal 107, which is the output of the first amplifier circuit 106, remains at the L level, and the gate of the step-down PMOS transistor 108 Since the input also remains at the L level, the internal step-down power supply block 101 continues to operate and continues to supply current from the external power supply 102 to the internal power supply 103. Here, the other internal booster power supply block 112 operates simultaneously (described later) and supplies current to the internal power supply 103 so that the internal power supply 103 can maintain 2.6 V. When the voltage reaches 6V, the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and thus reaches 1.3V. In the first amplifier circuit 106, the internal power supply feedback voltage 111 is set to the reference voltage. Since the voltage is higher than the voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.
　一方、このとき、内部昇圧電源ブロック１１２は、外部電源１０２の電圧をモニターするために第３の抵抗素子１１５と第４の抵抗素子１１６とによって外部電源１０２の２分の１の電圧である外部電源フィードバック電圧１１７を常時生成している。外部電源フィードバック電圧１１７と、前述のリファレンス生成回路１０４で生成した定電圧１．３Ｖであるリファレンス電圧１０５とを、第２のアンプ回路１１８に入力する。外部電源１０２は低電圧範囲であり２．５Ｖの電圧であるため、外部電源フィードバック電圧１１７（＝１．２５Ｖ）はリファレンス電圧１０５（＝１．３Ｖ）を下回っており、両者を比較して第２のアンプ回路１１８はＨレベルの信号を第２の検知信号１１９として出力する。次に、内部電源１０３が２．６Ｖを下回っている場合には前述の内部降圧電源ブロック１０１での動作によって第１のアンプ回路１０６からはＬレベルの信号が、内部電源１０３が２．６Ｖを上回っている場合にはＨレベルの信号がそれぞれ第１の検知信号１０７として出力される。この第１の検知信号１０７は、降圧用ＰＭＯＳトランジスタ１０８のゲートに入力されると同時に内部昇圧電源ブロック１１２、より詳細にはインバータ回路である第１の論理回路１２０にも入力される。この第１の論理回路１２０を介して第１の検知信号１０７は反転して第３の検知信号１２１として、内部電源１０３が２．６Ｖを下回っている場合にはＨレベル、内部電源１０３が２．６Ｖを上回っている場合にはＬレベルの論理信号としてＮＡＮＤ回路である第２の論理回路１２２に入力される。第２の論理回路１２２では、内部電源１０３が２．６Ｖを下回っている場合にはＨレベルの第２の検知信号１１９とＨレベルの第３の検知信号１２１とが、内部電源１０３が２．６Ｖを上回っている場合にはＨレベルの第２の検知信号１１９とＬレベルの第３の検知信号１２１とがそれぞれ入力される。内部電源１０３が２．６Ｖを下回っている場合、つまり電流供給が必要な状態では、Ｈレベルの第２の検知信号１１９とＨレベルの第３の検知信号１２１とから、第２の論理回路１２２はＬレベルの信号を第１の論理信号１２３に出力し、オシレータ回路１１４は内部で生成している基準信号を第２の論理信号１２４としてポンプ回路１１３に出力する。ポンプ回路１１３は第２の論理信号１２４が入力されているため昇圧動作を実施し、外部電源１０２を昇圧して電流を内部電源１０３に供給し、内部電源１０３が２．６Ｖに達するまで動作する。そして、内部電源１０３が２．６Ｖに達した後、あるいは内部電源１０３が元々２．６Ｖを上回っている場合、つまり電流供給が不要である状態では、第３の検知信号１２１はＬレベルであるため、Ｈレベルの第２の検知信号１１９とから、第２の論理回路１２２はＨレベルの信号を第１の論理信号１２３に出力し、オシレータ回路１１４は内部で生成している基準信号を出力しない。ポンプ回路１１３は第２の論理信号１２４が入力されないため昇圧動作を実施しない。 On the other hand, at this time, the internal boost power supply block 112 has an external voltage that is half the voltage of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 in order to monitor the voltage of the external power supply 102. The power supply feedback voltage 117 is always generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is in a low voltage range and a voltage of 2.5 V, the external power supply feedback voltage 117 (= 1.25 V) is lower than the reference voltage 105 (= 1.3 V). The second amplifier circuit 118 outputs an H level signal as the second detection signal 119. Next, when the internal power supply 103 is lower than 2.6V, an operation of the internal step-down power supply block 101 causes an L level signal from the first amplifier circuit 106, and the internal power supply 103 decreases 2.6V. In the case where it exceeds the upper limit, an H level signal is output as the first detection signal 107, respectively. The first detection signal 107 is input to the gate of the step-down PMOS transistor 108 and simultaneously to the internal boost power supply block 112, more specifically, the first logic circuit 120 that is an inverter circuit. The first detection signal 107 is inverted through the first logic circuit 120 to be the third detection signal 121. When the internal power supply 103 is lower than 2.6V, the first detection signal 107 is H level, and the internal power supply 103 is 2 When it exceeds .6V, it is inputted to the second logic circuit 122 which is a NAND circuit as an L level logic signal. In the second logic circuit 122, when the internal power supply 103 is lower than 2.6V, the second detection signal 119 at H level and the third detection signal 121 at H level are set to 2. When the voltage exceeds 6 V, an H level second detection signal 119 and an L level third detection signal 121 are input. When the internal power supply 103 is less than 2.6 V, that is, in a state where current supply is necessary, the second logic circuit 122 is generated from the second detection signal 119 at H level and the third detection signal 121 at H level. Outputs an L level signal to the first logic signal 123, and the oscillator circuit 114 outputs an internally generated reference signal to the pump circuit 113 as the second logic signal 124. Since the second logic signal 124 is input, the pump circuit 113 performs a boost operation, boosts the external power supply 102, supplies current to the internal power supply 103, and operates until the internal power supply 103 reaches 2.6V. . Then, after the internal power supply 103 reaches 2.6V or when the internal power supply 103 originally exceeds 2.6V, that is, in a state where no current supply is required, the third detection signal 121 is at the L level. Therefore, from the second detection signal 119 at the H level, the second logic circuit 122 outputs an H level signal to the first logic signal 123, and the oscillator circuit 114 outputs an internally generated reference signal. do not do. The pump circuit 113 does not perform the boosting operation because the second logic signal 124 is not input.
　このように内部昇圧電源ブロック１１２は、外部電源１０２が低電圧範囲である場合には、内部電源１０３の電圧レベルに応じて昇圧動作を実施するどうかを制御され、内部電源１０３が所望の電圧である２．６Ｖを満たしているときには昇圧動作は実施せず、内部電源１０３が２．６Ｖを下回っているときには２．６Ｖに達するまで昇圧動作を実施し、２．６Ｖに達した時点で昇圧動作を停止する動作をとる。 As described above, when the external power supply 102 is in the low voltage range, the internal boost power supply block 112 is controlled to perform the boost operation according to the voltage level of the internal power supply 103, and the internal power supply 103 is set to a desired voltage. When the voltage of 2.6V is satisfied, the voltage boosting operation is not performed. When the internal power supply 103 is lower than 2.6V, the voltage boosting operation is performed until the voltage reaches 2.6V, and when the voltage reaches 2.6V, the voltage boosting operation is performed. Take action to stop.
　よって、外部電源１０２が低電圧範囲である場合に、内部電源１０３の電圧レベルが低下したときには、内部降圧電源ブロック１０１から電流供給を実施して内部電源１０３の電圧を２．６Ｖに上昇させるために動作するが、内部降圧電源ブロック１０１の動作だけでは十分な電流供給ができない（２．６Ｖまで電圧を上げることができない）場合には、内部昇圧電源ブロック１１２も動作して外部電源１０２をもとに昇圧動作を実施して内部電源１０３を２．６Ｖに維持する動作をとる。 Therefore, when the external power supply 102 is in the low voltage range and the voltage level of the internal power supply 103 decreases, current is supplied from the internal step-down power supply block 101 to increase the voltage of the internal power supply 103 to 2.6V. However, when sufficient current cannot be supplied only by the operation of the internal step-down power supply block 101 (the voltage cannot be increased to 2.6 V), the internal step-up power supply block 112 is also operated to connect the external power supply 102. Then, the boosting operation is performed to maintain the internal power supply 103 at 2.6V.
　以上のような構成によれば、外部電源１０２の電圧がメモリに供給する内部電源１０３の電圧を下回った場合、つまり外部電源１０２の電圧が低電圧となった場合でも、内部降圧電源ブロック１０１での電流供給に加えて内部昇圧電源ブロック１１２の動作による電流供給を実施することにより、安定して内部電源１０３をメモリに供給することが可能となり、回路面積や電力効率の観点から見ても、従来例のように複数の内部昇圧回路を搭載する場合に対して大幅な面積削減、電力削減を同時に実現できる。 According to the configuration as described above, even when the voltage of the external power supply 102 falls below the voltage of the internal power supply 103 supplied to the memory, that is, even when the voltage of the external power supply 102 becomes low, the internal step-down power supply block 101 In addition to the current supply, the internal power supply 103 can be stably supplied to the memory by performing the current supply by the operation of the internal boosting power supply block 112. From the viewpoint of circuit area and power efficiency, Compared to the case where a plurality of internal booster circuits are mounted as in the conventional example, a large area reduction and power reduction can be realized simultaneously.
　また、一般的には内部昇圧電源ブロック１１２のような昇圧電源回路では、昇圧ポンプ動作による内部電源１０３の電圧変動ノイズが大きくなり、メモリに供給する電源に変動が起こることが課題となるが、以上のような構成によれば、内部昇圧電源ブロック１１２でのポンプ動作による内部電源１０３の電圧変動ノイズは、内部降圧電源ブロック１０１内で電圧のフィードバックを実施し、内部降圧電源ブロック１０１からも電流を供給する構成をとることによって抑制される。 In general, in a boost power supply circuit such as the internal boost power supply block 112, the voltage fluctuation noise of the internal power supply 103 due to the boost pump operation becomes large, and the power supply supplied to the memory varies. According to the configuration as described above, the voltage fluctuation noise of the internal power supply 103 due to the pumping operation in the internal boost power supply block 112 performs voltage feedback in the internal buck power supply block 101, and the current from the internal buck power supply block 101 is also current. It is suppressed by taking the structure which supplies.
　また、リファレンス生成回路１０４やリファレンス電圧１０５及び第１の検知信号１０７を内部降圧電源ブロック１０１と内部昇圧電源ブロック１１２とで共用することにより、個別にそれぞれの回路を構成する場合に対して回路面積を大幅に削減することが可能となる。 Further, by sharing the reference generation circuit 104, the reference voltage 105, and the first detection signal 107 between the internal step-down power supply block 101 and the internal step-up power supply block 112, the circuit area can be reduced as compared with the case where each circuit is configured individually. Can be greatly reduced.
　また、内部電源１０３が低下しているかどうかを検知するための内部電源フィードバック電圧１１１、及び外部電源１０２が低下しているかどうかを検知するための外部電源フィードバック電圧１１７を、それぞれ第１の抵抗素子１０９、第２の抵抗素子１１０、第３の抵抗素子１１５、第４の抵抗素子１１６を用いて２分の１の電圧に変換して検知に用いることにより、外部電源１０２が内部電源１０３を下回った場合でも、第１のアンプ回路１０６及び第２のアンプ回路１１８に内部電源フィードバック電圧１１１と同じレベルの電圧（１．３Ｖ程度）を供給できるため、安定した検知動作を実現できる。これは、例えばリファレンス生成回路１０４で生成するリファレンス電圧１０５を２．６Ｖとし、内部電源１０３を電圧変換せずにそのまま両者を第１のアンプ回路１０６に入力して検知する回路構成をとった場合には、外部電源１０２が２．５Ｖに低下したとき、つまり内部電源１０３の所望の電圧である２．６Ｖを下回ってしまったとき等では、リファレンス生成回路１０４が２．５Ｖまでのリファレンス電圧１０５しか生成できなくなってしまい、これにより内部降圧電源ブロック１０１及び内部昇圧電源ブロック１１２が動作しても、内部電源１０３を２．５Ｖまでしか上げられなくなってしまうという課題を解決できる構成である。外部電源フィードバック電圧１１７も、リファレンス電圧１０５を１．３Ｖの定電圧で生成していることに合わせて、外部電源１０２の２分の１の電圧に設定している。 In addition, an internal power supply feedback voltage 111 for detecting whether or not the internal power supply 103 is lowered, and an external power supply feedback voltage 117 for detecting whether or not the external power supply 102 is lowered are respectively connected to the first resistance elements. 109, the second resistance element 110, the third resistance element 115, and the fourth resistance element 116 are used to detect the voltage after being converted to a half voltage, so that the external power supply 102 is lower than the internal power supply 103. Even in this case, since the same level of voltage (about 1.3 V) as the internal power supply feedback voltage 111 can be supplied to the first amplifier circuit 106 and the second amplifier circuit 118, a stable detection operation can be realized. In this case, for example, the reference voltage 105 generated by the reference generation circuit 104 is 2.6 V, and the internal power supply 103 is input to the first amplifier circuit 106 as it is without voltage conversion and is detected. When the external power supply 102 drops to 2.5V, that is, when the voltage falls below 2.6V, which is the desired voltage of the internal power supply 103, the reference generation circuit 104 has a reference voltage 105 up to 2.5V. Therefore, even if the internal step-down power supply block 101 and the internal step-up power supply block 112 operate, the problem that the internal power supply 103 can only be raised to 2.5V can be solved. The external power supply feedback voltage 117 is also set to a half voltage of the external power supply 102 in accordance with the generation of the reference voltage 105 at a constant voltage of 1.3V.
　なお、本実施形態では、内部電源フィードバック電圧１１１を内部電源１０３の２分の１の電圧に、外部電源フィードバック電圧１１７を外部電源１０２の２分の１の電圧に、リファレンス電圧１０５を１．３Ｖの定電圧にそれぞれ設定した一例を示したが、これに限定するものではなく、内部電源フィードバック電圧１１１、外部電源フィードバック電圧１１７、リファレンス電圧１０５が内部電源１０３より低い電圧であれば同等の効果を実現できる。 In this embodiment, the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103, the external power supply feedback voltage 117 is set to a half voltage of the external power supply 102, and the reference voltage 105 is set to 1.3V. However, the present invention is not limited to this, and the same effect can be obtained if the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are lower than the internal power supply 103. realizable.
　また、本実施形態では、内部電源フィードバック電圧１１１、外部電源フィードバック電圧１１７、リファレンス電圧１０５を内部電源１０３より低い電圧に設定した一例を示したが、これに限定するものではなく、一例として示した抵抗素子や昇圧回路等の電圧変換回路を用いてより高い電圧に設定しても、同様にリファレンス電圧１０５も抵抗素子等の電圧変換回路や昇圧回路等を用いて高い電圧として供給すれば、外部電源１０２が低電圧となった場合にも電源回路として十分な動作を実現することができるため、同等の効果を実現できる。 In this embodiment, an example in which the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are set to voltages lower than the internal power supply 103 is shown. However, the present invention is not limited to this, and is shown as an example. Even if a higher voltage is set using a voltage conversion circuit such as a resistance element or a booster circuit, the reference voltage 105 can be externally supplied as a higher voltage using a voltage conversion circuit such as a resistance element or a booster circuit. Even when the power supply 102 has a low voltage, a sufficient operation as a power supply circuit can be realized, so that the same effect can be realized.
　また、本実施形態では、内部電源フィードバック電圧１１１、外部電源フィードバック電圧１１７を生成するのに抵抗素子を用いる一例を示したが、これに限定するものではなく、電圧を変換する別の手段を用いても同等の効果を実現できる。 In the present embodiment, an example in which a resistance element is used to generate the internal power supply feedback voltage 111 and the external power supply feedback voltage 117 has been described. However, the present invention is not limited to this, and another means for converting the voltage is used. However, the same effect can be realized.
　また、本実施形態では、外部電源１０２が低電圧範囲では内部降圧電源ブロック１０１と内部昇圧電源ブロック１１２とを両方動作させる一例を示したが、これに限定するものではなく、外部電源１０２が低電圧範囲では内部降圧電源ブロック１０１の動作を停止して内部昇圧電源ブロック１１２のみを動作させて内部電源１０３を供給することも可能である。この場合には内部降圧電源ブロック１０１内の降圧用ＰＭＯＳトランジスタ１０８のゲート入力に、第１の検知信号１０７と第２の検知信号１１９とを入力とする論理回路、より具体的にはＯＲ回路等を追加して、外部電源１０２が低電圧範囲、つまり第２の検知信号１１９がＨレベルのときには降圧用ＰＭＯＳトランジスタ１０８のゲート入力をＨレベルにする構成とすればよい。 In the present embodiment, an example is shown in which both the internal step-down power supply block 101 and the internal step-up power supply block 112 are operated when the external power supply 102 is in a low voltage range. However, the present invention is not limited to this. In the voltage range, the operation of the internal step-down power supply block 101 can be stopped and only the internal step-up power supply block 112 can be operated to supply the internal power supply 103. In this case, a logic circuit in which the first detection signal 107 and the second detection signal 119 are input to the gate input of the step-down PMOS transistor 108 in the internal step-down power supply block 101, more specifically an OR circuit or the like. When the external power supply 102 is in the low voltage range, that is, when the second detection signal 119 is at the H level, the gate input of the step-down PMOS transistor 108 may be set to the H level.
　また、本実施形態では、リファレンス電圧１０５を定電圧の１．３Ｖとして設定した一例を示したが、これに限定するものではなく、リファレンス生成回路１０４内で任意の電圧に設定しても同様の効果を実現できる。これと、内部電源フィードバック電圧１１１を任意の電圧に設定することにより、メモリに供給する内部電源１０３の電圧を自由に設定することができるため、メモリで複数の電圧の内部電源１０３が要求される場合でも対応することが可能となる。 In the present embodiment, an example in which the reference voltage 105 is set to a constant voltage of 1.3 V has been described. However, the present invention is not limited to this, and the same voltage may be set in the reference generation circuit 104. The effect can be realized. By setting the internal power supply feedback voltage 111 to an arbitrary voltage, the voltage of the internal power supply 103 supplied to the memory can be freely set. Therefore, the memory requires the internal power supply 103 having a plurality of voltages. It is possible to cope with even cases.
　また、本実施形態では、外部電源１０２が内部電源１０３の電圧である２．６Ｖを下回ったときに内部昇圧電源ブロック１１２を動作させる一例を示したが、これに限定するものではなく、外部電源１０２と内部電源１０３との電圧差が小さくなったとき、一例としては外部電源１０２が２．７Ｖ程度の電圧まで低下したときに内部昇圧電源ブロック１１２を動作させる等しても、同等の効果を実現できる。この場合には、外部電源１０２と内部電源１０３との電圧差が小さくなることによって、外部電源１０２から降圧用ＰＭＯＳトランジスタ１０８を介して内部電源１０３に電流を供給する際の電力効率が低下する前に内部昇圧電源ブロック１１２を動作させることによって、内部電源１０３を供給する際に電力効率が低下するのを抑制することが可能となる。 In the present embodiment, an example is shown in which the internal boost power supply block 112 is operated when the external power supply 102 falls below 2.6 V, which is the voltage of the internal power supply 103. However, the present invention is not limited to this. For example, when the voltage difference between the internal power supply 103 and the internal power supply 103 becomes small, even if the internal boost power supply block 112 is operated when the external power supply 102 drops to a voltage of about 2.7 V, for example, the same effect can be obtained. realizable. In this case, the voltage difference between the external power supply 102 and the internal power supply 103 is reduced before power efficiency when current is supplied from the external power supply 102 to the internal power supply 103 via the step-down PMOS transistor 108 is reduced. By operating the internal boost power supply block 112 at the same time, it is possible to suppress a reduction in power efficiency when the internal power supply 103 is supplied.
　《第２の実施形態》
　図２は、本発明の第２の実施形態による内部電源回路を備えた半導体集積回路の概略構成を示す図である。以下、内部電源回路を備えた半導体集積回路の代表的な内部電源生成の動作における本発明の実施の形態を説明する。 << Second Embodiment >>
FIG. 2 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the second embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.
　なお、図２の構成要素のうちで図１に記載している構成要素と同じ構成を持つものに関しては同じ符号を付与している。 In addition, the same code | symbol is provided about the component which has the same structure as the component described in FIG. 1 among the components of FIG.
　本発明の第２の実施形態での半導体集積回路は、内部降圧電源ブロック２００と、内部昇圧電源ブロック２０１と、リファレンス生成回路１０４とから構成される。 The semiconductor integrated circuit according to the second embodiment of the present invention includes an internal step-down power supply block 200, an internal step-up power supply block 201, and a reference generation circuit 104.
　内部降圧電源ブロック２００は、３．３Ｖの外部電源１０２、２．６Ｖが必要となる内部電源１０３、リファレンス回路１０４において定電圧源等から生成される１．３Ｖの定電圧であるリファレンス電圧１０５、リファレンス電圧１０５と後述の内部電源フィードバック電圧１１１とが入力され、内部電源フィードバック電圧１１１がリファレンス電圧１０５より低くなった場合に検知信号Ｌレベルを出力する第１のアンプ回路１０６、第１のアンプ回路１０６で生成される検知信号である第１の検知信号１０７、外部電源１０２又は後述の内部昇圧電源２０４から内部電源１０３を生成するための降圧用ＰＭＯＳトランジスタ１０８、内部電源１０３の電圧をもとに内部電源１０３の２分の１の電圧を出力するための第１の抵抗素子１０９、第１の抵抗素子１０９と同じ抵抗値を持つ第２の抵抗素子１１０、内部電源１０３から第１の抵抗素子１０９を介して内部電源１０３の２分の１の電圧値として出力される内部電源フィードバック電圧１１１、後述する内部昇圧電源ブロック２０１で生成する内部昇圧電源２０４、後述する内部昇圧電源ブロック２０１内で生成される第２の検知信号１１９の信号論理を反転させるためのインバータ回路で構成される第１の論理回路２０５、第１の論理回路２０５によって第２の検知信号１１９の信号論理を反転させた信号である第３の検知信号２０６、外部電源１０２と降圧用ＰＭＯＳトランジスタ１０８のソースノードとの間の接続を第３の検知信号２０６で制御し、第３の検知信号２０６がＨレベルのときに両端のノードを接続、Ｌレベルのときには切断する第１のスイッチ２０２、後述する内部昇圧電源２０４と降圧用ＰＭＯＳトランジスタ１０８のソースノードとの間の接続を第２の検知信号１１９で制御し、第２の検知信号１１９がＨレベルのときに両端のノードを接続、Ｌレベルのときには切断する第２のスイッチ２０３から構成されている。 The internal step-down power supply block 200 includes a 3.3V external power supply 102, an internal power supply 103 that requires 2.6V, a reference voltage 105 that is a 1.3V constant voltage generated from a constant voltage source or the like in the reference circuit 104, A first amplifier circuit 106 and a first amplifier circuit which output a detection signal L level when a reference voltage 105 and an internal power supply feedback voltage 111 described later are input and the internal power supply feedback voltage 111 becomes lower than the reference voltage 105. Based on the first detection signal 107 which is a detection signal generated at 106, the voltage of the step-down PMOS transistor 108 for generating the internal power supply 103 from the external power supply 102 or the internal boosting power supply 204 described later, and the voltage of the internal power supply 103. First resistance element 1 for outputting a half voltage of the internal power supply 103 9. The second resistance element 110 having the same resistance value as that of the first resistance element 109, and an internal voltage output from the internal power supply 103 via the first resistance element 109 as a half voltage value of the internal power supply 103. A power feedback voltage 111, an internal boost power supply 204 generated by an internal boost power supply block 201 described later, and an inverter circuit for inverting the signal logic of a second detection signal 119 generated in the internal boost power supply block 201 described later First logic circuit 205, third detection signal 206 which is a signal obtained by inverting the signal logic of the second detection signal 119 by the first logic circuit 205, the source of the external power supply 102 and the step-down PMOS transistor 108 The connection between the nodes is controlled by the third detection signal 206, and the nodes at both ends are connected when the third detection signal 206 is at the H level. The first detection switch 202 that is disconnected when it is at the L level, the connection between the internal boosting power supply 204 described later and the source node of the step-down PMOS transistor 108 are controlled by the second detection signal 119, and the second detection signal 119 is The second switch 203 is configured to connect the nodes at both ends when the level is H and to disconnect when the level is the L level.
　内部昇圧電源ブロック２０１は、３．３Ｖの外部電源１０２、昇圧動作の実施により生成する内部昇圧電源２０４、外部電源１０２を昇圧して内部昇圧電源２０４を生成するためのポンプ回路１１３、外部電源１０２が供給されると自動的に昇圧動作のための基準信号を生成し、入力される制御信号のレベルに応じてこの基準信号を出力するかどうかを制御するオシレータ回路１１４、外部電源１０２をもとに外部電源１０２の２分の１の電圧を出力するための第３の抵抗素子１１５、第３の抵抗素子１１５と同じ抵抗値を持つ第４の抵抗素子１１６、第３の抵抗素子１１５を介して外部電源１０２の２分の１の電圧値として出力される外部電源フィードバック電圧１１７、リファレンス電圧１０５と外部電源フィードバック電圧１１７とが入力され、外部電源フィードバック電圧１１７がリファレンス電圧１０５より低くなった場合に検知信号Ｈレベルを出力する第２のアンプ回路１１８、第２のアンプ回路１１８で生成される検知信号であり内部降圧電源ブロック２００にも入力される第２の検知信号１１９、第２の検知信号１１９の信号論理を反転させるためのインバータ回路で構成される第２の論理回路２０７、第２の論理回路２０７を介して第２の検知信号１１９の信号論理を反転した信号であり、オシレータ回路１１４で生成される基準信号を出力するかどうかを制御する第１の論理信号２０８、オシレータ回路１１４から出力されてポンプ回路１１３に入力される、内部昇圧動作を実施するためのオシレータ信号である第２の論理信号１２４から構成されている。 The internal boost power supply block 201 includes a 3.3 V external power supply 102, an internal boost power supply 204 generated by performing a boost operation, a pump circuit 113 for boosting the external power supply 102 to generate the internal boost power supply 204, and the external power supply 102. Is automatically generated, and an oscillator circuit 114 for controlling whether or not to output this reference signal according to the level of the input control signal is generated based on the external power supply 102. Through the third resistance element 115 for outputting a half voltage of the external power supply 102, the fourth resistance element 116 having the same resistance value as the third resistance element 115, and the third resistance element 115. The external power supply feedback voltage 117, the reference voltage 105, and the external power supply feedback voltage 117 are output as a half voltage value of the external power supply 102. The second amplifier circuit 118 that outputs a detection signal H level when the external power supply feedback voltage 117 is lower than the reference voltage 105, and is a detection signal generated by the second amplifier circuit 118 and an internal step-down power supply block The second detection signal 119 input also to the second detection signal 119, the second logic circuit 207 configured by an inverter circuit for inverting the signal logic of the second detection signal 119, and the second logic circuit 207 via the second logic circuit 207. 2 is a signal obtained by inverting the signal logic of the detection signal 119, the first logic signal 208 for controlling whether or not to output the reference signal generated by the oscillator circuit 114, and output from the oscillator circuit 114 to the pump circuit 113. It is composed of a second logic signal 124 that is an input oscillator signal for performing an internal boosting operation.
　内部降圧電源ブロック２００では、外部電源１０２から第１のスイッチ２０２を介した後、又は後述する内部昇圧電源２０４から第２のスイッチ２０３を介した後に、降圧用ＰＭＯＳトランジスタ１０８を介して内部電源１０３に電流を供給することにより、内部電源１０３としてメモリ（図示していない）に電流を供給する。第１のスイッチ２０２及び第２のスイッチ２０３の接続切り替えは、外部電源１０２の電圧レベルによって後述の内部昇圧電源ブロック２０１で生成される第２の検知信号１１９によって行われる。 In the internal step-down power supply block 200, the external power supply 102 passes through the first switch 202, or the internal booster power supply 204, which will be described later, passes through the second switch 203, and then passes through the step-down PMOS transistor 108. Current is supplied to the memory (not shown) as the internal power supply 103. The connection between the first switch 202 and the second switch 203 is switched by a second detection signal 119 generated by an internal boosting power supply block 201 described later according to the voltage level of the external power supply 102.
　一方、内部昇圧電源ブロック２０１では、外部電源１０２をポンプ回路１１３に供給し、オシレータ回路１１４からポンプ回路１１３を動作させるための第２の論理信号１２４が入力された場合に、外部電源１０２を昇圧して内部昇圧電源２０４が生成され、これを内部降圧電源ブロック２００に供給する。オシレータ回路１１４は、外部電源１０２の供給とともに内部で自動で生成している基準信号を、第２の検知信号１１９の反転信号である第１の論理信号２０８がＬレベルのときに第２の論理信号１２４として出力し、第１の論理信号２０８がＨレベルのときには何も出力しない回路構成をとっている。 On the other hand, in the internal boost power supply block 201, the external power supply 102 is supplied to the pump circuit 113, and when the second logic signal 124 for operating the pump circuit 113 is input from the oscillator circuit 114, the external power supply 102 is boosted. Thus, an internal boost power supply 204 is generated and supplied to the internal step-down power supply block 200. The oscillator circuit 114 generates a reference signal that is automatically generated internally with the supply of the external power supply 102 when the first logic signal 208, which is an inverted signal of the second detection signal 119, is at the L level. The circuit configuration is such that the signal 124 is output and nothing is output when the first logic signal 208 is at the H level.
　以上のように構成された本発明の第２の実施形態に関して、最初に外部電源１０２が３．３Ｖ程度の通常電圧範囲（第１の電圧範囲）、一例として外部電源１０２が３．３Ｖ、内部電源１０３が２．６Ｖの場合を例として説明する。 Regarding the second embodiment of the present invention configured as described above, first, the external power source 102 has a normal voltage range of about 3.3V (first voltage range). As an example, the external power source 102 has 3.3V, A case where the power supply 103 is 2.6 V will be described as an example.
　まず、内部降圧電源ブロック２００では、内部電源１０３が所望の電圧である２．６Ｖを下回った場合、第１の抵抗素子１０９と第２の抵抗素子１１０とを介して内部電源１０３の２分の１の電圧（＜１．３Ｖ）が内部電源フィードバック電圧１１１として第１のアンプ回路１０６に入力される。一方、リファレンス生成回路１０４で生成された定電圧１．３Ｖであるリファレンス電圧１０５も第１のアンプ回路１０６に入力され、両者の間で電圧比較が行われる。この場合には、内部電源フィードバック電圧１１１（＜１．３Ｖ）の方がリファレンス電圧１０５（＝１．３Ｖ）よりも低いため、第１のアンプ回路１０６は検知信号として第１の検知信号１０７にＬレベルの信号を出力する。これを受けて、降圧用ＰＭＯＳトランジスタ１０８のゲート入力がＬレベルとなり、降圧用ＰＭＯＳトランジスタ１０８はオンする。一方、このとき、内部昇圧電源ブロック２０１では、外部電源１０２が３．３Ｖであるために、外部電源１０２の電圧をモニターするための第３の抵抗素子１１５と第４の抵抗素子１１６とによって外部電源１０２の２分の１の電圧である外部電源フィードバック電圧１１７（＝１．６５Ｖ）を常時生成している。外部電源フィードバック電圧１１７と、前述のリファレンス生成回路１０４で生成した定電圧１．３Ｖであるリファレンス電圧１０５とを、第２のアンプ回路１１８に入力する。外部電源１０２は通常電圧範囲であり３．３Ｖの電圧を保持しているため、外部電源フィードバック電圧１１７（＝１．６５Ｖ）はリファレンス電圧１０５（＝１．３Ｖ）を上回っており、両者を比較して第２のアンプ回路１１８はＬレベルの信号を第２の検知信号１１９として出力する。この第２の検知信号１１９がＬレベルであることを受けて、内部降圧電源ブロック２００では、第２の検知信号１１９の反転信号である第３の検知信号２０６がＨレベルの信号となるため、第１のスイッチ２０２にはＨレベルが印加され、第１のスイッチ２０２は接続される。一方、第２のスイッチ２０３には第２の検知信号１１９がＬレベルとして印加されるため、第２のスイッチ２０３はオープン状態となり、内部昇圧電源２０４と降圧用ＰＭＯＳトランジスタ１０８とは接続されずにオープン状態となる。 First, in the internal step-down power supply block 200, when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 (<1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111. On the other hand, the reference voltage 105, which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two. In this case, since the internal power supply feedback voltage 111 (<1.3 V) is lower than the reference voltage 105 (= 1.3 V), the first amplifier circuit 106 outputs the first detection signal 107 as a detection signal. An L level signal is output. In response, the gate input of the step-down PMOS transistor 108 becomes L level, and the step-down PMOS transistor 108 is turned on. On the other hand, at this time, in the internal boost power supply block 201, since the external power supply 102 is 3.3 V, the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are externally connected. An external power supply feedback voltage 117 (= 1.65 V) that is a half voltage of the power supply 102 is constantly generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is in the normal voltage range and holds a voltage of 3.3 V, the external power supply feedback voltage 117 (= 1.65 V) exceeds the reference voltage 105 (= 1.3 V). Then, the second amplifier circuit 118 outputs an L level signal as the second detection signal 119. In response to the fact that the second detection signal 119 is at the L level, in the internal step-down power supply block 200, the third detection signal 206, which is an inverted signal of the second detection signal 119, becomes an H level signal. An H level is applied to the first switch 202, and the first switch 202 is connected. On the other hand, since the second detection signal 119 is applied to the second switch 203 as the L level, the second switch 203 is in an open state, and the internal boost power supply 204 and the step-down PMOS transistor 108 are not connected. Open state.
　これにより、第１のスイッチ２０２が接続されて第２のスイッチ２０３はオフされ、更に降圧用ＰＭＯＳトランジスタ１０８がオンされることから、外部電源１０２は、内部電源１０３へ第１のスイッチ２０２と降圧用ＰＭＯＳトランジスタ１０８とを介して電流を供給し、内部電源１０３を所望の電圧である２．６Ｖまで上昇させる。内部電源１０３に十分な電流が供給され、所望の電圧である２．６Ｖまで達すると、内部電源フィードバック電圧１１１は内部電源１０３の２分の１の電圧と設定しているために１．３Ｖに達し、第１のアンプ回路１０６では、内部電源フィードバック電圧１１１がリファレンス電圧１０５よりも高くなるため、第１の検知信号１０７はＬレベルからＨレベルへと切り替わる。これを受けて、降圧用ＰＭＯＳトランジスタ１０８のゲート入力がＬレベルからＨレベルへと切り替わるために降圧用ＰＭＯＳトランジスタ１０８はオフし、外部電源１０２から内部電源１０３への電流供給は止まる。 As a result, the first switch 202 is connected, the second switch 203 is turned off, and the step-down PMOS transistor 108 is turned on, so that the external power supply 102 is stepped down with the first switch 202 to the internal power supply 103. A current is supplied through the PMOS transistor 108 to raise the internal power supply 103 to a desired voltage of 2.6V. When a sufficient current is supplied to the internal power supply 103 and reaches the desired voltage of 2.6 V, the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and is thus set to 1.3 V. In the first amplifier circuit 106, since the internal power supply feedback voltage 111 becomes higher than the reference voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off and the current supply from the external power supply 102 to the internal power supply 103 is stopped.
　このようにして、内部降圧電源ブロック２００は、内部電源１０３が所望の電圧である２．６Ｖを下回ると降圧動作を実施して外部電源１０２から内部電源１０３へ電流を供給して内部電源１０３が２．６Ｖを維持するよう動作する。 In this way, the internal step-down power supply block 200 performs the step-down operation when the internal power supply 103 falls below the desired voltage of 2.6 V, and supplies current from the external power supply 102 to the internal power supply 103. Operates to maintain 2.6V.
　一方、このとき、内部昇圧電源ブロック２０１は、前述のように外部電源１０２の電圧をモニターするための第３の抵抗素子１１５と第４の抵抗素子１１６とによって外部電源１０２の２分の１の電圧である外部電源フィードバック電圧１１７を常時生成している。外部電源フィードバック電圧１１７と、前述のリファレンス生成回路１０４で生成した定電圧１．３Ｖであるリファレンス電圧１０５とを、第２のアンプ回路１１８に入力する。外部電源１０２は通常電圧範囲であり３．３Ｖの電圧を保持しているため、外部電源フィードバック電圧１１７（＝１．６５Ｖ）はリファレンス電圧１０５（＝１．３Ｖ）を上回っており、両者を比較して第２のアンプ回路１１８はＬレベルの信号を第２の検知信号１１９として出力する。第２の検知信号１１９がＬレベルを出力することを受けて、第２の論理回路２０７を介してオシレータ回路１１４の入力である第１の論理信号２０８にはＨレベルの信号が出力される。オシレータ回路１１４は、入力である第１の論理信号２０８がＨレベルで入力されるため、内部で生成している基準信号を出力せず、後段のポンプ回路１１３へは何も入力されないために昇圧動作は実施されない。 On the other hand, at this time, the internal boost power supply block 201 is half of the external power supply 102 by the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 as described above. The external power supply feedback voltage 117 that is a voltage is constantly generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is in the normal voltage range and holds a voltage of 3.3 V, the external power supply feedback voltage 117 (= 1.65 V) exceeds the reference voltage 105 (= 1.3 V). Then, the second amplifier circuit 118 outputs an L level signal as the second detection signal 119. In response to the output of the second detection signal 119 to an L level, an H level signal is output to the first logic signal 208 that is the input of the oscillator circuit 114 via the second logic circuit 207. Since the first logic signal 208 that is an input is input at the H level, the oscillator circuit 114 does not output the internally generated reference signal and does not input anything to the pump circuit 113 in the subsequent stage, so that the voltage is boosted. The action is not performed.
　このため、内部昇圧電源ブロック２０１は、外部電源１０２が通常電圧範囲である３．３Ｖの電圧を保持している場合には、内部電源１０３の電圧レベルによらずに昇圧動作は実施せず、内部昇圧電源２０４としても電流供給を実施しない。 Therefore, the internal boost power supply block 201 does not perform the boost operation regardless of the voltage level of the internal power supply 103 when the external power supply 102 holds a voltage of 3.3 V that is the normal voltage range. The internal boost power supply 204 is not supplied with current.
　よって、外部電源１０２が通常電圧範囲である場合に、内部電源１０３の電圧レベルが低下したときには内部降圧電源ブロック２００からのみ電流供給を実施して内部電源１０３の電圧を２．６Ｖに維持するように動作する。 Therefore, when the external power supply 102 is in the normal voltage range, when the voltage level of the internal power supply 103 decreases, current is supplied only from the internal step-down power supply block 200 so that the voltage of the internal power supply 103 is maintained at 2.6V. To work.
　次に、外部電源１０２が２．５Ｖ程度の低電圧範囲（前記第１の電圧範囲より低い第２の電圧範囲）、一例として外部電源１０２が２．５Ｖ、内部電源１０３が２．６Ｖの場合を例として説明する。 Next, when the external power supply 102 is in a low voltage range of about 2.5V (second voltage range lower than the first voltage range), for example, the external power supply 102 is 2.5V and the internal power supply 103 is 2.6V. Will be described as an example.
　まず、内部降圧電源ブロック２００では、内部電源１０３が所望の電圧である２．６Ｖを下回った場合、第１の抵抗素子１０９と第２の抵抗素子１１０とを介して内部電源１０３の２分の１の電圧（＜１．３Ｖ）が内部電源フィードバック電圧１１１として第１のアンプ回路１０６に入力される。一方、リファレンス生成回路１０４で生成された定電圧１．３Ｖであるリファレンス電圧１０５も第１のアンプ回路１０６に入力され、両者の間で電圧比較が行われる。この場合には、内部電源フィードバック電圧１１１（＜１．３Ｖ）の方がリファレンス電圧１０５（＝１．３Ｖ）よりも低いため、第１のアンプ回路１０６は検知信号として第１の検知信号１０７にＬレベルの信号を出力する。これを受けて、降圧用ＰＭＯＳトランジスタ１０８のゲート入力がＬレベルとなり、降圧用ＰＭＯＳトランジスタ１０８はオンする。一方、このとき、内部昇圧電源ブロック２０１では、外部電源１０２が２．５Ｖであるために、外部電源１０２の電圧をモニターするための第３の抵抗素子１１５と第４の抵抗素子１１６とによって外部電源１０２の２分の１の電圧である外部電源フィードバック電圧１１７（＝１．２５Ｖ）を常時生成している。外部電源フィードバック電圧１１７と、前述のリファレンス生成回路１０４で生成した定電圧１．３Ｖであるリファレンス電圧１０５とを、第２のアンプ回路１１８に入力する。外部電源１０２は低電圧範囲であり２．５Ｖの電圧であるため、外部電源フィードバック電圧１１７（＝１．２５Ｖ）はリファレンス電圧１０５（＝１．３Ｖ）を下回っており、両者を比較して第２のアンプ回路１１８はＨレベルの信号を第２の検知信号１１９として出力する。この第２の検知信号１１９がＨレベルであることを受けて、内部降圧電源ブロック２００では、第２の検知信号１１９の反転信号である第３の検知信号２０６がＬレベルの信号となるため、第１のスイッチ２０２にはＬレベルが印加され、第１のスイッチ２０２はオープン状態となる。一方、第２のスイッチ２０３には第２の検知信号１１９がＨレベルとして印加されるため、第２のスイッチ２０３が接続された状態となり、内部昇圧電源２０４と降圧用ＰＭＯＳトランジスタ１０８とが接続された状態となる。つまり、後述する内部昇圧電源ブロック２０１で昇圧された内部昇圧電源２０４が内部降圧電源ブロック２００に供給されるため、内部昇圧電源２０４から第２のスイッチ２０３と降圧用ＰＭＯＳトランジスタ１０８とを介して内部電源１０３へ電流を供給し、内部電源１０３を所望の電圧である２．６Ｖまで上昇させる。内部電源１０３が２．６Ｖに達した時点で内部電源フィードバック電圧１１１は内部電源１０３の２分の１の電圧と設定しているために１．３Ｖに達し、第１のアンプ回路１０６では、内部電源フィードバック電圧１１１がリファレンス電圧１０５よりも高くなるため、第１の検知信号１０７はＬレベルからＨレベルへと切り替わる。これを受けて、降圧用ＰＭＯＳトランジスタ１０８のゲート入力がＬレベルからＨレベルへと切り替わるために降圧用ＰＭＯＳトランジスタ１０８はオフし、内部昇圧電源２０４から内部電源１０３への電流供給は止まる。 First, in the internal step-down power supply block 200, when the internal power supply 103 falls below a desired voltage of 2.6 V, the internal power supply 103 is divided into two minutes through the first resistance element 109 and the second resistance element 110. 1 (<1.3 V) is input to the first amplifier circuit 106 as the internal power supply feedback voltage 111. On the other hand, the reference voltage 105, which is a constant voltage of 1.3 V generated by the reference generation circuit 104, is also input to the first amplifier circuit 106, and voltage comparison is performed between the two. In this case, since the internal power supply feedback voltage 111 (<1.3 V) is lower than the reference voltage 105 (= 1.3 V), the first amplifier circuit 106 outputs the first detection signal 107 as a detection signal. An L level signal is output. In response, the gate input of the step-down PMOS transistor 108 becomes L level, and the step-down PMOS transistor 108 is turned on. On the other hand, at this time, in the internal boost power supply block 201, since the external power supply 102 is 2.5 V, the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are externally connected. An external power supply feedback voltage 117 (= 1.25 V), which is a half voltage of the power supply 102, is always generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is in a low voltage range and a voltage of 2.5 V, the external power supply feedback voltage 117 (= 1.25 V) is lower than the reference voltage 105 (= 1.3 V). The second amplifier circuit 118 outputs an H level signal as the second detection signal 119. In response to the fact that the second detection signal 119 is at the H level, in the internal step-down power supply block 200, the third detection signal 206 that is an inverted signal of the second detection signal 119 is an L level signal. The L level is applied to the first switch 202, and the first switch 202 is opened. On the other hand, since the second detection signal 119 is applied as the H level to the second switch 203, the second switch 203 is connected, and the internal boosting power source 204 and the step-down PMOS transistor 108 are connected. It becomes the state. That is, since the internal boost power supply 204 boosted by the internal boost power supply block 201 described later is supplied to the internal step-down power supply block 200, the internal boost power supply 204 internally passes through the second switch 203 and the step-down PMOS transistor 108. A current is supplied to the power supply 103 to raise the internal power supply 103 to a desired voltage of 2.6V. When the internal power supply 103 reaches 2.6 V, the internal power supply feedback voltage 111 is set to a voltage half that of the internal power supply 103 and thus reaches 1.3 V. In the first amplifier circuit 106, Since the power supply feedback voltage 111 becomes higher than the reference voltage 105, the first detection signal 107 is switched from the L level to the H level. In response to this, the gate input of the step-down PMOS transistor 108 is switched from the L level to the H level, so that the step-down PMOS transistor 108 is turned off, and the current supply from the internal boost power supply 204 to the internal power supply 103 is stopped.
　一方、このとき、内部昇圧電源ブロック２０１では、外部電源１０２の電圧をモニターするための第３の抵抗素子１１５と第４の抵抗素子１１６とによって外部電源１０２の２分の１の電圧である外部電源フィードバック電圧１１７（＝１．２５Ｖ）を常時生成している。外部電源フィードバック電圧１１７と、前述のリファレンス生成回路１０４で生成した定電圧１．３Ｖであるリファレンス電圧１０５とを、第２のアンプ回路１１８に入力する。外部電源１０２は低電圧範囲であり２．５Ｖの電圧であるため、外部電源フィードバック電圧１１７（＝１．２５Ｖ）はリファレンス電圧１０５（＝１．３Ｖ）を下回っており、両者を比較して第２のアンプ回路１１８はＨレベルの信号を第２の検知信号１１９として出力する。第２の検知信号１１９がＨレベルを出力することを受けて、第２の論理回路２０７を介してオシレータ回路１１４の入力である第１の論理信号２０８にはＬレベルの信号が出力される。オシレータ回路１１４は、入力である第１の論理信号２０８がＬレベルで入力されるため、内部で生成している基準信号を第２の論理信号１２４としてポンプ回路１１３へ出力し、ポンプ回路１１３はこれを受けて昇圧動作を実施する。ポンプ回路１１３で昇圧された内部昇圧電源２０４は内部降圧電源ブロック２００へ供給され、前述の内部降圧電源ブロック２００での動作により、内部電源１０３に電流を供給するための電流ソースとなり内部降圧電源ブロック２００での動作により内部電源１０３が所望の電圧である２．６Ｖに達するまで電流を供給する。外部電源１０２が内部電源１０３の所望の電圧である２．６Ｖを再度上回った場合には、外部電源フィードバック電圧１１７が１．３Ｖを上回るため、第２のアンプ回路１１８の出力である第２の検知信号１１９はＨレベルからＬレベルに切り替わり、インバータ回路である第２の論理回路２０７を介してオシレータ回路１１４への入力信号である第１の論理信号２０８はＬレベルからＨレベルへと切り替わり、これを受けてオシレータ回路１１４は内部で生成している基準信号をポンプ回路１１３に出力するのを止め、ポンプ回路１１３は昇圧動作を止める。 On the other hand, at this time, in the internal boost power supply block 201, the third resistance element 115 and the fourth resistance element 116 for monitoring the voltage of the external power supply 102 are external voltages that are half the voltage of the external power supply 102. A power supply feedback voltage 117 (= 1.25 V) is constantly generated. The external power supply feedback voltage 117 and the reference voltage 105 that is the constant voltage 1.3 V generated by the reference generation circuit 104 are input to the second amplifier circuit 118. Since the external power supply 102 is in a low voltage range and a voltage of 2.5 V, the external power supply feedback voltage 117 (= 1.25 V) is lower than the reference voltage 105 (= 1.3 V). The second amplifier circuit 118 outputs an H level signal as the second detection signal 119. In response to the output of the second detection signal 119 at the H level, an L level signal is output to the first logic signal 208 that is the input of the oscillator circuit 114 via the second logic circuit 207. Since the first logic signal 208 as an input is input at the L level, the oscillator circuit 114 outputs the internally generated reference signal to the pump circuit 113 as the second logic signal 124. The pump circuit 113 In response to this, a boosting operation is performed. The internal boost power supply 204 boosted by the pump circuit 113 is supplied to the internal step-down power supply block 200, and becomes the current source for supplying current to the internal power supply 103 by the operation of the internal step-down power supply block 200 described above. The operation at 200 supplies current until the internal power supply 103 reaches a desired voltage of 2.6V. When the external power supply 102 again exceeds the desired voltage of 2.6 V, which is the internal power supply 103, the external power supply feedback voltage 117 exceeds 1.3 V, so that the second output that is the output of the second amplifier circuit 118 is output. The detection signal 119 is switched from the H level to the L level, and the first logic signal 208 that is an input signal to the oscillator circuit 114 is switched from the L level to the H level via the second logic circuit 207 that is an inverter circuit. In response to this, the oscillator circuit 114 stops outputting the internally generated reference signal to the pump circuit 113, and the pump circuit 113 stops the boosting operation.
　このように内部昇圧電源ブロック２０１は、外部電源１０２が低電圧範囲である場合には、外部電源１０２の電圧レベルに応じて昇圧動作を実施するどうかを制御され、外部電源１０２が内部電源１０３の所望の電圧である２．６Ｖを上回っているときには昇圧動作は実施せず、外部電源１０２が２．６Ｖを下回っているときには昇圧動作を実施し、２．６Ｖを上回った時点で昇圧動作を停止する動作をとる。 Thus, when the external power supply 102 is in the low voltage range, the internal boost power supply block 201 is controlled to perform the boost operation according to the voltage level of the external power supply 102, and the external power supply 102 is connected to the internal power supply 103. When the voltage exceeds 2.6V, which is the desired voltage, the boost operation is not performed. When the external power supply 102 is less than 2.6V, the voltage boost operation is performed. When the voltage exceeds 2.6V, the voltage boost operation is stopped. Take action to do.
　よって、外部電源１０２が低電圧範囲である場合に、内部電源１０３の電圧レベルが低下したときには、内部降圧電源ブロック２００において外部電源１０２から内部電源１０３へ十分な電流供給ができなくなるために、内部昇圧電源ブロック２０１において昇圧した内部昇圧電源２０４を電源として内部降圧電源ブロック２００に外部電源１０２の代わりに電流を供給し、内部昇圧電源２０４から第２のスイッチ２０３と降圧用ＰＭＯＳトランジスタ１０８とを介して内部電源１０３に電流を供給して内部電源１０３を所望の電圧である２．６Ｖに維持する動作をとる。 Therefore, when the external power supply 102 is in the low voltage range, when the voltage level of the internal power supply 103 decreases, the internal step-down power supply block 200 cannot supply sufficient current from the external power supply 102 to the internal power supply 103. A current is supplied to the internal step-down power supply block 200 instead of the external power supply 102 using the internal step-up power supply 204 boosted in the step-up power supply block 201 as a power source, and the internal boost power supply 204 passes through the second switch 203 and the step-down PMOS transistor 108. The current is supplied to the internal power supply 103 to maintain the internal power supply 103 at a desired voltage of 2.6V.
　以上のような構成によれば、外部電源１０２の電圧がメモリに供給する内部電源１０３の電圧を下回った場合、つまり外部電源１０２の電圧が低電圧となった場合でも、内部降圧電源ブロック２００において内部電源１０３に電流を供給する電源を、外部電源１０２から内部昇圧電源２０４に切り替えて内部電源１０３に電流を供給することにより、安定した内部電源１０３をメモリに供給することが可能となり、回路面積や電力効率の観点から見ても、従来例のように複数の内部昇圧回路を搭載する場合に対して大幅な面積削減、電力削減を同時に実現できる。 According to the configuration as described above, even when the voltage of the external power supply 102 falls below the voltage of the internal power supply 103 supplied to the memory, that is, when the voltage of the external power supply 102 becomes low, the internal step-down power supply block 200 By switching the power supply for supplying current to the internal power supply 103 from the external power supply 102 to the internal boost power supply 204 and supplying the current to the internal power supply 103, it becomes possible to supply a stable internal power supply 103 to the memory. Also from the viewpoint of power efficiency, a large area reduction and power reduction can be realized at the same time as in the case where a plurality of internal booster circuits are mounted as in the conventional example.
　また、リファレンス生成回路１０４やリファレンス電圧１０５及び第２の検知信号１１９を内部降圧電源ブロック２００と内部昇圧電源ブロック２０１とで共用することにより、個別にそれぞれの回路を構成する場合に対して回路面積を大幅に削減することが可能となる。 Further, by sharing the reference generation circuit 104, the reference voltage 105, and the second detection signal 119 between the internal step-down power supply block 200 and the internal step-up power supply block 201, the circuit area can be reduced compared to the case where each circuit is individually configured. Can be greatly reduced.
　また、内部電源１０３が低下しているかどうかを検知するための内部電源フィードバック電圧１１１、及び外部電源１０２が低下しているかどうかを検知するための外部電源フィードバック電圧１１７を、それぞれ第１の抵抗素子１０９、第２の抵抗素子１１０、第３の抵抗素子１１５、第４の抵抗素子１１６を用いて２分の１の電圧に変換して検知に用いることにより、外部電源１０２が内部電源１０３を下回った場合でも、第１のアンプ回路１０６及び第２のアンプ回路１１８に内部電源フィードバック電圧１１１と同じレベルの電圧（１．３Ｖ程度）を供給できるため、安定した検知動作を実現できる。これは、例えばリファレンス生成回路１０４で生成するリファレンス電圧１０５を２．６Ｖとし、内部電源１０３を電圧変換せずにそのまま両者を第１のアンプ回路１０６に入力して検知する回路構成をとった場合には、外部電源１０２が２．５Ｖに低下したとき、つまり内部電源１０３の所望の電圧である２．６Ｖを下回ってしまったとき等では、リファレンス生成回路１０４が２．５Ｖまでのリファレンス電圧１０５しか生成できなくなってしまい、これにより内部降圧電源ブロック２００及び内部昇圧電源ブロック２０１が動作しても、内部電源１０３を２．５Ｖまでしか上げられなくなってしまうという課題を解決できる構成である。外部電源フィードバック電圧１１７も、リファレンス電圧１０５を１．３Ｖの定電圧で生成していることに合わせて、外部電源１０２の２分の１の電圧に設定している。 In addition, an internal power supply feedback voltage 111 for detecting whether or not the internal power supply 103 is lowered, and an external power supply feedback voltage 117 for detecting whether or not the external power supply 102 is lowered are respectively connected to the first resistance elements. 109, the second resistance element 110, the third resistance element 115, and the fourth resistance element 116 are used to detect the voltage after being converted to a half voltage, so that the external power supply 102 is lower than the internal power supply 103. Even in this case, since the same level of voltage (about 1.3 V) as the internal power supply feedback voltage 111 can be supplied to the first amplifier circuit 106 and the second amplifier circuit 118, a stable detection operation can be realized. In this case, for example, the reference voltage 105 generated by the reference generation circuit 104 is 2.6 V, and the internal power supply 103 is input to the first amplifier circuit 106 as it is without voltage conversion and is detected. When the external power supply 102 drops to 2.5V, that is, when the voltage falls below 2.6V, which is the desired voltage of the internal power supply 103, the reference generation circuit 104 has a reference voltage 105 up to 2.5V. Therefore, even if the internal step-down power supply block 200 and the internal step-up power supply block 201 are operated, the problem that the internal power supply 103 can only be raised to 2.5V can be solved. The external power supply feedback voltage 117 is also set to a half voltage of the external power supply 102 in accordance with the generation of the reference voltage 105 at a constant voltage of 1.3V.
　なお、本実施形態では、内部電源フィードバック電圧１１１を内部電源１０３の２分の１の電圧に、外部電源フィードバック電圧１１７を外部電源１０２の２分の１の電圧に、リファレンス電圧１０５を１．３Ｖの定電圧にそれぞれ設定した一例を示したが、これに限定するものではなく、内部電源フィードバック電圧１１１、外部電源フィードバック電圧１１７、リファレンス電圧１０５が内部電源１０３より低い電圧であれば同等の効果を実現できる。 In this embodiment, the internal power supply feedback voltage 111 is set to a half voltage of the internal power supply 103, the external power supply feedback voltage 117 is set to a half voltage of the external power supply 102, and the reference voltage 105 is set to 1.3V. However, the present invention is not limited to this, and the same effect can be obtained if the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are lower than the internal power supply 103. realizable.
　また、本実施形態では、内部電源フィードバック電圧１１１、外部電源フィードバック電圧１１７、リファレンス電圧１０５を内部電源１０３より低い電圧に設定した一例を示したが、これに限定するものではなく、一例として示した抵抗素子や昇圧回路等の電圧変換回路を用いてより高い電圧に設定しても、同様にリファレンス電圧１０５も抵抗素子等の電圧変換回路や昇圧回路等を用いて高い電圧として供給すれば、外部電源１０２が低電圧となった場合にも電源回路として十分な動作を実現することができるため、同等の効果を実現できる。 In this embodiment, an example in which the internal power supply feedback voltage 111, the external power supply feedback voltage 117, and the reference voltage 105 are set to voltages lower than the internal power supply 103 is shown. However, the present invention is not limited to this, and is shown as an example. Even if a higher voltage is set using a voltage conversion circuit such as a resistance element or a booster circuit, the reference voltage 105 can be externally supplied as a higher voltage using a voltage conversion circuit such as a resistance element or a booster circuit. Even when the power supply 102 has a low voltage, a sufficient operation as a power supply circuit can be realized, so that the same effect can be realized.
　また、本実施形態では、内部電源フィードバック電圧１１１、外部電源フィードバック電圧１１７を生成するのに抵抗素子を用いる一例を示したが、これに限定するものではなく、電圧を変換する別の手段を用いても同等の効果を実現できる。 In the present embodiment, an example in which a resistance element is used to generate the internal power supply feedback voltage 111 and the external power supply feedback voltage 117 has been described. However, the present invention is not limited to this, and another means for converting the voltage is used. However, the same effect can be realized.
　また、本実施形態では、リファレンス電圧１０５を定電圧の１．３Ｖとして設定した一例を示したが、これに限定するものではなく、リファレンス生成回路１０４内で任意の電圧に設定しても同様の効果を実現できる。これと、内部電源フィードバック電圧１１１を任意の電圧に設定することにより、メモリに供給する内部電源１０３の電圧を自由に設定することができるため、メモリで複数の電圧の内部電源１０３が要求される場合でも対応することが可能となる。 In the present embodiment, an example in which the reference voltage 105 is set to a constant voltage of 1.3 V has been described. However, the present invention is not limited to this, and the same voltage may be set in the reference generation circuit 104. The effect can be realized. By setting the internal power supply feedback voltage 111 to an arbitrary voltage, the voltage of the internal power supply 103 supplied to the memory can be freely set. Therefore, the memory requires the internal power supply 103 having a plurality of voltages. It is possible to cope with even cases.
　また、本実施形態では、外部電源１０２が内部電源１０３の電圧である２．６Ｖを下回ったときに内部昇圧電源ブロック２０１を動作させる一例を示したが、これに限定するものではなく、外部電源１０２と内部電源１０３との電圧差が小さくなったとき、一例としては外部電源１０２が２．７Ｖ程度の電圧まで低下したときに内部昇圧電源ブロック２０１を動作させる等しても、同等の効果を実現できる。この場合には、外部電源１０２と内部電源１０３との電圧差が小さくなることによって、外部電源１０２から第１のスイッチ２０２と降圧用ＰＭＯＳトランジスタ１０８とを介して内部電源１０３に電流を供給する際の電力効率が低下する前に内部昇圧電源ブロック２０１を動作させることによって、内部電源１０３を供給する際に電力効率が低下するのを抑制することが可能となる。 In the present embodiment, an example is shown in which the internal booster power supply block 201 is operated when the external power supply 102 falls below 2.6 V, which is the voltage of the internal power supply 103. However, the present invention is not limited to this. For example, when the voltage difference between the internal power supply 103 and the internal power supply 103 becomes small, even if the internal boost power supply block 201 is operated when the external power supply 102 drops to a voltage of about 2.7 V, for example, the same effect can be obtained. realizable. In this case, when the voltage difference between the external power supply 102 and the internal power supply 103 is reduced, a current is supplied from the external power supply 102 to the internal power supply 103 via the first switch 202 and the step-down PMOS transistor 108. By operating the internal boost power supply block 201 before the power efficiency decreases, it is possible to suppress the power efficiency from decreasing when the internal power supply 103 is supplied.
　《第３の実施形態》
　図３は、本発明の第３の実施形態による内部電源回路を備えた半導体集積回路の概略構成を示す図である。以下、内部電源回路を備えた半導体集積回路の代表的な内部電源生成の動作における本発明の実施の形態を説明する。 << Third Embodiment >>
FIG. 3 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the third embodiment of the present invention. Hereinafter, embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit having an internal power supply circuit will be described.
　なお、図３の構成要素のうちで図１に記載している構成要素と同じ構成を持つものに関しては同じ符号を付与している。 In addition, the same code | symbol is provided about the component which has the same structure as the component described in FIG. 1 among the components of FIG.
　本発明の第１の実施形態での構成に加えて、本実施形態では、内部降圧電源ブロック１０１の出力と内部昇圧電源ブロック３００の出力とを結合して内部電源１０３とするにあたり、内部昇圧電源ブロック３００の中で、ポンプ回路１１３の出力経路上に第５の抵抗素子３０１と容量素子３０２とからなるフィルタを追加した回路で構成されている。内部降圧電源ブロック１０１の動作は本発明の第１の実施形態と同様である。 In addition to the configuration of the first embodiment of the present invention, in this embodiment, when the output of the internal step-down power supply block 101 and the output of the internal boost power supply block 300 are combined to form the internal power supply 103, the internal boost power supply The block 300 includes a circuit in which a filter composed of a fifth resistance element 301 and a capacitive element 302 is added on the output path of the pump circuit 113. The operation of the internal step-down power supply block 101 is the same as that of the first embodiment of the present invention.
　一般的に、内部で昇圧動作を実施して内部電源１０３を生成する場合にはポンプ動作による電圧変動から、内部電源１０３にも電圧変動ノイズが伝播してしまい、安定した内部電源１０３の供給が困難となったり、あるいは内部電源１０３の電圧が外部電源１０２の電圧に対して大きく上回ってしまった場合に、降圧用ＰＭＯＳトランジスタ１０８を介して内部電源１０３から外部電源１０２へと電流が逆流してしまうという懸念がある。 In general, when the internal power supply 103 is generated by performing the boosting operation internally, voltage fluctuation noise propagates to the internal power supply 103 due to voltage fluctuation caused by the pump operation, and a stable supply of the internal power supply 103 is achieved. When it becomes difficult or the voltage of the internal power supply 103 greatly exceeds the voltage of the external power supply 102, the current flows backward from the internal power supply 103 to the external power supply 102 via the step-down PMOS transistor 108. There is a concern that it will end up.
　これに対して、本実施形態のような構成によれば、内部昇圧電源ブロック３００の中で、内部電源１０３の出力部に第５の抵抗素子３０１と容量素子３０２とを追加することにより、ポンプ回路１１３での昇圧動作に起因する内部電源１０３の電圧変動ノイズを、第５の抵抗素子３０１と容量素子３０２とを介することで抑制し、メモリに供給する内部電源１０３への電圧変動ノイズにフィルタをかけ、より一層安定した電源として供給することが可能となる。 On the other hand, according to the configuration of the present embodiment, by adding the fifth resistance element 301 and the capacitive element 302 to the output part of the internal power supply 103 in the internal boost power supply block 300, the pump The voltage fluctuation noise of the internal power supply 103 caused by the boosting operation in the circuit 113 is suppressed via the fifth resistance element 301 and the capacitive element 302, and the voltage fluctuation noise to the internal power supply 103 supplied to the memory is filtered. It becomes possible to supply as a more stable power supply.
　これにより、複雑な回路追加は不要で回路面積の増大は抑制したうえで、昇圧、降圧動作で生成する内部電源１０３を、より一層安定した電源としてメモリに供給することが可能となる。 As a result, it is possible to supply the internal power supply 103 generated by the step-up / step-down operation to the memory as a more stable power supply without adding a complicated circuit and suppressing an increase in circuit area.
　なお、本実施形態では、内部電源１０３に対して抵抗素子、容量素子を追加する構成を一例として示したが、これに限定するものではなく、電圧変動を抑制する別の手段やクランプ回路、保護回路等、電圧変動ノイズや電流逆流を抑制する同等の機能を持つ構成を用いても同様の効果を実現できる。 In the present embodiment, a configuration in which a resistance element and a capacitance element are added to the internal power supply 103 is shown as an example. However, the present invention is not limited to this, and other means for suppressing voltage fluctuation, a clamp circuit, and protection The same effect can be realized by using a circuit or the like having a similar function for suppressing voltage fluctuation noise and current backflow.
　また、クランプ回路を用いた場合であれば、内部電源１０３の電圧が外部電源１０２の電圧を上回ってしまった場合でも、内部電源１０３から外部電源１０２へと電流が逆流してしまうことを防止するという効果も実現できる。 Further, in the case where a clamp circuit is used, even if the voltage of the internal power supply 103 exceeds the voltage of the external power supply 102, the current is prevented from flowing back from the internal power supply 103 to the external power supply 102. This effect can also be realized.
　また、本実施形態では、内部昇圧電源ブロック３００側に電圧変動抑制手段を追加する例を示したが、これに限定するものではなく、内部降圧電源ブロック１０１側に電圧変動抑制手段やクランプ回路、保護回路等を搭載しても同様の効果を実現できる。 In the present embodiment, an example in which voltage fluctuation suppression means is added to the internal boost power supply block 300 side is shown, but the present invention is not limited to this, and voltage fluctuation suppression means, a clamp circuit, The same effect can be realized even if a protection circuit or the like is installed.
　《第４の実施形態》
　図４は、本発明の第４の実施形態による内部電源回路を備えた半導体集積回路の概略構成を示す図である。以下、内部電源回路を備えた半導体集積回路の代表的な内部電源生成の動作における本発明の実施の形態を説明する。 << Fourth Embodiment >>
FIG. 4 is a diagram showing a schematic configuration of a semiconductor integrated circuit including an internal power supply circuit according to the fourth embodiment of the present invention. Embodiments of the present invention in a typical internal power generation operation of a semiconductor integrated circuit including an internal power supply circuit will be described below.
　なお、図４の構成要素のうちで図１に記載している構成要素と同じ構成を持つものに関しては同じ符号を付与している。 In addition, the same code | symbol is provided about the component which has the same structure as the component described in FIG. 1 among the components of FIG.
　本発明の第１の実施形態での構成に対して、本実施形態では、内部降圧電源ブロック４００の中で、降圧用ＰＭＯＳトランジスタ１０８の代わりに降圧用ＮＭＯＳ（N-type Metal Oxide Semiconductor）トランジスタ４０１と、第１の検知信号１０７の信号論理を反転するためのインバータ回路である第３の論理回路４０２と、第３の論理回路４０２から出力される第４の検知信号４０３とから構成されている。内部昇圧電源ブロック１１２の動作は本発明の第１の実施形態と同様である。 In contrast to the configuration of the first embodiment of the present invention, in this embodiment, in the internal step-down power supply block 400, a step-down NMOS (N-type Metal Oxide Semiconductor) transistor 401 is used instead of the step-down PMOS transistor 108. And a third logic circuit 402 which is an inverter circuit for inverting the signal logic of the first detection signal 107, and a fourth detection signal 403 output from the third logic circuit 402. . The operation of the internal boost power supply block 112 is the same as that of the first embodiment of the present invention.
　内部降圧電源ブロック４００の動作に関しては、内部電源１０３の電圧が所望の電圧である２．６Ｖよりも下がって外部電源１０２からの電流供給が必要となった際に、第１のアンプ回路１０６からＬレベルの第１の検知信号１０７が出力される。この第１の検知信号１０７は、インバータ回路である第３の論理回路４０２を介して反転されたＨレベルの信号となって第４の検知信号４０３として降圧用ＮＭＯＳトランジスタ４０１のゲートに入力される。降圧用ＮＭＯＳトランジスタ４０１は、ゲートにＨレベルが印加されることによってオンし、外部電源１０２から内部電源１０３へと電流を供給し、内部電源１０３を２．６Ｖで維持するよう動作する。 Regarding the operation of the internal step-down power supply block 400, when the voltage of the internal power supply 103 falls below the desired voltage of 2.6 V and the current supply from the external power supply 102 becomes necessary, the first amplifier circuit 106 An L level first detection signal 107 is output. The first detection signal 107 becomes an inverted H level signal via the third logic circuit 402 that is an inverter circuit, and is input to the gate of the step-down NMOS transistor 401 as the fourth detection signal 403. . The step-down NMOS transistor 401 is turned on when an H level is applied to the gate, supplies current from the external power supply 102 to the internal power supply 103, and operates to maintain the internal power supply 103 at 2.6V.
　以上のような構成によれば、本発明の第１の実施形態と同様に、外部電源１０２の電圧が低下した場合でも、内部電源１０３を安定して供給することが可能となり、かつ内部電源１０３の電圧が外部電源１０２の電圧を上回ってしまった場合でも、降圧用のトランジスタをＮＭＯＳトランジスタ４０１で構成しているために電流の逆流を防止できる。 According to the above configuration, as in the first embodiment of the present invention, even when the voltage of the external power supply 102 decreases, the internal power supply 103 can be stably supplied, and the internal power supply 103 can be supplied. Even if the voltage exceeds the voltage of the external power supply 102, the back-down current can be prevented because the step-down transistor is composed of the NMOS transistor 401.
　これにより、本発明の第１の実施形態の構成に対して降圧用のトランジスタの構成を変更するだけで回路面積の増大なく、昇圧、降圧動作で生成する内部電源１０３をより一層安定した電源として供給し、電流の逆流も防止することが可能となる。 As a result, the internal power supply 103 generated by the step-up / step-down operation is made more stable without changing the circuit area simply by changing the step-down transistor configuration with respect to the configuration of the first embodiment of the present invention. It is possible to prevent reverse current flow by supplying.
　なお、本発明の趣旨を逸脱しない範囲で上記第１～第４の実施形態における各構成要素を任意に組み合わせてもよい。 It should be noted that the components in the first to fourth embodiments may be arbitrarily combined without departing from the spirit of the present invention.
　本発明に係る半導体集積回路は、ＳｏＣの電源仕様の低電圧化や電源電圧変動による外部電源電圧の低電圧化に対する内部電源生成の安定化、動作電圧範囲の改善、回路面積の削減に効果を有し、特に内部電源回路を備えた半導体集積回路として有用である。 The semiconductor integrated circuit according to the present invention is effective in stabilizing the generation of internal power, improving the operating voltage range, and reducing the circuit area with respect to lowering the SoC power supply specifications and lowering the external power supply voltage due to power supply voltage fluctuations. In particular, it is useful as a semiconductor integrated circuit having an internal power supply circuit.
１０１　内部降圧電源ブロック
１０２　外部電源
１０３　内部電源
１０４　リファレンス生成回路
１０５　リファレンス電圧
１０６　第１のアンプ回路
１０７　第１の検知信号
１０８　降圧用ＰＭＯＳトランジスタ
１０９　第１の抵抗素子
１１０　第２の抵抗素子
１１１　内部電源フィードバック電圧
１１２　内部昇圧電源ブロック
１１３　ポンプ回路
１１４　オシレータ回路
１１５　第３の抵抗素子
１１６　第４の抵抗素子
１１７　外部電源フィードバック電圧
１１８　第２のアンプ回路
１１９　第２の検知信号
１２０　第１の論理回路
１２１　第３の検知信号
１２２　第２の論理回路
１２３　第１の論理信号
１２４　第２の論理信号
２００　内部降圧電源ブロック
２０１　内部昇圧電源ブロック
２０２　第１のスイッチ
２０３　第２のスイッチ
２０４　内部昇圧電源
２０５　第１の論理回路
２０６　第３の検知信号
２０７　第２の論理回路
２０８　第１の論理信号
３００　内部昇圧電源ブロック
３０１　第５の抵抗素子
３０２　容量素子
４００　内部降圧電源ブロック
４０１　降圧用ＮＭＯＳトランジスタ
４０２　第３の論理回路
４０３　第４の検知信号 101 Internal power supply block 102 External power supply 103 Internal power supply 104 Reference generation circuit 105 Reference voltage 106 First amplifier circuit 107 First detection signal 108 Step-down PMOS transistor 109 First resistance element 110 Second resistance element 111 Internal power supply Feedback voltage 112 Internal boost power supply block 113 Pump circuit 114 Oscillator circuit 115 Third resistance element 116 Fourth resistance element 117 External power supply feedback voltage 118 Second amplifier circuit 119 Second detection signal 120 First logic circuit 121 3 detection signal 122 second logic circuit 123 first logic signal 124 second logic signal 200 internal step-down power supply block 201 internal boost power supply block 202 first switch 203 second switch 204 internal boost power supply 205 first Logic circuit 206 Third detection signal 207 Second logic circuit 208 First logic signal 300 Internal boost power supply block 301 Fifth resistance element 302 Capacitance element 400 Internal step-down power supply block 401 Step-down NMOS transistor 402 Third logic circuit 403 Fourth detection signal

Claims (19)

  1. 　外部電源をもとに降圧動作を実施する内部降圧電源ブロックと、
    　前記外部電源をもとに昇圧動作を実施する内部昇圧電源ブロックとを備え、
    　前記外部電源が第１の電圧範囲では、前記内部降圧電源ブロックのみを使用して所望の電圧の内部電源を生成し、前記外部電源が前記第１の電圧範囲より低い第２の電圧範囲では、前記内部降圧電源ブロックに加えて又は前記内部降圧電源ブロックに代えて前記内部昇圧電源ブロックを使用して前記所望の電圧の内部電源を生成することを特徴とする半導体集積回路。     An internal step-down power supply block that performs step-down operation based on an external power supply;
    An internal boost power supply block that performs a boost operation based on the external power supply,
    When the external power supply is in the first voltage range, the internal power supply of a desired voltage is generated using only the internal step-down power supply block, and in the second voltage range where the external power supply is lower than the first voltage range, A semiconductor integrated circuit characterized in that an internal power supply of the desired voltage is generated using the internal boost power supply block in addition to or instead of the internal buck power supply block.
  2. 　請求項１記載の半導体集積回路において、
    　前記内部昇圧電源ブロックは、前記外部電源の電圧値によって動作するかどうかを決定することを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 1,
    The semiconductor integrated circuit according to claim 1, wherein the internal boost power supply block determines whether or not to operate according to a voltage value of the external power supply.
  3. 　請求項１記載の半導体集積回路において、
    　前記内部降圧電源ブロックは、前記外部電源の電圧値によって動作するかどうかを決定することを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 1,
    The semiconductor integrated circuit according to claim 1, wherein the internal step-down power supply block determines whether or not to operate according to a voltage value of the external power supply.
  4. 　請求項１記載の半導体集積回路において、
    　所定の電圧を生成するリファレンス生成回路を更に備え、
    　前記リファレンス生成回路で生成されるリファレンス電圧が、前記内部降圧電源ブロック及び前記内部昇圧電源ブロックに入力されることを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 1,
    A reference generation circuit for generating a predetermined voltage;
    A semiconductor integrated circuit, wherein a reference voltage generated by the reference generation circuit is input to the internal step-down power supply block and the internal step-up power supply block.
  5. 　請求項４記載の半導体集積回路において、
    　前記リファレンス生成回路内で、前記リファレンス電圧は所望の値に可変とすることを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 4, wherein
    A semiconductor integrated circuit characterized in that the reference voltage is variable to a desired value in the reference generation circuit.
  6. 　請求項４記載の半導体集積回路において、
    　前記内部降圧電源ブロックは、
    　前記内部電源の電圧を第１のフィードバック電圧に変換する第１の電圧変換回路と、
    　前記第１のフィードバック電圧と前記リファレンス電圧とを入力して第１の検知信号を出力する第１の内部電源制御回路とを有することを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 4, wherein
    The internal step-down power supply block is:
    A first voltage conversion circuit for converting the voltage of the internal power source into a first feedback voltage;
    A semiconductor integrated circuit comprising: a first internal power supply control circuit that inputs the first feedback voltage and the reference voltage and outputs a first detection signal.
  7. 　請求項６記載の半導体集積回路において、
    　前記リファレンス電圧及び前記第１のフィードバック電圧は、前記内部電源の電圧よりも低いことを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 6.
    The semiconductor integrated circuit, wherein the reference voltage and the first feedback voltage are lower than a voltage of the internal power supply.
  8. 　請求項６記載の半導体集積回路において、
    　前記内部降圧電源ブロックは、前記第１の検知信号を入力して前記外部電源から前記内部電源を生成する第１の内部電源生成回路を更に有し、前記第１の内部電源生成回路はＰＭＯＳトランジスタで構成されたことを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 6.
    The internal step-down power supply block further includes a first internal power supply generation circuit that receives the first detection signal and generates the internal power supply from the external power supply, and the first internal power supply generation circuit includes a PMOS transistor. A semiconductor integrated circuit comprising:
  9. 　請求項６記載の半導体集積回路において、
    　前記内部昇圧電源ブロックは、
    　前記外部電源の電圧を第２のフィードバック電圧に変換する第２の電圧変換回路と、
    　前記第２のフィードバック電圧と前記リファレンス電圧とを入力して第２の検知信号を出力する第２の内部電源制御回路とを有することを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 6.
    The internal boost power supply block is
    A second voltage conversion circuit for converting the voltage of the external power source into a second feedback voltage;
    A semiconductor integrated circuit comprising: a second internal power supply control circuit that inputs the second feedback voltage and the reference voltage and outputs a second detection signal.
  10. 　請求項９記載の半導体集積回路において、
    　前記第２のフィードバック電圧は、前記外部電源及び前記内部電源の電圧よりも低いことを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 9, wherein
    The semiconductor integrated circuit, wherein the second feedback voltage is lower than voltages of the external power supply and the internal power supply.
  11. 　請求項９記載の半導体集積回路において、
    　前記内部昇圧電源ブロックは、
    　前記第１の検知信号を受けて第３の検知信号を出力する第１の論理回路と、
    　前記第２の検知信号と前記第３の検知信号とを受けて第１の論理信号を出力する第２の論理回路とを更に有することを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 9, wherein
    The internal boost power supply block is
    A first logic circuit that receives the first detection signal and outputs a third detection signal;
    A semiconductor integrated circuit further comprising: a second logic circuit that receives the second detection signal and the third detection signal and outputs a first logic signal.
  12. 　請求項１１記載の半導体集積回路において、
    　前記内部昇圧電源ブロックは、前記第１の論理信号を受けて前記内部電源を出力する第２の内部電源生成回路を更に有することを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 11, wherein
    The internal boosted power supply block further includes a second internal power supply generation circuit that receives the first logic signal and outputs the internal power supply.
  13. 　請求項１記載の半導体集積回路において、
    　前記内部電源の電源配線にノイズ除去回路又は保護回路を更に備えたことを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 1,
    A semiconductor integrated circuit, further comprising a noise removal circuit or a protection circuit in a power supply wiring of the internal power supply.
  14. 　請求項１３記載の半導体集積回路において、
    　前記ノイズ除去回路又は前記保護回路は、前記内部昇圧電源ブロック内に配置されたことを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 13.
    The semiconductor integrated circuit, wherein the noise removal circuit or the protection circuit is disposed in the internal boost power supply block.
  15. 　請求項１３記載の半導体集積回路において、
    　前記ノイズ除去回路又は前記保護回路は、前記内部降圧電源ブロック内に配置されたことを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 13.
    The semiconductor integrated circuit, wherein the noise removal circuit or the protection circuit is disposed in the internal step-down power supply block.
  16. 　請求項６記載の半導体集積回路において、
    　前記内部降圧電源ブロックは、前記第１の検知信号を入力して前記外部電源から前記内部電源を生成する第１の内部電源生成回路を更に有し、前記第１の内部電源生成回路はＮＭＯＳトランジスタで構成されたことを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 6.
    The internal step-down power supply block further includes a first internal power supply generation circuit that receives the first detection signal and generates the internal power supply from the external power supply, and the first internal power supply generation circuit includes an NMOS transistor. A semiconductor integrated circuit comprising:
  17. 　選択された電源をもとに降圧動作を実施する内部降圧電源ブロックと、
    　外部電源をもとに内部昇圧電源を生成する内部昇圧電源ブロックとを備え、
    　前記外部電源が第１の電圧範囲では、前記内部降圧電源ブロックが前記外部電源から所望の電圧の内部電源を生成し、前記外部電源が前記第１の電圧範囲より低い第２の電圧範囲では、前記内部昇圧電源ブロックが生成した前記内部昇圧電源から前記内部降圧電源ブロックが前記所望の電圧の内部電源を生成することを特徴とする半導体集積回路。     An internal step-down power supply block that performs step-down operation based on the selected power supply;
    An internal boost power supply block that generates an internal boost power supply based on the external power supply,
    When the external power supply is in a first voltage range, the internal step-down power supply block generates an internal power supply of a desired voltage from the external power supply, and in a second voltage range where the external power supply is lower than the first voltage range, A semiconductor integrated circuit, wherein the internal step-down power supply block generates an internal power supply of the desired voltage from the internal boosted power supply generated by the internal step-up power supply block.
  18. 　請求項１７記載の半導体集積回路において、
    　前記内部昇圧電源ブロックは、前記外部電源の電圧値によって動作するかどうかを決定することを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 17.
    The semiconductor integrated circuit according to claim 1, wherein the internal boost power supply block determines whether or not to operate according to a voltage value of the external power supply.
  19. 　請求項１７記載の半導体集積回路において、
    　前記内部降圧電源ブロックが前記外部電源又は前記内部昇圧電源のいずれをもとに前記内部電源を生成するかを、前記外部電源の電圧値に応じて生成される検知信号によって、前記外部電源に接続された第１のスイッチ、又は前記内部昇圧電源に接続された第２のスイッチのいずれかを接続することで制御することを特徴とする半導体集積回路。     The semiconductor integrated circuit according to claim 17.
    Whether the internal step-down power supply block generates the internal power supply based on the external power supply or the internal boosted power supply is connected to the external power supply by a detection signal generated according to the voltage value of the external power supply The semiconductor integrated circuit is controlled by connecting one of the first switch and the second switch connected to the internal boost power supply.
PCT/JP2011/000773 2010-03-26 2011-02-10 Semiconductor integrated circuit WO2011118119A1 (en)

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Citations (6)

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JPH05234390A (en) * 1992-02-24 1993-09-10 Fujitsu Ltd Semiconductor integrated circuit device
JPH0644775A (en) * 1992-07-23 1994-02-18 Toshiba Corp Semiconductor integrated circuit
JPH0778470A (en) * 1993-09-10 1995-03-20 Fujitsu Ltd Semiconductor storage
JP2002100974A (en) * 2000-09-21 2002-04-05 Toshiba Corp Semiconductor device
JP2004071095A (en) * 2002-08-08 2004-03-04 Renesas Technology Corp Semiconductor memory
JP2007059924A (en) * 2006-09-22 2007-03-08 Mitsubishi Electric Corp Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05234390A (en) * 1992-02-24 1993-09-10 Fujitsu Ltd Semiconductor integrated circuit device
JPH0644775A (en) * 1992-07-23 1994-02-18 Toshiba Corp Semiconductor integrated circuit
JPH0778470A (en) * 1993-09-10 1995-03-20 Fujitsu Ltd Semiconductor storage
JP2002100974A (en) * 2000-09-21 2002-04-05 Toshiba Corp Semiconductor device
JP2004071095A (en) * 2002-08-08 2004-03-04 Renesas Technology Corp Semiconductor memory
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