KR20010029653A - Driving method of a display device and a driving circuit - Google Patents

Abstract

PURPOSE: To provide a method and a circuit for driving a display device realizing low power consumption. CONSTITUTION: Plural gradation signals GR0-GR15 that at least a part GR1-GR14 of the gradation signals answering to respective gradation levels become fold-back symmetry around a horizontal synchronizing signal are awaited, and the gradation signals according to display data are selected from them to generate a drive voltage.

Description

Display method driving method and driving circuit {DRIVING METHOD OF A DISPLAY DEVICE AND A DRIVING CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a driving circuit of a display device, and more particularly to a driving method and a driving circuit of a display device for performing gradation display by pixels arranged in a matrix.

As a representative example of the matrix display device, a liquid crystal display device may be mentioned. Conventionally, a liquid crystal display device that performs gradation display (also referred to as "medium color display") by so-called pulse width modulation is known, and Japanese Patent Application Laid-open No. 96-286171 (published date: November 1, 1996) is known. This liquid crystal display device is disclosed.

Next, with reference to FIG. 10, the liquid crystal display 70 which performs such gradation display is demonstrated. The liquid crystal display device 70 includes a liquid crystal panel 71 displaying an image, a segment side driving circuit 72 outputting a driving voltage to each segment electrode X1 to Xm of the liquid crystal panel 71; Common-side driving circuit 73 for outputting a driving voltage to common electrodes (scanning electrodes) Y1 to Yn, and a power supply circuit for generating and supplying various driving voltages V0 to V5 applied to the liquid crystal panel 71. ) And a controller 75 for transmitting various control signals for controlling the segment side driving circuit 72 and the common side driving circuit 73. In addition, in FIG. 10, the power supply of each circuit block is abbreviate | omitted.

The liquid crystal panel 71 is formed by inserting a liquid crystal between a pair of substrates. In the case of a transmissive panel, both substrates are made light-transmissive, and strip-shaped segment electrodes X1 to Xm are provided in parallel with each other on the insulating substrate, and strip-shaped common electrodes Y1 to parallel with each other on the other insulating substrate. Yn is installed. Moreover, the liquid crystal aligning film which covers the electrodes X1-Xm * Y1-Yn provided in each board | substrate is provided, respectively.

The liquid crystal panel 71 executes display due to a combination of a plurality of (m × n) pixels, with the segment where the segment electrodes X1 to Xm and the scan electrodes Y1 to Yn intersect as pixels.

From the controller 75 to the segment side drive circuit 72. Display data 76 such as a digitized image, data latch clock 77 for injecting the display data 76 into the segment side driving circuit 72, the horizontal synchronizing signal LP, the AC signal 79 and the gray scale The signal clock 80 is input. On the other hand, the vertical synchronizing signal 81 for recognizing the head of one screen is input to the common side driving circuit 73 from the controller 75 at the same time as the horizontal synchronizing signal LP and the AC signal 79.

Six kinds of power supply voltages V0 to V5 are output from the power supply circuit 74. The power supply voltages V0, V2, V3, and V5 are supplied to the segment side driving circuit 72, and the power supply voltages V0, V1, V4, and V5 are large. It is supplied to the driven side driver circuit 73, respectively.

As shown in FIG. 11, the segment side driving circuit 72 includes a shift register circuit 91, a data latch circuit 92, a line latch circuit 93, a gray level signal generating circuit 94, and a gray level decoder 95. ), And a level shifter circuit 96 and a liquid crystal drive output circuit 97. The segment-side driving circuit 72 is supplied with power supply voltages Vcc and GND, which are power sources of the segment-side driving circuit 72, and supplied to the level shifter circuit 96 and the liquid crystal drive output circuit 97. The power supply voltage VDD is input.

Next, the driving operation of the liquid crystal display device 70 will be described with reference to the timing charts of FIGS. 12 and 13.

12 and 13, in addition to the main control signal, in addition to the main control signals, the voltage difference between the gray level signals T0 to T15, the voltage waveform applied to the segment electrode Xj, the voltage waveform applied to the common electrode Yi, and the voltage applied to the positive electrodes Xj · Yi. That is, the voltage applied to the pixels Xj and Yi of the liquid crystal panel 71 is shown. In FIG. 12, the low frequency part centering on the vertical synchronous signal 81 is shown, and the high frequency part centering on the horizontal synchronous signal LP is shown in FIG.

The segment side drive circuit 72 is input with digitalized display data 76 for one horizontal period and a data latch clock 77 for one horizontal period. Here, the display data 76 has a 4-bit configuration in order to describe the 16 gray scale display. The display data 76 is transferred into the shift register circuit 91 by the data latch clock 77 and sequentially latched at a predetermined address of the data latch circuit 92 by the previous data latch clock 77. . When the display data 76 for one horizontal period is accumulated in the data latch circuit 92, the transfer of the shift register circuit 91 is stopped by the horizontal synchronization signal LP, and the accumulated display data 76 is stored in the data. It is latched from the latch circuit 92 to the line latch circuit 93. The output of the line latch circuit 93 holds its latched value until the next horizontal synchronous signal LP is input.

The latched display data 76 is input to the gradation decoder circuit 95. In the gray scale decoder circuit 95, pulses T0 to T15 having 16 kinds of pulse widths necessary for displaying 16 gray scales from the gray scale signal generating circuit 94 are input. When the horizontal synchronous signal LP is input, the gradation signal generating circuit 94 counts the gradation signal clock 80 starting with the horizontal synchronous signal LP, and then, within one horizontal period, T0, T1, T2, ... Generates 16 kinds of pulses, T14 and T15. Here, pulse T0 is set to GND level, and pulse T15 is set to Vcc level.

The gradation decoder circuit 95 converts one pulse signal from 16 kinds of pulses T0 to T15 according to the input 4-bit display data 76, and 4-bit display data (0000) -T0, (0001) = T1. , (0010) = T2, ... (1110) -T14, (1111) -T15, and this selected pulse signal is output to the level shifter circuit (96).

After the signal level is converted by the level shifter circuit 96, in the liquid crystal drive output circuit 97 composed of an analog switch such as a transmission gate, for example, a pulse signal and an alteration signal 79 based on the display data 76 are used. According to the combination, one voltage is selected from four level values V0, V2, V3, and V5 for each of the segment electrodes X1 to Xm, and each sag of the liquid crystal panel 71 is synchronized with the horizontal synchronizing signal LP. It is output to the fragment electrodes X1 to Xm.

The AC signal 79 inverts the applied voltage so that a DC component does not accumulate in the liquid crystal panel 71 and impairs reliability. In the simple matrix liquid crystal panel, the AC signal is inverted every frame.

On the other hand, although not shown, the common side driver circuit 73 includes a shift resist circuit, a level shifter circuit, and a liquid crystal drive output circuit. When the vertical synchronous signal 81 is input, the vertical synchronous signal 81 is supplied. The horizontal synchronization signal LP is transmitted as a clock in the shift register circuit, and output from each stage of the shift register circuit to generate a signal corresponding to the scan signal.

After the signal voltage level in the shift register circuit is converted by the level shifter circuit, four level values (V0, V1, V4) for each common electrode Y1 to Yn in accordance with the combination of the signal and the alteration signal 79 are obtained. , One voltage is selected from V5) and is output to the common electrodes Y1 to Yn of the liquid crystal panel 71.

The display of each pixel of the liquid crystal panel 71 is determined by the effective value of the voltage difference between the segment electrodes X1 to X m and the common electrodes Y1 to Yn in a period (that is, one frame period) necessary for displaying one screen. . The effective value applied to each of these pixels is changed by pulse width modulation to perform gradation display.

In the liquid crystal display 70, from displaying one screen by scanning the common electrodes Y1 to Yn, as shown in Fig. 12, at least one horizontal period in one vertical period (one frame) is up to H1 to Hn. .

12 shows the output waveform of the voltage Vxj output to the segment electrode Xj. Here, the output j of the gradation decoder circuit 95 corresponding to the segment electrode Xj is in accordance with the display data 76, the pulse width T3 in the horizontal period Hi, the pulse width T8 in the next horizontal period Hi + 1, and the next. In the horizontal period Hi + 2, the pulse width is T14.

In the next frame after the inverted signal 79 is inverted, the output j of the gradation decoder circuit 95 depends on the display data 76, and the pulse width T3 in the horizontal period Hi and the pulse width in the next horizontal period Hi + 1. T10.

On the other hand, the common output voltage VY1 shown in FIG. 12 is a voltage output to the common electrode Yi. As shown in the figure, the common electrode Yi is selected and scanned in the horizontal period Hi. The common output voltage is output to the common electrode Yi + 1 such that the common electrode Yi + 1 is selected and scanned in the next horizontal period Hi + 1, and the common electrodes Y1 to Yn are subsequently scanned sequentially.

As a result, the voltage waveforms V (xJ, Yl) are applied to the pixels Xj and Yi of the liquid crystal panel as the difference between the output voltage to the segment electrode Xj and the output voltage to the common electrode Yi. The gray scale display is performed by changing the effective value applied to each pixel by pulse width modulation (for example, T3 and T8).

In recent years, the liquid crystal display device mounted in the portable device is changed to a large screen as more display capability is requested, and thus power consumption is increasing.

On the other hand, there is also a demand for miniaturization and weight reduction of portable devices, and the miniaturization of power sources has increased the burden on batteries, and therefore, attempts to further reduce power consumption of liquid crystal displays are urgently required.

However, in the liquid crystal display device 70 described above, a problem arises in that it is difficult to reduce power consumption.

In the liquid crystal display device 70, as shown in Fig. 12, the gradation signal by the pulse width modulation method is output at the same timing in synchronization with the horizontal synchronizing signal LP. In addition, a certain voltage is applied to each pixel of the liquid crystal panel 71 not only for the pixel selected by the scanning signal but also for the pixel in the non-selected state. In short, when the common electrode Yi is selected, a certain voltage is applied not only to the pixel connected to the common electrode Yi but also to the pixel connected to the common electrode other than the common electrode Yi.

In Fig. 12, the voltages W1 to W8 applied to the pixels Xj and Yi at the time of non-selection are shown. In this manner, although the voltage is low, the voltages W1 to W8 corresponding to the gradation signal are output to the pixels at the time of non-selection in every horizontal period. Therefore, even in the non-selected pixel, the charge and discharge are repeated in the capacitance between the segment electrode and the common electrode at each time when any one of the common electrodes Y1 to Yn is selected.

The current consumed by charging and discharging to the non-selected pixels is proportional to fCV (N-1). Where f is the number of charges and discharges, C is the pixel capacitance at one scan electrode, V is the voltage applied to the pixel, N is the number of scan electrodes, and N-1 is the number of unselected scan electrodes. As the above liquid crystal display device 70, the gradation signal shown in Fig. 13 is used, and the number of charge / discharge cycles in one horizontal period is one time each (two times in total).

The voltage applied to the pixel in the non-selected state is not large compared with the pixel in the selected state, but in the case of a large screen, the capacitance of the pixel in the non-selected state becomes larger compared with the capacitance of the pixel in the selected state, As the number of scanning lines increases, the N value also increases. Therefore, in order to further reduce the power consumption, the power consumption consumed by the pixels of the non-selection unit cannot be ignored.

SUMMARY OF THE INVENTION In view of the above problems, the present invention aims to reduce the power consumed in a pixel in an unselected state in a driving method or a driving circuit of a display device.

The driving method of the display device according to the present invention is, in order to achieve the above object,

For each horizontal period of the horizontal synchronization signal, a plurality of gray level signals varying in accordance with the gray level of the display data are selected, a driving signal is generated in accordance with the selected gray level signal, and this is applied to a plurality of pixels arranged in a matrix, As a driving method of a display device for displaying, the gradation signal is a driving method of a display device which maintains its level when shifting to an adjacent horizontal period.

According to the above method, in each horizontal period of the horizontal synchronization signal, a gradation signal that changes in accordance with the gradation level of the display data is selected. According to the selected gradation signal, a driving signal for driving the pixels on the matrix is generated.

When this drive signal drives a pixel on the matrix, the pixel performs gradation display in accordance with the gradation level of the display data.

Conventionally, the gradation signal is output in pulse form in synchronization with the horizontal synchronizing signal. As a result, in each horizontal period, the gradation signal exhibits two level changes in total in the rising and falling directions. This means the following. That is, when displaying that the pixels are formed in a matrix, even if the level is low even for the pixels in the non-selected state, since a certain driving signal is applied, even in the non-selected state, the pixels are charged in each horizontal period. And discharge are performed once each. This makes it impossible to ignore power consumption consumed by the pixels in the non-selected state when the display device is a large screen, making it difficult to further reduce the power consumption.

Thus, in the present invention, the gray level signal is maintained at the level of the gray level signal when shifting to an adjacent horizontal period. In other words, if the first horizontal period and the second horizontal period are in contact with this order, the level of the gradation signal in the first horizontal period is maintained even if the transition to the second horizontal period occurs. From this, in each horizontal period, since the gradation signal shows only the level change of either rising or falling, the number of charge / discharge cycles of the pixels in the non-selected state is also only one time (one charge or one discharge only). Either one time). As a result, the power consumption consumed in the non-selected pixels can be reduced by about half.

By achieving the low power consumption as described above, when the portable application is made, the large screen of the display device becomes possible, and the burden of the portable power source is reduced, so that the long-term use of the device and the miniaturization of the power source can be reliably realized.

The gray level signal preferably has a waveform that is symmetrical with respect to the time axis about the horizontal synchronization signal. In addition, it is preferable to apply the display device to a liquid crystal display device, whereby a lower power consumption of the liquid crystal display device can be achieved, which is more suitable for a portable device.

Still other objects, features, and advantages of the present invention will be fully understood from the following description. Further benefits of the present invention will become apparent from the following description with reference to the accompanying drawings.

1 is a block diagram schematically showing a configuration of a liquid crystal display device to which a driving method and a driving circuit according to Embodiment 1 of the present invention are applied;

2 is a block diagram schematically showing a configuration of a segment side driving circuit in the liquid crystal display device;

3 is a timing chart showing output waveforms of a common side driver circuit and a segment side driver circuit in the liquid crystal display device, a voltage waveform applied to a pixel of a liquid crystal panel, and the like;

4 is a timing chart showing output signals and the like of the 1/2 frequency division circuit and the gradation signal generation circuit in the segment side driving circuit;

5 is a circuit diagram showing the configuration of the 1/2 division circuit and the gradation signal generating circuit;

6 is a circuit diagram showing the configuration of a gradation decoder circuit in the segment side driving circuit;

7 is a block diagram schematically illustrating a configuration of a liquid crystal display device to which a driving method and a driving circuit are applied according to another embodiment of the present invention;

8 is a block diagram schematically showing a configuration of a segment side driving circuit in the liquid crystal display device;

9 is a timing chart showing output waveforms of the common side driver circuit and the segment side driving circuit in the liquid crystal display device, the voltage waveform applied to the pixels of the liquid crystal panel, and the like;

10 is a block diagram schematically showing a configuration of a conventional liquid crystal display device;

11 is a block diagram schematically showing the configuration of a segment side driving circuit in the conventional liquid crystal display device;

12 is a timing chart showing output waveforms of the common side driver circuit and the segment side driving circuit in the conventional liquid crystal display device, voltage waveforms applied to the pixels of the liquid crystal panel, and the like;

Fig. 13 is a timing chart showing gradation signal pulses and the like output from the gradation signal generation circuit in the conventional segment side driving circuit.

A first embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.

FIG. 1 is a block diagram schematically showing the configuration of a liquid crystal display device 20 in which a driving circuit according to the present embodiment is used. The liquid crystal display device 20 includes a liquid crystal panel 1 displaying an image, and Segment side drive circuit (segment driver) 2 which outputs drive voltage to segment electrodes X1 to Xm of liquid crystal panel (display panel) 1, and common electrode (scan electrode) Y1 of liquid crystal panel 1; A common side driving circuit (common driver) 3 for outputting a driving voltage to ˜Yn and various voltages V0 to V5 are generated, and these are supplied to the segment side driving circuit 2 and the common side driving circuit 3. And a controller 5 for transmitting various control signals for controlling the power supply circuit 4, the segment side driving circuit 2, and the common side driving circuit 3; 1, the power supply of each circuit block is omitted.

From the controller 5 to the segment side driving circuit 2, display data (data signal) 6 such as a digitalized image, and data for injecting the display data 6 into the segment side driving circuit 2 are provided. The latch clock 7, the horizontal synchronization signal LP, the AC signal 9, the gradation signal clock 10, and the reset signal RST are input. On the other hand, the horizontal synchronizing signal LP, the AC signal 9, and the vertical synchronizing signal 19 for recognizing the head of one screen are input from the controller 5 to the common side driving circuit 3.

The vertical synchronization signal 19 is also input to the segment side driving circuit 2, and in this configuration, the vertical synchronization signal 19 is input to the segment side driving circuit 2 as described later. Subsequently, the horizontal synchronizing signal LP is also input.

The six kinds of power supply voltages V0 to V5 are output from the power supply circuit 4, and the power supply voltages V0, V2, V3, and V5 are supplied to the segment side driving circuit 2, and the power supply voltages V0, V1, V4, and V5 are large. It is supplied to the driven side drive circuit 3, respectively.

The liquid crystal panel 1 includes a pair of substrates, a plurality of segment electrodes (first electrodes) X1 to Xm parallel to each other provided on one substrate, and a plurality of common parallel to each other provided on the substrate on the other side. Electrodes (second electrode) Y1 to Yn cross each other, and each intersection constitutes a pixel.

The segment side driving circuit 2 displays 16 gray scales by pulse width modulation, as shown in Fig. 2, the shift register circuit 11, the data latch circuit 12, and the line latch circuit 13 ), A 1/2 division circuit 14, a gradation signal generating circuit 15, a gradation decoder circuit (gradation signal selection means) 16, a level shifter circuit 17, and a liquid crystal drive output circuit 18, have.

As the segment side driving circuit 2, a vertical synchronization signal 19 for recognizing the head of the screen of the liquid crystal panel 1 is input, and thereafter, scanning the common electrodes Y1 to Yn of the liquid crystal panel 1 in sequence When the horizontal synchronizing signal LP, which is also a synchronizing signal, is input, digitalized display data 6 (4 bits x m) for one horizontal period and a data latch clock 7 for one horizontal period are input. The display data 6 is transferred into the shift register circuit 11 in synchronization with the data latch clock 7 and latched at a predetermined address of the data latch circuit 12.

When the display data 6 for one horizontal period is accumulated in the data latch circuit 12, the display data 6 latched in the data latch circuit 12 is transferred to the line latch circuit 13 by the horizontal synchronization signal LP. Latched, the value is held during the next one horizontal period. Thereafter, the display data 6 latched in the line latch circuit 13 is input to the gradation decoder circuit 16. In the subsequent horizontal period, the same operation is performed in each circuit.

As described later, the gradation decoder circuit 16 receives the gradation signals GR0 to GR15 (see Fig. 4) having 16 kinds of pulse widths necessary for displaying 16 gradations from the gradation signal generating circuit 15, for each line. According to the value of the 4-bit display data 6, one gradation signal is selected and outputted to the level shifter circuit 17. [0033] FIG.

In order to generate the gray scale signals GR1 to GR14, the segment side driving circuit 2 divides the signals divided in half in synchronization with the falling of the horizontal synchronous signal LP in the 1/2 frequency division circuit 14 as described below. Generate DQ (see FIG. 4). As described later, the gradation signal generating circuit 15 horizontally pulses a pulse as a gradation signal generated by counting the gradation signal clock 10 based on the signal DQ from the 1/2 division circuit 14. A pulse laterally symmetric is outputted against the falling of the synchronization signal LP. However, the gray scale signals GR0 and GR15 for white display and black display are excluded, and so-called gray tone signals GR1 to GR14, which are so-called intermediate tone display pulses, are generated as described above.

The gradation signal input from the gradation decoder circuit 16 to the level shifter circuit 17 is input to the liquid crystal drive output circuit 18 composed of analog switches such as a transmission gate after the signal level is converted. As the liquid crystal drive output circuit 18, four levels (V0, V2, V3, V5) for each segment electrode X1 to Xm in accordance with the combination of the gradation signal and the AC signal 9 based on the display data 6 ), An appropriate voltage is selected and output to each segment electrode X1 to Xm of the liquid crystal panel 1 in synchronization with the horizontal synchronizing signal LP.

On the other hand, although not shown, the common side driver circuit 3 includes a common side shift register circuit, a common side level shifter circuit, and a common side liquid crystal drive output circuit. When the vertical synchronizing signal 19 is input to the common side driving circuit 3, the vertical synchronizing signal 19 is transferred into the common side shift register circuit using the horizontal synchronizing signal LP as a clock to transfer the vertical synchronizing signal 19 into the common side shift register circuit. The signal corresponding to the scanning signal is generated by outputting to each stage of the signal.

After the voltage level of the signal is converted in the common shift register circuit by the common level shifter circuit, the four level values V0, Y0 are set for each common electrode Y1 to Yn according to the combination of the signal and the alteration signal 9. One suitable voltage is selected from V1, V4, and V5 and output to the common electrodes Y1 to Yn of the liquid crystal panel 1.

In Fig. 3, the voltage (driving voltage) waveform Vx applied to the segment electrode Xj (j is any value of 1 to m) of the liquid crystal panel 1, and the common electrode Yi (i is any of 1 to n). Voltage difference VY1 applied to the value) and the voltage applied to the positive electrode Xj · Yi, that is, the applied voltage V (Xj, Yi) to the pixels Xj, Yi of the liquid crystal panel 1 is shown.

As described above, the segment side driving circuit 2 includes a 1/2 division circuit 14 and a gradation signal generation circuit 15 because 16 gradations are displayed by pulse width modulation. These specific configurations will be described with reference to FIG. 5. In addition, the 1/2 frequency division circuit 14 and the gradation signal generation circuit 15 are commonly used for all the lines of the segment electrodes X1 to Xm, and output the driving voltages to the segment electrodes X1 to Xm, respectively. It is shared between signal processing circuits.

The gradation signal generation circuit 15 includes fourteen D-type flip-flop circuits (hereinafter referred to as flip-flop) DF / F1 to 14, fourteen AND / OR (AND / OR) circuits AND / 0R 1 to 14, Fourteen selection circuits SEL1 to 14 are included. The AND / OR circuit AND / 0R i (i is an arbitrary value from 1 to 14. The same also applies below) includes two AND circuits (denoted by A and B in FIG. 5) and the AND circuit. An OR circuit is input to each output, and the output of the OR circuit is connected to an input terminal Di of a corresponding flip-flop DF / Fi.

The selection circuit SELi also includes two AND circuits (denoted A & B) in FIG. 5 and an OR circuit to which the respective outputs of the AND circuits are input.

The output Qi of the flip-flop DF / Fi is connected to one input terminal of the B side AND circuit of the AND / OR circuit AND / 0R i + 1 and one input terminal of the A side AND circuit in the selection circuit SELi. However, one input terminal of the B-side AND circuit in the first AND / OR circuit AND / OR 1 is connected to the power supply Vcc (high level).

The output / Qi of the flip-flop DF / Fi (an inverted signal of the output Qi of the DF / Fi) is connected to one input terminal of the B-side AND circuit in the selection circuit SELi. The output Qi + 1 of the flip-flop DF / Fi + 1 is input to one input terminal of the A-side AND circuit of the AND / OR circuit AND / 0R i. However, one input terminal of the A side AND circuit of the 14th AND / OR circuit AND / 0R 14 is connected to the power supply Vcc.

On the other hand, the 1/2 frequency divider circuit 14 includes a D flip-flop circuit (hereinafter referred to as "flip-flop") 30 constituting a toggle circuit, and two inverter circuits 31.32. The output DQ of the flip-flop 30 is connected in common to the other input terminal of the A side AND circuit of each AND / OR circuit AND / 0R i, and the other input of the A side AND circuit of each selection circuit SELi. It is also commonly connected to the terminal.

The output / DQ (inverting signal of DQ) of the flip-flop 30 of the 1/2 frequency division circuit 14 is commonly connected to the other input terminal of the B-side AND circuit of each AND / OR circuit AND / 0R i. And the other input terminal of the B side AND circuit of each selection circuit SELi.

As a result, the flip-flops DF / F1 to 14 switch the output DQ (or the inverted signal / DQ) from the 1/2 frequency divider 14 between the low level and the high level, so that the AND / OR circuit AND Since the outputs of / 0R 1 to 14 are also switched, they function as bidirectional shift registers.

To the clock input terminal CK of the flip-flops DF / F1 to 14, the gray level signal clock is commonly input through the inverter circuit 31. The reset signal RST is commonly input to the reset input terminal R (reset at high level) of the flip-flops DF / F1 to 14.

The output of the selection circuit SELi becomes the gradation signal GRi. In addition, the gradation signal GR0 is connected to the ground level, and the gradation signal GR15 is connected to Vcc.

The flip-flop 30 of the 1/2 frequency division circuit 14 is composed of a toggle circuit to which the input terminal D and the output terminal / Q are connected. The horizontal synchronous signal LP is applied to the clock input terminal CK of the flip-flop 30. It is input through the inverter circuit 32.

As described above, the signal DQ is output at one output terminal Q of the flip-flop 30, and the signal / DQ is output at the other output terminal / Q, and input to the gradation signal generating circuit 15, respectively. Although not shown, in order to ensure the initial setting, the vertical synchronization signal 19 may be input to the reset input terminal R of the flip-flop 30.

The circuit operation of the 1/2 frequency division circuit 14 and the gradation signal generation circuit 15 will be described next with reference to the timing chart of FIG.

First, all of the flip-flops DF / F1 to 14 in the gradation signal generation circuit 15 are reset by the reset signal RST. Further, a signal / LP (inverted signal of the horizontal sync signal LP) is input to the clock input terminal CK of the flip-flop 30 in the 1/2 frequency divider circuit 14, so that the signal / LP rises (i.e., the signal LP). 4), the signal DQ performs a toggle operation. In other words, the signal DQ is switched between the high level (denoted "A" in FIG. 4) and the low level (denoted "B" in FIG. 4) when the pulse of the horizontal synchronizing signal LP falls.

In the period A when the signal DQ is at a high level, the AND-OR circuit AND / 0R side A AND circuit of 1 to 14 is activated, so in the flip-flop DF / F1 to 14 constituting the shift register, the flip-flop DF / Fi + Data is transferred from 1 to flip-flop DF / Fi.

First, although the output Q14 of the flip-flop DF / F14 is initially at the low level, the attraction terminal of the AND side of the AND circuit of the AND / OR circuit AND / 0R 14 at the time CLK1 of the clock signal 10 decreases. Vcc (high level) is taken in to output a high level signal from the output terminal Q14. Next, the flip-flop DF / F 13 accepts the above output at the time when the next clock falls (CLK2) and outputs a high level signal from the output terminal Q13.

The high level signal is then output in synchronism with the falling of the gradation signal clock 10 sequentially from the output terminal Q12 to Q1 by the same operation.

Since the AND side of the selection circuit SELi is also activated, the signal at the output terminal Qi of each flip-flop DF / Fi is output as the gradation signal GRi.

Therefore, in the period in which the signal DQ is in the high level A, the gradation signal GRi outputs a high level when the CLK15-i of the gradation signal clock 10 falls, and maintains the high level in the remaining period.

Subsequently, when the next signal / LP is input to the clock input terminal CK of the flip-flop 30, the signal DQ changes to low level B. At this time, the reset signal RST is input to the flip-flops DF / F1 to 14.

During the low level B period, in the flip-flop DF / F1 to 14 constituting the shift register circuit, the B-side AND circuit of the AND / OR circuit AND / 0R 1 to 14 is activated, and the flip-flop DF / Fi is reversed. Data is transferred to the flip-flop DF / Fi + 1.

First, the output Q1 of the flip-flop DF / F1 is initially at the low level due to the reset signal RST. However, the B side of the AND / OR circuit AND / 0R (1) at the time when the gray level signal clock 10 falls (CLKl). Vcc (high level) is input from the input terminal of the AND circuit, and a high level is output from the output terminal Q1. The output terminal Q1 on the other side of the flip-flop DF / F1 changes inversely to the low level.

Next, the flip-flop DF / F2 takes the above output at the time when the next gray level clock 10 falls (CLK2) and outputs a high level signal from the output terminal Q2. The output terminal / Q2 on the other side of the flip-flop DF / F2 reversely changes to the low level.

The high level is output from the output terminals Q3 to Q14 sequentially in the same manner as described above, in synchronization with the fall of the gradation signal clock 10. On the other hand, the output terminals Q3 to Q14 are converted to low level and output.

Since the AND side of the selection circuit SELi is activated, the signal at the output terminal / Qi of the respective flip-flop DF / Fi is output as the gradation signal GRi. Therefore, when the signal DQ is in the low level B period, the GRi outputs a waveform that changes from the high level to the low level when the CLKi of the gradation signal clock 10 falls, and the remaining period maintains the low level.

Thereafter, the reset signal RST is inputted to the flip-flops DF / F1 to 14, and when the horizontal synchronizing signal LP falls, the signal DQ becomes the high level A again, and the above operation is repeated in the period of the high level A. do. Therefore, as shown in FIG. 4, the output signal GRi is output by the following operation | movement. In the meantime, as described above, GR0 maintains a low level and GR15 maintains a high level.

Each gradation signal GR0 to GR15 generated by the gradation signal generation circuit 15 is input to the gradation decoder circuit 16 as described above.

FIG. 6 is a diagram showing the configuration of a gradation decoder circuit 16 and a line latch circuit 13 for outputting a driving voltage to the segment electrode Xj of the liquid crystal panel 1.

Therefore, the gradation decoder circuit 16 and the line latch circuit l3 are provided for each segment electrode X1 to Xm, but the gradation signals GR0 to GR15 from the gradation signal generation circuit 15 are the segment electrodes X1 to Xm. It is input in common to all of the gradation decoder circuits 16 for.

The gradation decoder circuit 16 includes sixteen first AND circuits 33, sixteen second AND circuits 34, and an OR circuit 35, and the line latch circuit 13 includes four D's. A type flip-flop circuit (hereinafter referred to as "flip-flop") 36 and an inverter circuit 37 are included.

The gradation signals GR0 to GR15 from the gradation signal generation circuit 15 are input to one input terminal of the corresponding first AND circuit 33, respectively, and the output from the first AND circuit 33 is the OR circuit ( 35). In addition, each of the second AND circuits 34 is input with output signals (outputs at the output terminals Q or / Q) from the four flip-flops 36, and the outputs from the second AND circuits 34 are Each input is input to the other input terminal of the corresponding first AND circuit 33.

Four flip-flops 36 in the line latch circuit 13 respectively correspond to 4-bit display data D3, D2, D1, and D0 for 16-gradation display, and the clock input terminal of each flip-flop 36 The horizontal synchronizing signal LP inverted through the inverter circuit 37 is input to CK.

Therefore, the display data of the corresponding bit when the horizontal synchronization signal LP is lowered is input to the input terminal D of each flip-flop 36, and the output terminals Q and / Q of each flip-flop 36 are based on the display data. The signal is output from).

Thus, as the gradation decoder circuit 16, one of the gradation signals GR0 to GR15 is selected according to the 4-bit display data D3, D2, D1, and D0, as shown in Table 1 below. The selected gradation signal is output from the output terminal of the OR circuit 35 to the level shifter 17.

TABLE 1

Display data D 3 D 2 Dl D0 Output from the gradation decoder circuit 0 0 0 00 0 0 10 0 1 00 0 1 1... … 1 1 1 01 1 1 1 GR0GR1GR2GR3... … GR14GR15

The gray level signal output from the gray level decoder circuit 16 is converted into a voltage level by the level shifter circuit 17. Thereafter, as described above, a driving voltage is generated through the liquid crystal drive output circuit 18 composed of analog switches such as a transmission gate, and the driving voltage is applied to the corresponding segment electrode Xj of the liquid crystal panel 1. .

3, the gradation signal (gradation display pulse) GR3 outputted to the segment electrode Xj when the scanning electrode Yi is scanned, and the gradation signal output to the segment Xj when the next scanning electrode Yi + 1 is being scanned. The GR8 is output while the level of the gradation signal is maintained at the same level as it moves from the horizontal period Hi to Hi + 1. Therefore, in one horizontal period, there is no change point of the rising or falling of the pulse only once.

Therefore, as shown in the voltages W11, W12, and W13 in Fig. 3, when the pixels Xj and Yi are selected (in scanning, in other words, in Fig. 3, on the common electrode other than Yi in the horizontal period Hi), The charge / discharge of the pixel capacitance of the liquid crystal panel 1 in the pixel) is performed once in one horizontal period. Moreover, since GR0 and GR15 suitable for white display and black display have no change point, they are irrelevant to charge / discharge.

As described above, in the present embodiment, the phase timing of the gradation signals GR1 to GR14 can be changed every one horizontal period by generating pulses of the gradation signals GR1 to GR14 that are laterally symmetric about the horizontal synchronizing signal LP. .

As a result, the rise (or fall) of the pulses of the gradation signals GR1 to GR14 is decreased once every one horizontal period, and the rise (or fall) of the pulse of the driving voltage applied to the non-selected pixel is once every one horizontal period. As a result, the charge / discharge in the non-selected pixel can be reduced to about 1/2.

Therefore, when gray scale display is performed by the pulse width modulation method, power consumption can be greatly reduced as compared with the conventional case. By lowering power consumption, the large screen of the liquid crystal display device 20 can be made large when the portable device is used, and the burden of the portable power source can be reduced, so that the liquid crystal display device 20 can be used for a long time. The power supply can be miniaturized.

Incidentally, the increase in the number of circuits in this embodiment compared with the conventional configuration is an AND / OR circuit provided to the 1/2 frequency division circuit 14 and the gradation signal generation circuit 15 in the segment side driving circuit 2. In addition, since these circuits are common to the segment electrodes X1 to Xm, the circuits stop at an increase of around 1% at most.

Therefore, in order to downsize the drive circuit for a portable device, the segment side drive circuit 2, the common side drive circuit 3, and also the circuit blocks such as the controller 5, the display RAM and the power supply circuit 4, etc. Even if chipping is carried out, there is no problem in applying the present invention.

On the contrary, in response to the large screen, a plurality of segment side driving circuits are cascaded to connect data latch clocks and the like to the segment side driving circuits of the next stage to share other control signals and power supplies. Also about this, this invention can be applied.

The segment side driving circuit 2 according to the present embodiment is a normal LSI chip, which is formed by a tape carrier package (TCP) to an electrode (ITO line) of the liquid crystal panel 1, for example, an anisotropic conductive film (ACF) or the like. It can be realized by the structure installed by thermocompression through. As another configuration, the driving circuit LSI chip in the form of a chip-on-glass (COG) can be formed on the electrode (ITO line) of the liquid crystal panel 1 by, for example, thermocompression bonding through an anisotropic conductive film (ACF). . In addition, a circuit may be constructed on the glass substrate of the liquid crystal panel 1 by low temperature polysilicon technology or the like.

EXAMPLE 2

Another embodiment of the present invention will be described with reference to FIGS. 7 to 9. In addition, for the convenience of explanation, the same code | symbol is shown to the member which has the function shown by the said Example, and the description is abbreviate | omitted.

The liquid crystal display device 20 selects the voltage applied to the segment electrodes X1 to Xm as a voltage of four values, and selects the voltage applied to the common electrodes Y1 to Yn as a four-value voltage that is the same value. It is a structure which drives each pixel of the panel 1.

The liquid crystal display device 50 of this embodiment is different from this, and selects the voltage applied to the segment electrodes X1 to Xm at a binary value, and the voltage applied to the common electrodes Y1 to Yn at a value of 3. Each pixel of the liquid crystal panel 1 is driven.

As shown in FIG. 7, the liquid crystal display device 50 is the same as the liquid crystal display device 20 with respect to configurations other than the segment side driving circuit 52 and the power supply circuit 54. The power supply circuit 54 generates voltages VS1 and VS2 to be applied to the segment electrodes X1 to Xm, outputs them to the segment side driving circuit 52, and at the same time the voltages VC1 to VC2 to be applied to the common electrodes Y1 to Yn. VC3 is generated and output to the common side drive circuit 3.

As shown in Fig. 8, the segment side driving circuit 52 includes the shift register circuit 11, the data latch circuit 12, the line latch circuit 13, the 1/2 division circuit 14, and the gradation signal generation. A circuit 15, a gradation decoder 16, and a liquid crystal drive output circuit 18. The configuration and operation of each of these circuits are as described above except for the liquid crystal drive output circuit 18. The liquid crystal drive output circuit 18 has a configuration in which the voltage VS1 · VS2 and the alternating signal 9 are input, and the circuit configuration thereof is also different.

In the segment side driving circuit 52, the voltage applied VS2 to the liquid crystal panel 1 is the ground level, and the voltage V1 applied to the liquid crystal panel 1 is the power supply Vcc (for example, 5V) of the segment side driving circuit 52. In this case, the high voltage is not required for the segment side driving circuit 52, and the level shifter circuit can be omitted. In this configuration, the power supply of the segment side driving circuit 52 is Vcc and GND, and as a result, the power supply voltage VDD is no longer required.

In FIG. 9, in the liquid crystal display device 50, the voltage waveform VxJ applied to the segment electrode Xj (j is an arbitrary value of 1 to m) of the liquid crystal panel 1, and the common electrode Yi (i is 1 The voltage difference VY1 applied to the arbitrary value of -n) and the voltage difference of the voltage applied to the positive electrode XjYi, that is, the applied voltage V (XJ, Yl) to the pixels Xj, Yi of the liquid crystal panel 1 appear.

As shown in Fig. 9, in the liquid crystal display device 50 of the present embodiment, like the liquid crystal display device 20, the gradation signal is changed only once in one horizontal period, and gradation display with reduced power consumption is realized. do.

That is, in the liquid crystal display device 50, the gradation signal GR3 output to the segment electrode Xj when scanning the scan electrode Yi, and the gradation signal GR8 output to the segment Xj when the next scanning electrode Yi + 1 is scanned, When moving from the horizontal period Hi to Hi + 1, the level of the gradation signal is output while maintaining the same level. Therefore, in one horizontal period, there is no change point of the rising or falling of the pulse only once.

For this reason, as shown by the voltages W14, W15, and W16 in FIG. 9, the charge and discharge of the pixel capacitance of the liquid crystal panel 1 in the unselected pixel is one horizontal period. Therefore, in the liquid crystal display device 50, charging / discharging to a pixel that is not selected can be about 1/2 of the conventional one. As a result, a significant reduction in power consumption of the liquid crystal display device 50 can be achieved.

As mentioned above, although the Example of this invention was described, this invention is not limited to this, A various change and combination are possible.

For example, the display panel is not limited to the liquid crystal panel. Incidentally, although the present embodiment has 16 gradation display, the present invention is not limited to the 16 gradation display, but can be applied to any of the gradation displays. In addition, the display data can use either parallel data or serial data, and can be latched at a predetermined address of the data latch circuit. In addition, if the display data corresponds to R, G, and B, the present invention can easily correspond to the color display.

In addition, the present invention can be applied to a display panel having a structure in which a plurality of segment side driving circuits are provided accordingly when the segment electrodes are divided into a plurality of groups (for example, divided into one or the other).

The present embodiment is a configuration example in which the gradation signals at equal intervals are generated by the gradation signal clock, but the present invention can also be applied to a configuration in which the boiling interval gradation signals combined with the transmission characteristics of the liquid crystal panel are generated. In such a configuration for generating a gradation signal having a boiling interval, for example, a reference clock generating circuit is provided, a clock having various phases is created by frequency division or the like based on a high frequency clock output from the circuit, and the gradation is selected while selecting the clock. An example is a configuration in which a gradation signal having a boiling interval is input to a signal generating circuit as a clock. As another configuration example, a plurality of gradation signal generation circuits are prepared, and clocks having different phases are input to the gradation signal generation circuits, respectively, to select gradation signals output from the circuit and to generate gradation signals at boiling intervals. Can be mentioned. Thus, by preparing a gray level signal having various boiling intervals and selecting the gray level signal, it can be applied to liquid crystal panels having different duty ratios and different effective voltages for each gray level display.

Further, in the present embodiment, the white display and the black display GR0 and GR15 are executed at a constant level (Vcc level, GND level), but with respect to the white display and the black display, lateral symmetry around the horizontal synchronizing signal is performed. The gradation signal of the pulse field can be used.

In the present embodiment, the gradation display voltage waveform applied to the pixels of the display panel is a waveform obtained by adding the gradation signal pulse width to the gradation voltage waveform, but the voltage waveform which subtracts the gradation signal pulse width from the gradation voltage waveform. As described above, a pulse having one change point in one horizontal period may be used.

In the driving method of the display device according to the present invention, as described above, the plurality of first electrodes and the plurality of second electrodes are arranged to intersect with each other, and each of the intersections is pixelated, and sequentially in the plurality of second electrodes. For the pixel on the selected second electrode, a driving voltage corresponding to the gradation level of the input data signal is applied from the first electrode to perform gradation display, and the driving voltage is one horizontal period by the input horizontal synchronizing signal. In the method of driving a display device generated each time, at least a part of the gray level signal corresponding to each gray level is prepared with a plurality of gray level signals that are laterally symmetric about the horizontal synchronization signal, wherein the data signal The driving voltage is generated by selecting the gray scale signal according to the method.

According to the above method, by generating a pulse of the gradation signal which is laterally symmetric about the horizontal synchronization signal, the phase and timing of the gradation signal can be changed every one horizontal period.

As a result, the rise (or fall) of the pulse of the gradation signal decreases once every one horizontal period, and the rise (or fall) of the pulse of the driving voltage applied to the non-selected pixels decreases once every one horizontal period, thereby displaying the display. The number of charge / discharge cycles of the pixel capacitance of the device can be reduced.

Therefore, when gray scale display is performed by the pulse width modulation method, power consumption can be greatly reduced as compared with the conventional case. Such low power consumption allows large display screens to be used when being used for a portable device, and can reduce the burden on a portable power supply, thereby enabling long-term use of the device and miniaturizing the power supply.

In addition, "centering on the horizontal synchronizing signal" means that the center of the horizontal synchronizing signal pulse is falling, but can generate a gradation symmetrical signal that is laterally symmetric about the rise of the horizontal synchronizing signal pulse, In the peak period of the horizontal synchronizing signal pulse, a gradation signal which is laterally symmetrical may be generated about an arbitrary point in time.

In addition, in the method of driving the display device according to the present invention, a plurality of first electrodes and a plurality of second electrodes are arranged to cross each other, and each intersection is pixelated, and is sequentially selected from the plurality of second electrodes. The driving voltage corresponding to the gradation level of the input data signal is applied to the pixel on the second electrode from the first electrode to perform gradation display, and the driving voltage is generated every one horizontal period by the input horizontal synchronization signal. In the driving method of the display device, a plurality of gradations that maintain the same voltage level when at least a part of the gradation signals corresponding to each gradation level are two consecutive horizontal periods, and shift from the previous horizontal period to the subsequent horizontal period. A signal is prepared, and among these, a gray level signal corresponding to the data signal is selected to generate the driving voltage.

It is suitable to apply the driving method of the present invention to a liquid crystal display device, whereby the power consumption can be further reduced in the liquid crystal display device, which is more suitable for a portable device.

In addition, in order to solve the above problems, the driving circuit of the display device according to the present invention is arranged so that a plurality of first electrodes and a plurality of second electrodes cross each other, and each of the crossing portions is pixelated to form the plurality of second electrodes. To the pixels on the second electrode sequentially selected in the electrode, a driving voltage corresponding to the gradation level of the input data signal is applied from the first electrode to perform gradation display, so that the driving voltage is applied to the input horizontal synchronization signal. In the driving circuit of the display device generated every one horizontal period, a gradation signal for generating a plurality of gradation signals in which at least a part of the gradation signals corresponding to each gradation level is laterally symmetric around the horizontal synchronization signal. And a gradation signal selecting means for selecting a gradation signal according to the data signal among the plurality of gradation signals. It shall be.

According to the above configuration, by generating the pulse of the gradation signal which is laterally symmetric about the horizontal synchronizing signal, the rise (or fall) of the gradation signal pulse is reduced once every one horizontal period, thereby filling the pixel capacity of the display device. The number of discharges can be reduced.

Therefore, when gray scale display is performed by the pulse width modulation method, power consumption can be greatly reduced as compared with the conventional case. Such low power consumption enables large display screens to be used in portable use, and can reduce the burden on portable power supplies, thereby enabling long-term use of the device and miniaturizing the power supply. .

In addition, since the power consumption is reduced by a simple circuit configuration, there is almost no increase in the circuit, and there is no problem in miniaturization of the display device.

Preferably, the driving circuit of the present invention includes a 1/2 division circuit for switching the output signal each time the horizontal synchronous signal is input and sending the output signal to the gradation signal generation circuit. The signal generation circuit can generate pulses of the gradation signal which are laterally symmetric about the horizontal synchronizing signal based on the output signal of the 1/2 division circuit.

In addition, it is suitable that the 1/2 frequency divider circuit includes a D flip-flop circuit as a toggle circuit, thereby realizing a simple circuit configuration.

In addition, a "toggle circuit" means here the circuit which an output inverts every time a clock signal is input.

The gradation signal generation circuit is further configured to output a gradation signal by selecting a bidirectional shift register circuit for changing the transmission direction for each input of the horizontal synchronization signal and an output signal from each stage of the bidirectional shift register circuit every one horizontal period. It is appropriate to have a configuration including a selection circuit, whereby a simple circuit configuration is realized. In addition, since the pulse width of the gray level signal generated easily can be changed by changing the clock input to the bidirectional shift register circuit, it is possible to provide a driving circuit which can realize driving in accordance with the characteristics of the display panel. .

It is preferable to apply the driving circuit of the present invention to a liquid crystal display device, whereby the liquid crystal display device can be further reduced in power consumption, which is more suitable for a portable device.

Specific examples or embodiments in the description of the present invention are for the purpose of clarifying the technical contents of the present invention, and are not to be construed as limited only by such specific examples. Various modifications and changes can be made within the scope of the claims as set forth below.

Claims (12)

A plurality of first electrodes and a plurality of second electrodes are arranged to intersect with each other, each crossing portion is a pixel, and a pixel on a second electrode sequentially selected from the plurality of second electrodes is used for the input of the data signal. According to the gradation level, a driving voltage is applied from the first electrode to perform gradation display, and the driving voltage is a driving method of a display device generated every horizontal period by an input horizontal synchronization signal. Preparing a plurality of gradation signals such that at least a part of the gradation signals corresponding to each gradation level is laterally symmetric about the horizontal synchronization signal; And And selecting the gray level signal corresponding to the data signal from the plurality of gray level signals to generate the driving voltage. A plurality of first electrodes and a plurality of second electrodes are arranged to intersect with each other, each crossing portion is a pixel, and a pixel on a second electrode sequentially selected from the plurality of second electrodes is used for the input of the data signal. A driving voltage corresponding to a gradation level is applied from the first electrode to perform gradation display, and the driving voltage is a driving method of a display device generated every one horizontal period by an input horizontal synchronization signal. Preparing a plurality of gradation signals in which at least a part of the gradation signals corresponding to each gradation level maintains the same voltage level in the transition from the preceding horizontal period to the later horizontal period in two consecutive horizontal periods; And And selecting the gray level signal corresponding to the data signal from the plurality of gray level signals to generate the driving voltage. The method of claim 1, wherein the display device is a liquid crystal display device. The method of claim 2, wherein the display device is a liquid crystal display device. A plurality of first electrodes and a plurality of second electrodes are arranged to intersect with each other, each crossing portion is a pixel, and a pixel on a second electrode sequentially selected from among the plurality of second electrodes is used for the input of the data signal. A driving circuit of a display device in which a driving voltage corresponding to a gradation level is applied from the first electrode to perform gradation display, and the driving voltage is generated every one horizontal period by an input horizontal synchronization signal. A gradation signal generation circuit for generating a plurality of gradation signals that are laterally symmetric about the horizontal synchronization signal with at least a part of the gradation signals corresponding to each gradation level; And And gray level signal selecting means for selecting a gray level signal corresponding to the data signal among the plurality of gray level signals. 6. The driving circuit of claim 5, further comprising a half frequency divider circuit for switching the output signal for each input of the horizontal synchronization signal and sending the output signal to the gray level signal generating circuit. 7. The driving circuit of claim 6, wherein the half-dividing circuit includes a D-type flip-flop circuit serving as a toggle circuit. 6. The gradation signal generating circuit according to claim 5, wherein the gradation signal generating circuit selects a bidirectional shift register circuit for changing a transfer direction with respect to the input of the horizontal synchronizing signal, and an output signal from each stage of the bidirectional shift register circuit every one horizontal period. And a selection circuit for outputting as a gradation signal. 6. The driving circuit of the display device according to claim 5, wherein the driving circuit of the display device is a driving circuit of the liquid crystal display device. Selecting, for each horizontal period of the horizontal synchronizing signal, a plurality of gray level signals that change in accordance with the gray level of the display data; Generating a driving signal according to the selected gray level signal; And A method of driving a display device comprising the step of applying gradation display by applying the signal to a plurality of pixels arranged in a matrix. And the gradation signal maintains its level upon transition to an adjacent horizontal period. For each horizontal period of the horizontal synchronous signal, a plurality of gradation signals varying in accordance with the gradation level of the display data are selected, a drive signal is generated in accordance with the gradation signal selected, and applied to a plurality of pixels arranged in a matrix. As a driving circuit of a display device that displays gradation by And the gradation signal is generated and selected by the gradation signal processing circuit, and the gradation signal processing circuit maintains the level of the gradation signal when the gradation signal transitions to an adjacent horizontal period. The gradation signal processing circuit according to claim 11, wherein the gradation signal processing circuit includes a ½ division circuit for dividing a horizontal synchronization signal ½ and a gradation signal generated by counting a clock for a gradation signal in accordance with a half division horizontal synchronization signal. And a gradation signal generating circuit which maintains its level when transitioning to an adjacent horizontal period, The gradation signal generating circuit includes a plurality of flip-flops, a plurality of AND / OR circuits provided between the flip-flops, and a plurality of gradation signals for selecting the gradation signals according to the outputs of the 1/2 division circuit and the outputs of the flip-flops. A selection circuit is provided; The output terminal Qi of the i-th flip-flop is connected to one input terminal of the first AND circuit of the (i + 1) -th AND / OR circuit and is connected to the first AND circuit in the i-th selection circuit. Connected to one of the two input terminals, while a high level voltage is applied to one of the attraction terminals of the second AND circuit in the first AND / OR circuit; The inverted output terminal / Qi of the i-th flip-flop is connected to one of two input terminals of the second AND circuit in the i-th selection circuit, and is input to the first AND circuit of the i-th AND / OR circuit. The output terminal Q (i + 1) of the (i + 1) th flip-flop is input to one of the terminals, and a high level voltage is applied to one of the input terminals of the first AND circuit of the AND / OR circuit of the last stage. Become; The 1/2 frequency division circuit is provided with a flip-flop circuit and first and second inverter circuits, and output terminals of the flip-flop are commonly connected to other input terminals of the first AND circuit of each of the AND / OR circuits. A common input is connected to another input terminal of the first AND circuit of each selection circuit, and an inverted output terminal of the flip-flop is commonly connected to another input terminal of the second AND circuit of the respective AND / OR circuits. Is also commonly connected to the other input terminal of the second AND circuit of each selection circuit; To the clock input terminal of the flip-flop in the gradation signal generation circuit, the clock for the gradation signal is commonly input through the first inverter circuit, and to the reset input terminals of the plurality of flip-flops in the gradation signal generation circuit. A driving circuit of a display device to which a reset signal is commonly input.