KR20010028876A - Apparatus for data backup of device having plural processors - Google Patents

Abstract

PURPOSE: A data backup device of an apparatus having a plurality of processors is provided to offer a stable backup function, and to easily restore backup information in case of changing a board by performing in case that each processor performs a backup of setting information of a device to a common backup memory, and by controlling an access in a backup circuit. CONSTITUTION: A control unit(13) controls that a plurality of processors(11)(12) access a memory(14) if a backup of setting information of a plurality of processors(11)(12) is performed to a memory(14). The control unit(13) makes the memory(14) used as a common memory of a plurality of processors(11)(12). The memory(14) performs a backup of the information of a plurality of processors(11)(12).

Description

Apparatus for data backup of device having plural processors}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data backup device of a device having a plurality of processors. In particular, when each processor in a device having a plurality of processor boards attempts to back up the configuration information of the device, it backs up to one common backup memory and backs up. The present invention relates to a data backup device of a device having a plurality of processors which provides a stable backup function by controlling their access in a circuit and is suitable for simply recovering backup information when the processor board is replaced.

In general, when there are two or more processors, the technology of using memory uses dual port RAM, or each processor uses a memory independently to perform a task.

1 is a block diagram of an apparatus including a plurality of processors, each including a conventional memory.

As shown therein, each of the memory 2 and 4 is provided therein so as to perform data transfer between the processors 1 and 3, respectively.

That is, in the case where there are two or more processors, each processor (1) (3) board has a backup memory (2) (4) in the board independently, each to manage their own backup memory. In this case, if you want to back up to different backup memory, you have to back up through communication between processors.

Thus, when there are two processor boards, each has its own backup memory (2) (4), so that when the power supply is interrupted or when the board is mounted and dismounted, the backup memory in the board is read separately. The device was operated to restore data or environment information set by the user.

When a user wants to store their own backup information in a memory of another processor, a method of double storing information to be backed up in another processor through communication between processors.

In addition, when replacing the processor board, the board's backup memory was inserted into the new board before the replacement.

However, this conventional technology has the inconvenience of having to replace the backup memory when replacing the board because the backup memory is inside the board.

In addition, when backing up to a single memory had to be through the communication between processors, there was a problem that increases the load on the processor.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to provide one common backup when each processor in a device having a plurality of processor boards attempts to back up the setting information of the device. It is to provide a data backup device of a device having a plurality of processors to provide a stable backup function and to simply restore the backup information when replacing the processor board by backing up to the memory and control their access in the backup circuit.

In order to achieve the above object, a data backup device of a device having a plurality of processors according to the present invention,

A plurality of processors; A controller configured to control the memory access of the plurality of processors so that the memory is used as a common memory of the plurality of processors when the configuration information of the plurality of processors is to be backed up to a memory; The technical configuration may include a memory for backing up the configuration information of the plurality of processors under the control of the controller.

1 is a block diagram of an apparatus including a plurality of processors, each including a conventional memory;

2 is a block diagram of a data backup device of an apparatus having a plurality of processors according to the present invention;

FIG. 3 is a detailed circuit diagram of the controller in FIG. 2.

Explanation of symbols on the main parts of the drawings

11, 12: processor 13: control unit

14: Memory

Hereinafter, an embodiment according to the technical concept of the data backup device of the device having a plurality of processors of the present invention as described above is as follows.

2 is a block diagram of a data backup device of an apparatus having a plurality of processors according to the present invention.

As shown therein, a plurality of processors (11) (12); When attempting to back up the setting information of the plurality of processors 11 and 12 to the memory 14, the memory 14 is controlled by accessing the memory 14 of the plurality of processors 11 and 12. A control unit 13 controlling to be used as a common memory of the processors 11 and 12; The memory 14 is configured to back up the setting information of the plurality of processors 11 and 12 under the control of the controller 13.

FIG. 3 is a detailed circuit diagram of the controller in FIG. 2.

As shown in the drawing, the plurality of processors 11 and 12 receive an address value and determine which processor among the plurality of processors 11 and 12 intends to back up to the memory 14 to enable the corresponding processor. An address processing unit 21 for changing the register to be writable; Data for transmitting setting information of one of the plurality of processors 11 and 12 to back up the setting information to the memory 14 according to the enable register value of the address processor 21 to the memory 14. A processing unit 22; The multiplexing processor 23 stores the address values, chip enable values, and read / write values of the plurality of processors 11 and 12 in the memory 14.

An operation of a data backup device of a device having a plurality of processors according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, FIG. 2 illustrates a configuration of an apparatus for data backup in the case of two processors. Therefore, the backup circuit composed of the control unit 13 and the memory 14 includes a programmable gate array for controlling access to the memory 14 and a nonvolatile memory capable of retaining data even when power supply is interrupted. And a control unit 13 made of PGA.

Therefore, when one of the two processors wants to use the backup memory 14, the controller 13 writes a value of "0" to the ENABLE register in the address processor 21, and reads and checks whether the value is correctly written. Access to (14).

This is to prevent two processors 11 and 12 from accessing at the same time. If the register value of one processor part is written as "0", the ENABLE A (or ENABLE B) signal of FIG. 3 becomes "L" and the other The value of the register is set to "1".

As a result, both ENABLE signals are "L" at the same time, preventing both ports from opening. After the backup using the backup memory 14 is completed, the ENABLE signal should be made "H".

If the ENABLE signal is not made "H" due to an abnormal operation of one processor, the ENABLE signal is forced to "H" by giving a reset signal.

In addition, the data bus uses a TRI-STATE buffer to open the memory-side output direction buffer for write access, and the read-side buffer for the processor (CPU) that is enabled for read access. The remaining buffers that are not open remain in the tree state.

The address, chip enable (CE, CHIP ENABLE) signal and read / write (R / W) signal are the ones from the two processor 11 (12) boards that enable the ENABLE signal to the memory.

The CE signal on the memory side turns ON only when one of the two processors is ENABLE to ensure stable memory operation.

As such, the present invention allows each processor in a device having a plurality of processor boards to back up to a common backup memory when attempting to back up the configuration information of the device and to control their access in the backup circuit.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the data backup device of a device having a plurality of processors according to the present invention manages the backup memory independently of the processor board so that the previous information can be used as it is without any additional work even when the processor board is replaced. Will be.

In addition, the present invention also allows a plurality of processors to access the same memory independently, it is possible to quickly back up to one backup memory without burdening the processor.

In addition, the present invention has the effect of reducing the risk of the contents of the backup memory due to the unit failure, etc. by controlling the access of the processor in the control unit consisting of a programmable gate array.

Claims (2)

A plurality of processors; A controller configured to control the memory access of the plurality of processors so that the memory is used as a common memory of the plurality of processors when the configuration information of the plurality of processors is to be backed up to a memory; And a memory for backing up the setting information of the plurality of processors under the control of the controller. The method of claim 1, wherein the control unit, An address processor configured to receive an address value from the plurality of processors, determine which one of the plurality of processors is to be backed up to the memory, and change an enable register of the corresponding processor to be writable; A data processor for transmitting, to the memory, configuration information of one of the plurality of processors to back up the configuration information to the memory according to an enable register value of the address processor; And a multiplexing processor configured to store address values, chip enable values, and read / write values of the plurality of processors in the memory.