KR20010027459A - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Method of manufacturing a capacitor in a semiconductor device Download PDF

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Publication number
KR20010027459A
KR20010027459A KR1019990039220A KR19990039220A KR20010027459A KR 20010027459 A KR20010027459 A KR 20010027459A KR 1019990039220 A KR1019990039220 A KR 1019990039220A KR 19990039220 A KR19990039220 A KR 19990039220A KR 20010027459 A KR20010027459 A KR 20010027459A
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South Korea
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film
oxide film
metal oxide
capacitor
metal
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KR1019990039220A
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Korean (ko)
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KR100373161B1 (en
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박창서
임찬
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박종섭
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to improve a leakage current characteristic of the capacitor, by preventing a storage electrode from being more oxidized in a deposition process of Ta2O5 and a heat treatment process for forming a dielectric layer. CONSTITUTION: A noble metal layer(6) as a storage electrode is formed on a semiconductor substrate(1) having a lower structure by using one of noble metals such as Ru, Ir and Rh. A conductive metal oxide layer(7) is formed on the noble metal layer. A Ta2O5 dielectric layer(8) is formed on the metal oxide layer. A plate electrode is formed on the Ta2O5 dielectric layer.

Description

반도체 소자의 캐패시터 제조 방법{Method of manufacturing a capacitor in a semiconductor device}Method of manufacturing a capacitor in a semiconductor device

본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 하부 전극으로 귀금속(noble metal)을 사용하고 유전체막으로 Ta2O5를 사용하는 MIM(Metal Insulator Metal) 구조의 캐패시터의 제조 공정에서, Ta2O5를 증착한 후에 실시하는 열처리 공정시 귀금속막 표면의 산화로 인한 유효 산화막 두께(Tox)의 증가를 방지하여 Ta2O5캐패시터의 누설 전류 특성을 개선시킬 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device. In particular, in the manufacturing process of a capacitor having a metal insulator metal (MIM) structure using a noble metal as a lower electrode and Ta 2 O 5 as a dielectric film, capacitor manufacturing method of the heat treatment process when the semiconductor element in the noble metal film to prevent an increase in effective oxide thickness (Tox) due to oxidation of the surface can improve the leakage current characteristics of the Ta 2 O 5 capacitor to be carried out after depositing the 2 O 5 It is about.

일반적으로, 반도체 메모리 소자의 제조 공정에서 Ta2O5와 같은 고 유전율의 물질을 이용한 캐패시터 제조에 있어서 소자의 고집적화에 따라 유전체막의 유효 산화막 두께(Tox) 감소 및 캐패시터의 누설 전류 특성의 개선이 요구되고 있다.In general, in manufacturing a capacitor using a high dielectric constant material such as Ta 2 O 5 in a semiconductor memory device manufacturing process, it is required to reduce the effective oxide thickness (Tox) of the dielectric film and to improve the leakage current characteristics of the capacitor due to the high integration of the device. It is becoming.

메모리 소자의 Ta2O5를 포함한 캐패시터 제조 공정시 하부 전극 물질로 폴리실리콘을 사용하는 경우 유효 산화막 두께를 30Å 이하로 감소시키는 것이 곤란하다. 그러나 금속 물질을 하부 전극으로 사용하는 경우 폴리실리콘과의 전기적 에너지 장벽 즉, 일 함수(work function)가 크므로 유효 산화막 두께를 감소시킬 수 있으며, 동일한 유효 산화막 두께에서의 누설 전류를 감소시킬 수 있다. 한편, 텅스텐과 같은 금속 물질을 하부 전극으로 이용하는 MIM(Metal Insulator Metal) 구조의 캐패시터 제조공정에서 텅스텐 하부 전극의 표면에 불순물이 함유된 산화막이 존재하게 되면 유전체막 증착 및 열처리 공정 후에 유전체막과 텅스텐 하부 전극 사이에 막질이 나쁘고 절연체인 텅스텐 산화막에 의해 유효 산화막 두께가 증가하게 된다. 또한, 후속 열처리 온도에서도 텅스텐 산화막의 산소 확산에 의해 텅스텐 하부 전극의 산화가 추가로 발생하여 누설 전류 특성을 더욱 열화 시키는 문제가 있다.When polysilicon is used as the lower electrode material in the capacitor manufacturing process including Ta 2 O 5 of the memory device, it is difficult to reduce the effective oxide film thickness to 30 kPa or less. However, when the metal material is used as the lower electrode, the effective energy film thickness, i.e., the work function, with the polysilicon is large, so that the effective oxide film thickness can be reduced and the leakage current at the same effective oxide film thickness can be reduced. . On the other hand, when an oxide film containing impurities is present on the surface of a tungsten lower electrode in a capacitor manufacturing process of a metal insulator metal (MIM) structure using a metal material such as tungsten as a lower electrode, the dielectric film and tungsten after the dielectric film deposition and heat treatment process The effective oxide film thickness is increased by the tungsten oxide film having poor film quality between the lower electrodes and the insulator. In addition, there is a problem that further oxidation of the tungsten lower electrode occurs due to oxygen diffusion of the tungsten oxide film even at a subsequent heat treatment temperature, thereby further deteriorating leakage current characteristics.

이러한 문제로 인하여, 금속 물질을 상, 하부 전극으로 이용한 MIM 구조의 캐패시터 형성시 유전체막 증착 후의 열 공정에 의한 하부 전극의 표면 산화 방지, 캐패시터의 유효 산화막 두께 감소 및 누설 전류 특성이 개선된 신뢰성 있는 소자를 제조하기 위해서는 양질의 캐패시터 유전체막을 증착하는 방법과 함께 유전체막의 하부층인 하부 전극의 재료 선택과 그 표면 처리 방법도 매우 중요한 이슈(issue)로 대두되고 있다.Due to these problems, when forming a capacitor having a MIM structure using a metal material as the upper and lower electrodes, it is possible to reliably prevent surface oxidation of the lower electrode by the thermal process after deposition of the dielectric film, reduce the effective oxide thickness of the capacitor, and improve the leakage current characteristics. In order to manufacture a device, along with a method of depositing a high quality capacitor dielectric film, a material selection and a surface treatment method of a lower electrode, which is a lower layer of the dielectric film, are also very important issues.

따라서, 본 발명은 MIM 구조의 캐패시터에서 하부 전극 재료로 Ru, Ir, Rh와 같은 귀금속을 사용하고, 유전체막으로 Ta2O5를 증착하기 전에 귀금속막의 표면을 강제로 산화시켜 순도가 높고 도전성을 갖는 금속 산화막을 형성시켜, 후속 Ta2O5증착 후 후속 열처리 공정을 진행하여도 하부 전극인 귀금속막이 산화되는 것이 방지되어 캐패시터의 누설 전류 특성을 개선시킬 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는 데 그 목적이 있다.Therefore, the present invention uses a noble metal such as Ru, Ir, Rh as the lower electrode material in the capacitor of the MIM structure, and forcibly oxidizes the surface of the noble metal film before depositing Ta 2 O 5 as the dielectric film to increase the purity and conductivity. It provides a method of manufacturing a capacitor of a semiconductor device capable of forming a metal oxide film having a metal oxide layer, preventing the oxidation of the precious metal film, which is a lower electrode, even when the subsequent heat treatment process is performed after the deposition of Ta 2 O 5 , thereby improving leakage current characteristics of the capacitor. Its purpose is to.

이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 하부 구조가 형성된 반도체 기판에 하부 전극으로 Ru, Ir 및 Rh중 어느 하나의 귀금속을 사용하여 귀금속막을 형성하는 단계; 상기 귀금속막의 표면에 도전성의 금속 산화막을 형성하는 단계; 상기 금속 산화막 상에 Ta2O5유전체막을 형성하는 단계; 및 상기 Ta2O5유전체막 상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming a precious metal film using any one of Ru, Ir, and Rh as a lower electrode on a semiconductor substrate on which a lower structure is formed; Forming a conductive metal oxide film on a surface of the noble metal film; Forming a Ta 2 O 5 dielectric film on the metal oxide film; And forming an upper electrode on the Ta 2 O 5 dielectric film.

도 1a 내지 도 1d는 본 발명에 따른 캐패시터 제조 방법을 설명하기 위해 도시한 단면도.1A to 1D are cross-sectional views for explaining a capacitor manufacturing method according to the present invention.

＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

1: 반도체 기판 2: 실리콘 산화막1: semiconductor substrate 2: silicon oxide film

3: 제 1 폴리실리콘층 4: Ti막3: first polysilicon layer 4: Ti film

5: TiN막 6: 귀금속막5: TiN film 6: noble metal film

7: 금속 산화막 8: Ta2O5유전체막7: metal oxide film 8: Ta 2 O 5 dielectric film

9: TiN막 10: 제 2 폴리실리콘층9: TiN film 10: 2nd polysilicon layer

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1a 내지 도 1d는 본 발명에 따른 캐패시터 제조 방법을 설명하기 위해 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a capacitor manufacturing method according to the present invention.

도 1a를 참조하면, 하부 구조가 형성된 반도체 기판(1) 상부에 실리콘 산화막(2)을 형성하고, 실리콘 산화막(2)상부에는 도핑된 제 1 폴리실리콘층(3)을 형성한다. 도핑된 제 1 폴리실리콘층(3) 상부에는 장벽 금속층(barrier metal layer)으로 Ti막(4)과 TiN막(5)을 순차적으로 형성한다.Referring to FIG. 1A, a silicon oxide film 2 is formed on a semiconductor substrate 1 on which a lower structure is formed, and a doped first polysilicon layer 3 is formed on the silicon oxide film 2. A Ti film 4 and a TiN film 5 are sequentially formed on the doped first polysilicon layer 3 as a barrier metal layer.

상기에서, Ti막(4)은 스퍼터링(Sputtering)법으로 Ti를 100 내지 200Å 두께로 증착하여 형성한다. TiN막(5)은 원료물질로 Ti(N(CH3)2)4(TDMAT)를 이용하고 운반가스로는 He 와 Ar 을 사용하는 금속 유기 화학기상증착(MOCVD)법으로 100 내지 200Å 두께로 증착하여 형성한다. 이때 증착 조건은 원료물질의 유량을 200 내지 500 sccm으로 하고, 운반가스인 He 와 Ar의 유량을 각각 100 내지 300 sccm으로 하며, 반응로 내의 압력을 2 내지 10 Torr로 유지하고, 반응로 내부 온도를 300 내지 500℃의 온도로 한다. 이후, 500 내지 1000W 의 파워로 20 내지 50초 정도 플라즈마 처리를 수행한다.In the above, the Ti film 4 is formed by depositing Ti to a thickness of 100 to 200 Å by sputtering. The TiN film 5 is deposited to a thickness of 100 to 200Å by metal organic chemical vapor deposition (MOCVD) method using Ti (N (CH 3 ) 2 ) 4 (TDMAT) as a raw material and using He and Ar as carrier gases. To form. At this time, the deposition conditions are the flow rate of the raw material to 200 to 500 sccm, the flow rate of the carrier gas He and Ar to 100 to 300 sccm, respectively, maintaining the pressure in the reactor to 2 to 10 Torr, the temperature inside the reactor To a temperature of 300 to 500 ° C. Thereafter, the plasma treatment is performed for about 20 to 50 seconds at a power of 500 to 1000 W.

도 1b를 참조하면, TiN막(5) 상부에 귀금속인 Ru, Ir 및 Rh중 어느 하나를 이용하여 귀금속막(6)을 형성하여 캐패시터의 하부 전극을 완성한다.Referring to FIG. 1B, the precious metal film 6 is formed on the TiN film 5 by using any one of Ru, Ir, and Rh, which are precious metals, to complete the lower electrode of the capacitor.

상기에서, 귀금속막(6)은 스퍼터링법이나 금속 유기물성 소오스를 이용하는 화학기상증착법으로 400 내지 600Å의 두께로 증착하여 형성한다.In the above, the noble metal film 6 is formed by depositing a thickness of 400 to 600 kPa by a sputtering method or a chemical vapor deposition method using a metal organic material source.

도 1c를 참조하면, 귀금속막(6)의 표면에 생성된 불순물이 함유된 산화막을 세정 공정으로 제거한 후, 산화 공정을 실시하여 귀금속막(6)의 표면에 금속 산화막(7)을 강제로 형성시킨다.Referring to FIG. 1C, after the oxide film containing impurities generated on the surface of the noble metal film 6 is removed by a cleaning process, an oxidation process is performed to forcibly form the metal oxide film 7 on the surface of the noble metal film 6. Let's do it.

상기에서, 세정 공정은 HF 용액을 사용한다. 금속 산화막(7)은 귀금속막(6)이 Ru일 경우 산화 공정에 의해 순도가 높고 도전성을 갖는 RuO2막이 되고, Ir일 경우 산화 공정에 의해 순도가 높고 도전성을 갖는 IrO2막이 되고, Rh일 경우 산화 공정에 의해 순도가 높고 도전성을 갖는 RhO2막이 된다. RuO2막, IrO2막 및 RhO2막과 같은 금속 산화막(7)은 10 내지 30Å의 두께로 형성한다. 금속 산화막(7)은 다음 3가지 방법 중 어느 하나를 적용하여 형성할 수 있다. 첫째, 350 내지 400℃의 온도에서 500W의 플라즈마 파워(plasma power)로 O2플라즈마 처리하는 방법이다. 둘째, 귀금속막(6) 표면에 O3가스를 불어넣은 상태에서 자외선을 조사하여 산소를 활성화시키는 방법으로서, 그 조건은 350 내지 400℃의 온도에서 25 내지 30 mW/㎠ 의 인텐시티 파워(intensity power)의 UV 램프를 사용한다. 셋째, O2분위기에서 550 내지 600℃의 온도로 급속 열처리(Rapid thermal annealing; RTA)하는 방법이다.In the above, the cleaning process uses HF solution. The metal oxide film 7 is a RuO 2 film having high purity and conductivity by the oxidation process when the noble metal film 6 is Ru, and becomes an IrO 2 film having high purity and conductivity by the oxidation process when Ir is In this case, an RhO 2 film having high purity and conductivity is obtained by an oxidation process. Metal oxide films 7 such as RuO 2 films, IrO 2 films, and RhO 2 films are formed to a thickness of 10 to 30 kPa. The metal oxide film 7 can be formed by applying any one of the following three methods. First, a method of O 2 plasma treatment with a plasma power of 500W at a temperature of 350 to 400 ℃. Second, a method of activating oxygen by irradiation of ultraviolet rays in the state of blowing O 3 gas on the surface of the noble metal film 6, the conditions are 25-30 mW / ㎠ intensity power (intensity power at a temperature of 350 ~ 400 ℃) ) UV lamp. Third, rapid thermal annealing (RTA) at a temperature of 550 to 600 ° C. in an O 2 atmosphere.

도 1d를 참조하면, 금속 산화막(7) 상에 Ta2O5유전체막(8)을 형성한다. Ta2O5 유전체막(8) 상에 TiN 막(9) 및 도핑된 제 2 폴리실리콘층(10)을 순차적으로 형성하여 캐패시터의 상부 전극을 완성한다. 이러한 일련의 공정에 의해 MIM 구조의 Ta2O5캐패시터가 제조된다.Referring to FIG. 1D, Ta on the metal oxide film 72O5The dielectric film 8 is formed. Ta2O5 The TiN film 9 and the doped second polysilicon layer 10 are sequentially formed on the dielectric film 8 to complete the upper electrode of the capacitor. Ta of MIM structure by this series of processes2O5Capacitors are manufactured.

상기에서, Ta2O5유전체막(8)은 원료물질로 Ta(C2H5O)5를 사용하고, 운반가스 및 산화제로 각각 N2가스와 O2가스를 이용하며, 이때 N2가스의 유량을 350 내지 450 sccm으로 유지하고, O2가스의 유량을 20 내지 50 sccm으로 유지하며, 반응로 내의 압력을 0.1 내지 0.6 Torr로 유지하고, 반응로 내의 온도를 350 내지 450℃의 온도로 하여 Ta2O5를 증착한 후, 600 내지 670℃의 온도에서 20 내지 60초 동안 N2가스 또는 O2가스를 이용하여 O2분위기로 급속 열처리 공정(Rapid thermal process; RTP)을 실시하거나, 350℃ 이하의 온도에서 O2플라즈마 어닐 공정을 수행하여 형성한다. TiN 막(9)은 화학기상증착법으로 형성한다.In the above, the Ta 2 O 5 dielectric film 8 uses Ta (C 2 H 5 O) 5 as a raw material, N 2 gas and O 2 gas as a carrier gas and an oxidizing agent, respectively, where N 2 gas The flow rate of the reactor is maintained at 350 to 450 sccm, the flow rate of the O 2 gas is maintained at 20 to 50 sccm, the pressure in the reactor is maintained at 0.1 to 0.6 Torr, the temperature in the reactor to a temperature of 350 to 450 ℃ the Ta 2 O was deposited to 5, 600 to a temperature of 670 ℃ for 20 to 60 seconds N 2 rapidly as gas or O 2 O 2 atmosphere using a gas heat treatment process (rapid thermal process; RTP) to conduct, or It is formed by performing an O 2 plasma annealing process at a temperature of less than 350 ℃. The TiN film 9 is formed by chemical vapor deposition.

상기한 본 발명의 기본적인 원리는 MIM 구조의 Ta2O5캐패시터의 하부 전극으로 산화 공정에 의해 도전성의 금속 산화물을 얻을 수 있는 재료인 Ru, Ir 또는 Rh를 사용하는 것이다. Ru, Ir 및 Rh 각각을 산화 공정에 의해 산화시켰을 때 얻어지는 금속 산화물인 RuO2, IrO2및 RhO2각각은 도전성 물질로서 하부 전극의 재료로도 사용가능하며, 또한 유전체막을 형성하기 위한 Ta2O5증착 및 열처리 공정시 산화 억제 역할을 한다.The basic principle of the present invention described above is to use Ru, Ir or Rh, which is a material capable of obtaining a conductive metal oxide by an oxidation process, as a lower electrode of a Ta 2 O 5 capacitor having a MIM structure. The metal oxides RuO 2 , IrO 2 and RhO 2 , which are metal oxides obtained by oxidizing each of Ru, Ir, and Rh by an oxidation process, can also be used as a material of the lower electrode as a conductive material, and also Ta 2 O for forming a dielectric film. 5 It acts as an antioxidant in the deposition and heat treatment process.

상술한 바와 같이, 본 발명은 MIM 구조의 Ta2O5캐패시터 제조공정에서 산화 공정에 의해 도전성의 금속 산화물을 얻을 수 있는 재료인 Ru, Ir 또는 Rh를 사용하여 하부 전극을 형성하고, 이 하부 전극의 표면을 산화시켜 RuO2, IrO2및 RhO2와 같은 도전성의 금속 산화막을 형성하므로써, 유전체막 형성을 위한 Ta2O5증착 및 열처리 공정시 하부 전극이 더 이상 산화되는 것이 방지되어 캐패시터의 누설 전류 특성을 개선시킬 수 있다.As described above, the present invention forms a lower electrode using Ru, Ir or Rh, which is a material capable of obtaining a conductive metal oxide by an oxidation process in a Ta 2 O 5 capacitor manufacturing process having a MIM structure, and the lower electrode By oxidizing the surface of the metal oxide to form conductive metal oxide films such as RuO 2 , IrO 2 and RhO 2 , the lower electrode is prevented from oxidizing any more during the Ta 2 O 5 deposition and heat treatment process for forming the dielectric film. Current characteristics can be improved.

Claims (8)

하부 구조가 형성된 반도체 기판에 하부 전극으로 Ru, Ir 및 Rh중 어느 하나의 귀금속을 사용하여 귀금속막을 형성하는 단계;Forming a precious metal film on the semiconductor substrate on which the lower structure is formed by using the precious metal of any one of Ru, Ir, and Rh as a lower electrode; 상기 귀금속막의 표면에 도전성의 금속 산화막을 형성하는 단계;Forming a conductive metal oxide film on a surface of the noble metal film; 상기 금속 산화막 상에 Ta2O5유전체막을 형성하는 단계; 및Forming a Ta 2 O 5 dielectric film on the metal oxide film; And 상기 Ta2O5유전체막 상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And forming an upper electrode on the Ta 2 O 5 dielectric film. 제 1 항에 있어서,The method of claim 1, 상기 귀금속막은 스퍼터링법이나 금속 유기물성 소오스를 이용하는 화학기상증착법으로 400 내지 600Å의 두께로 증착하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The noble metal film is a capacitor manufacturing method of a semiconductor device, characterized in that formed by the deposition of a thickness of 400 to 600 kPa by a chemical vapor deposition method using a sputtering method or a metal organic material source. 제 1 항에 있어서,The method of claim 1, 상기 금속 산화막을 형성하기 전에 상기 귀금속막의 표면에 생성되는 불순물이 함유된 산화막을 제거하기 위하여 HF 용액으로 세정 공정을 실시하는 단계를 더 추가하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And performing a cleaning process with an HF solution to remove an oxide film containing impurities generated on the surface of the noble metal film before forming the metal oxide film. 제 1 항에 있어서,The method of claim 1, 상기 금속 산화막은 10 내지 30Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The metal oxide film is a capacitor manufacturing method of a semiconductor device, characterized in that formed in a thickness of 10 to 30Å. 제 1 항에 있어서,The method of claim 1, 상기 금속 산화막은 상기 귀금속막이 상기 Ru, Ir 및 Rh중 어느 것으로 형성되느냐에 따라 RuO2막, IrO2막 및 RhO2막중 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And the metal oxide film is formed of any one of a RuO 2 film, an IrO 2 film, and a RhO 2 film according to whether the noble metal film is formed of Ru, Ir, or Rh. 제 1 항에 있어서,The method of claim 1, 상기 금속 산화막은 350 내지 400℃의 온도에서 500W의 플라즈마 파워로 O2플라즈마 처리하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The metal oxide film is a capacitor manufacturing method of a semiconductor device, characterized in that formed by O 2 plasma treatment with a plasma power of 500W at a temperature of 350 to 400 ℃. 제 1 항에 있어서,The method of claim 1, 상기 금속 산화막은 350 내지 400℃의 온도에서 25 내지 30 mW/㎠ 의 인텐시티 파워의 UV 램프를 사용하고, 상기 귀금속막 표면에 O3가스를 불어넣은 상태에서 자외선을 조사하여 산소를 활성화시켜 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The metal oxide film is formed by using an UV lamp having an intensity power of 25 to 30 mW / cm 2 at a temperature of 350 to 400 ° C. and activating oxygen by irradiating ultraviolet rays with O 3 gas blown onto the surface of the noble metal film. A method for manufacturing a capacitor of a semiconductor device, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 금속 산화막은 O2분위기에서 550 내지 600℃의 온도로 급속 열처리하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The metal oxide film is a capacitor manufacturing method of a semiconductor device, characterized in that formed by rapid heat treatment at a temperature of 550 to 600 ℃ in O 2 atmosphere.
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KR100416733B1 (en) * 1995-03-20 2004-07-05 삼성전자주식회사 FERROELECTRIC CAPACITOR WITH UPPER AND LOWER ELECTRODE MADE OF Rh

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