KR20010027016A - 반도체 패키지 - Google Patents
반도체 패키지 Download PDFInfo
- Publication number
- KR20010027016A KR20010027016A KR1019990038574A KR19990038574A KR20010027016A KR 20010027016 A KR20010027016 A KR 20010027016A KR 1019990038574 A KR1019990038574 A KR 1019990038574A KR 19990038574 A KR19990038574 A KR 19990038574A KR 20010027016 A KR20010027016 A KR 20010027016A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- circuit board
- resin layer
- semiconductor
- stacked
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000000465 moulding Methods 0.000 claims abstract description 8
- 239000011347 resin Substances 0.000 claims description 52
- 229920005989 resin Polymers 0.000 claims description 52
- 229910000679 solder Inorganic materials 0.000 claims description 20
- 239000002390 adhesive tape Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 abstract 6
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 230000005855 radiation Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 230000005540 biological transmission Effects 0.000 description 7
- 238000007747 plating Methods 0.000 description 6
- 239000008393 encapsulating agent Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000000428 dust Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (8)
- 다수개로 적층된 상부 표면을 보호하기 위해 솔더마스크(30)를 접착하며, 전기적인 신호가 전달될 수 있도록 회로패턴이 형성되며 내측에 외부로 전기적인 신호가 출력될 수 있도록 비아홀(39)이 형성되며 내부에 서로 다른 크기로 외부에서 내부로 관통되어 공간이 형성된 각각의 수지층(31)이 형성된 회로기판(32)와, 상기 회로기판(31)의 수지층(31) 내부에 안착하여 내부의 회로패턴에 의해 전기적인 신호가 전달되도록 다수의 개수로 적층시키는 반도체 칩(35)과, 상기 반도체 칩(35)의 저면에 수지층(31)간에 전기적인 신호전달이 이루어질 수 있도록 내측전달수단(41)을 몰딩하여 이루어진 반도체 패키지.
- 제 1항에 있어서, 상기 반도체 칩(35)은 솔더마스크(30)를 매개로 다수의 개수로 적층형성하여 이루어진 반도체 패키지.
- 제 1항에 있어서, 상기 회로기판(32)의 수지층(31)은 반도체 칩(35)의 저면에 전기적인 신호를 연결하기 위해 몰딩한 작은 크기의 솔더볼의 주변에 외부의 이물질 유입을 방지할 수 있도록 하는 내측전달수단(41) 주변을 감싸 충진시키는 언더필(51)을 더 연결하여 이루어진 반도체 패키지.
- 제 1항에 있어서, 상기 반도체 칩(35)은 적층된 각 반도체 칩(35)의 전기적인 신호를 내측전달수단(41)을 통해 회로기판(32)에 전달할 수 있도록 적층된 회로기판(32)의 수지층(31)과 동일한 수평선상에 위치하도록 형성하여 이루어진 반도체 패키지.
- 제 1항에 있어서, 회로기판(32)은 외측전달수단(42)이 본딩된 수지층(31) 저면 중앙에 외부의 냉각 공기에 의해 내측의 열이 냉각될 수 있도록 일정 두께로 구멍을 형성한 벤트홀(52)로 이루어진 반도체 패키지.
- 제 1항에 있어서, 상기 반도체 칩(35)은 내부의 회로패턴의 전기적인 신호가 서로 도통되는 것을 방지할 수 있도록 각각의 저면 또는 상면에 접착테이프(34)를 접착시켜 연결하는 이루어진 반도체 패키지.
- 제 1항에 있어서, 상기 수지층(31)은 내부의 열을 외부로 방출하며 내부의 부품을 보호할 수 있도록 일정 두께로 판 형성된 방열판(38)이 연결되어 이루어진 반도체패키지.
- 제 1항 또는 제 5항에 있어서, 외측전달수단(42)은 적층된 회로기판(32)의 수지층(31) 상부나 하부에 연결되거나 방열판(38)의 하부에 연결되어 이루어진 반도체 패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990038574A KR100357877B1 (ko) | 1999-09-10 | 1999-09-10 | 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990038574A KR100357877B1 (ko) | 1999-09-10 | 1999-09-10 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010027016A true KR20010027016A (ko) | 2001-04-06 |
KR100357877B1 KR100357877B1 (ko) | 2002-10-25 |
Family
ID=19610903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019990038574A KR100357877B1 (ko) | 1999-09-10 | 1999-09-10 | 반도체 패키지 |
Country Status (1)
Country | Link |
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KR (1) | KR100357877B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100836642B1 (ko) * | 2007-03-07 | 2008-06-10 | 삼성전기주식회사 | 전자 패키지 및 그 제조방법 |
-
1999
- 1999-09-10 KR KR1019990038574A patent/KR100357877B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100836642B1 (ko) * | 2007-03-07 | 2008-06-10 | 삼성전기주식회사 | 전자 패키지 및 그 제조방법 |
Also Published As
Publication number | Publication date |
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KR100357877B1 (ko) | 2002-10-25 |
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