KR20010026741A - Chemical mechanical polishing method for polishing with a high selectivity - Google Patents

Abstract

PURPOSE: A chemical mechanical polishing(CMP) method for high selective polishing is provided to remarkably shorten the time taken for an entire CMP process while easily performing the CMP process of a high selectivity, by greatly reducing time delay in polishing an upper surface with a high selectivity polishing agent. CONSTITUTION: A chemical mechanical polishing(CMP) process is firstly performed with a non ceria-based polishing agent to polish an embossed surface on a filling oxide layer. A CMP process is secondly performed regarding the filling oxide layer from which the embossed upper surface is eliminated, with a high selectivity polishing agent to stop polishing in a polishing stop layer.

Description

Chemical mechanical polishing method for polishing with a high selectivity

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chemical mechanical polishing method, which is one of the planarization methods in a semiconductor device manufacturing process, and more particularly, to a chemical mechanical polishing method for highly selective polishing.

In general, a semiconductor device manufactured by stacking a plurality of patterned material layers on a wafer generates a step, that is, a height difference depending on whether each material layer is patterned. This step increases with the increase in the number of layers of material to be laminated, the pattern miniaturization, and the increase in device integration. This step causes defects in each manufacturing process and deteriorates the electrical characteristics of the wiring. In the semiconductor device manufacturing process, planarization technology becomes increasingly important.

Chemical mechanical polishing (CMP) is well known as a technique for flattening the level of the wafer surface. This chemical mechanical polishing process is a global planarization process in the manufacture of semiconductor devices by combining mechanical methods using polishing pads and slurries and chemical methods using chemical components of slurry solutions to mechanically and chemically process wafer surfaces. It is a process of polishing.

The CMP process is also applied to trench type isolation processes such as shallow trench isolation (STI). In the trench type isolation process, a semiconductor substrate is etched to form a trench, an insulating material such as an oxide film is embedded therein, and a device isolation film is formed through a CMP process.

Hereinafter, a trench type device isolation process to which the conventional CMP method is applied will be described with reference to FIGS. 1 to 4.

Referring to FIG. 1, a photo process for defining an active region and a field region on a semiconductor substrate 10 is performed.

That is, the pad oxide film 3 having a thickness of 100 to 300 Å is formed on the semiconductor substrate 1. The entire surface of the substrate 1 on which the pad oxide film 3 is formed is divided into an active region where semiconductor individual elements are formed and an inactive region for electrically separating the semiconductor individual elements from each other.

The photoresist pattern PR is formed on the semiconductor substrate 1 on which the pad oxide layer 3 is formed to expose inactive regions other than the active region. The first and second trenches T1 and T2 are formed by anisotropically etching the semiconductor substrate 1 on which the pad oxide film 3 is formed using the photoresist pattern PR as an etching mask.

Here, the first trenches T1 are trenches for forming device isolation layers in areas of high density of individual semiconductor devices, such as cell regions, and are formed in relatively narrow regions, and the second trenches T2 are formed in peripheral circuit regions or cores. Like the core region, the semiconductor individual elements are formed in a relatively wide region as a trench for forming an isolation layer in a region where the density of the individual semiconductor elements is relatively lower than that of the cell region.

Referring to FIG. 2, after removing the photoresist pattern PR, thermally oxidize a resultant product in which the trenches T1 and T2 are formed to form a thermal oxide film 5 on sidewalls and bottoms of the trenches T1 and T2. .

The nitride film 7 of the thin film is formed on the entire surface of the resultant product in which the thermal oxide film 5 is formed to a thickness of about 50 to 500 kPa. At this time, when the thickness of the nitride film 7 is formed to be thinner than 50 GPa, the nitride film may not play a role as a stop layer in the subsequent CMP process, while the thickness of the nitride film 7 is formed to be thicker than 500 GPa. In this case, due to the strong internal stress of the nitride film itself, it may cause the substrate silicon stress, and the phosphate wet etching time after the subsequent CMP process is prolonged to cause the non-uniformity of the etching surface.

Next, an insulator film filling the trenches T1 and T2 is formed on the entire substrate on which the thin film nitride film 7 is formed, for example, an oxide film (SiO ₂ ) 9 having excellent investment characteristics.

Referring to FIG. 3, a conventional CMP method is applied to the oxide film 9. According to this CMP method, the oxide film 9 is continuously chemically polished using an abrasive having a higher selectivity of SiO ₂ than SiN until the nitride film 7 of the thin film is exposed. In the case where the nitride film 7 is a thin film having a thickness of about 100 to 300 mW, a cerium oxide (Ceria: CeO ₂ ) -based slurry having high selectivity is used in order to be used as a stop layer.

The thin film nitride film (SiN) 7 serves to block trench sidewall oxidation in a subsequent oxidation process and serves as a stop layer in a highly selective CMP process. Therefore, the CMP process is automatically stopped without further progressing by the nitride film (SiN) 7 of the thin film.

Referring to FIG. 4, the nitride film 7 and the thermal oxide film 5 exposed after the CMP process are wet-etched with a phosphate solution and a buffered oxide etchant (BOE), and then a sacrificial oxide film (not shown) is grown to wet again. By etching, the device isolation layers 9a and 9b are completed.

According to the trench type isolation method as described above, in order to use the nitride film of the thin film as the stop layer in the CMP process, a highly selective cerium oxide-based slurry is used as an abrasive.

At this time, although the selectivity of the oxide-to-nitride film was excellent in the selectivity of the oxide film to the nitride film of about 10: 1, the polishing rate on the upper embossing surface of the deposited oxide film in the unplanarized state was very low. There is a problem that the time required for the CMP process by the slurry of very long.

This poor polishing removal rate results in lower throughput and also increases the cost of the cerium oxide CMP process.

The technical problem to be achieved by the present invention is to provide a chemical mechanical polishing method having excellent polishing rate while using a highly selective abrasive.

1 to 4 are cross-sectional views illustrating a trench type device isolation process using a conventional CMP method.

5 to 8 are cross-sectional views illustrating a trench type device isolation process using the CMP method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 semiconductor substrate, 15 thermal oxide film, 17 silicon nitride film 19 CVD oxide film

In order to achieve the above technical problem, the chemical mechanical polishing method for high selectivity polishing according to the present invention, the trench formed on the semiconductor substrate, the polishing stop layer of the thin film formed on top of the trench, and to fill the trench In the chemical mechanical polishing method for depositing and removing a predetermined portion of the filling oxide film on the pattern structure of the semiconductor substrate formed on the polishing stop layer and formed of a filling oxide film filling the trench,

a) a first polishing step of chemical mechanical polishing with a non-ceramic abrasive to smoothly polish the convex embossed surface on the filling oxide film; And

b) a secondary polishing step of chemically mechanically polishing the charged oxide film from which the upper surface of the embossed shape is removed, with a highly selective polishing agent for the oxide film so as to automatically stop polishing in the polishing stop layer. It provides a configured chemical mechanical polishing method.

In the chemical mechanical polishing method, components of the stop layer include a silicon nitride film, a boron nitride film, and a polysilicon film.

As the highly selective abrasive, a ceria-based slurry is used.

According to the chemical mechanical polishing method for high selectivity polishing according to the present invention, in the polishing process for the filling oxide film formed on the trench, the first surface is polished with a non-ceramic abrasive on the convex embossed upper surface, and A two-step process of secondary polishing is performed on the packed oxide film from which the upper surface of the embossed shape is removed with a highly selective abrasive.

The above non-seria series primary polishing not only makes it possible to greatly reduce the polishing time on the embossed surface of the upper portion of the filling oxide film, but also to perform polishing in the polishing stop layer by secondary polishing with a highly selective abrasive. It can be stopped automatically. Therefore, it is possible to greatly reduce the time delay when polishing the upper surface by the highly selective abrasive, it is possible to significantly reduce the time required for the entire CMP process and at the same time smoothly achieve a high selectivity CMP process.

Hereinafter, a trench type device isolation process to which the CMP method of the present invention is applied will be described in detail with reference to FIGS. 5 to 8.

Referring to FIG. 5, first and second trenches T1 and T2 are formed on the semiconductor substrate 10. Here, the first trenches T1 are trenches formed in regions of high density of individual semiconductor devices, such as cell regions, and are relatively narrow, and the second trenches T2 are formed like peripheral circuit regions or core regions. The trenches are formed in regions where the density of the individual semiconductor elements is relatively lower than that of the cell region.

The method of forming the trenches T1 and T2 is the same as that described in the prior art.

That is, the semiconductor substrate 10 is divided into an active region in which semiconductor individual elements are formed and an inactive region, which is an area in which the semiconductor individual elements are electrically separated from each other, and then the semiconductor substrate 10 is formed by using a mask pattern. The first and second trenches T1 and T2 are formed by anisotropically etching the inactive region of.

After the first and second trenches T1 and T2 are formed, a mask pattern is removed, and a thin thermal oxide film 15 having a thickness of about 30 to 500 kPa is formed on the entire surface of the substrate 10. The thermal oxide film 15 serves to heal surface damage during trench etching, to form a stable Si-O ₂ bond on the silicon surface of the semiconductor substrate 10 to prevent leakage current through the surface, and The corner is curved by oxidation to form a role for preventing the concentration of stress.

After forming the trenches T1 and T2 as described above, a silicon nitride film (SiN) 17 is deposited to a thickness of about 50 to 500 kPa as a polishing stop layer on the entire upper surface of the thermal oxide film 15. The silicon nitride film 17 serves to block trench sidewall oxidation in a subsequent oxidation process and serves as a CMP stop layer in a high selectivity CMP process. When the silicon nitride layer (SiN) is formed thicker than the thickness, the role of the oxide barrier layer and the CMP stop layer is improved, but when the silicon nitride layer (SiN) is thickened, a silicon nitride layer (SiN) having a strong internal stress may cause stress on the Si of the substrate After the CMP process, the wet etching time of phosphoric acid may be lengthened to generate non-uniformity.

Next, an oxide film formed by chemical vapor deposition (CVD) is formed on the entire surface of the trenches T1 and T2 formed thereon, and then heated to a temperature of 900 to 1190 ° C. in an inert gas atmosphere such as N ₂ or Ar. The heat treatment is performed for about 1 hour to form a densified CVD oxide film 19.

Here, the oxide film may be formed using an CVD oxide film having high trench filling ability, such as USG (Undoped Silicate Glass) using TEOS (Tetra Ethyl Ortho Silicate), HDP (High Density Plasma), and high temperature USG (about 500 ° C). The first and second trenches T1 and T2 are deposited to a sufficient degree.

In addition to the above method, the densification step may be performed in a wet oxidation atmosphere or a dry oxidation atmosphere within a few minutes to several hours.

At this time, as shown in FIG. 5, the CVD oxide film formed on the upper portions of the first trenches T1 formed in the high density regions of the semiconductor individual devices, such as the cell region, has a thick filling thickness and embossed upper surface thereof. It will be formed in a state. On the other hand, the CVD oxide film formed on the upper portions of the second trenches T2 formed in the region where the density of the individual semiconductor elements, such as the peripheral circuit region or the core region, is lower than that of the cell region, has a thin filling thickness. The upper surface is formed in a relatively flat state.

6 and 7, the CMP method of the present invention is applied to the CVD oxide film 19 described above.

In FIG. 6, a first CMP step of performing chemical mechanical polishing with a non-ceramic abrasive is performed to flatly polish the convex embossed surface on the CVD oxide film 19 formed on the first trench T1. .

Silica-based slurry is used as the non-ceramic abrasive. The removal rate of the silica-based slurry on the CVD oxide film is in a range similar to or greater than that of the blanket removal rate.

Therefore, the polishing process can be performed at a very high polishing rate. The silica-based slurry has a low selectivity ratio of oxide to nitride of about 4: 1, but the first CMP step is a step irrelevant to the selectivity because the first CMP step is to polish the upper portion of the CVD oxide film 19. For reference, a blanket polishing rate means a polishing removal rate of a CMP process with respect to an oxide film having no pattern formed thereon.

Next, in FIG. 7, the CVD oxide film 19 having the upper surface of the embossed shape removed is polished so that the polishing can be automatically stopped when the silicon nitride film (SiN) 17 is exposed. A second CMP step of chemical mechanical polishing with a polishing agent is carried out.

As a highly selective abrasive, a cerium (Ceria: CeO ₂ ) -based slurry is used, and a high selectivity of about 10: 1 can be secured as a selectivity of an oxide film and a nitride film.

For reference, the CMP process using the ceria-based slurry is suitable for trench formation because of its high selectivity with respect to silicon nitride film (SiON), boron nitride film, polysilicon and Si of the substrate.

Thus, after the second CMP step, the oxide film in the trenches T1 and T2 is stopped by the silicon nitride film 17.

After the second CMP step, the exposed nitride film 17 and the thermal oxide film 15 are wet-etched with a phosphate solution and BOE, and then, after the sacrificial oxide film (not shown) is grown and wet-etched again, the device isolation films 19a and 19b are removed. Complete

The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.

As described above, according to the chemical mechanical polishing method for high-selectivity polishing according to the present invention, a non-ceramic abrasive may be used for the upper surface of the convex embossed form during the polishing process for the filling oxide film formed on the trench. Secondary polishing is carried out by secondary polishing with a highly selective abrasive on the packed oxide film from which the upper surface of the embossed shape is removed.

The above non-seria series primary polishing not only makes it possible to greatly reduce the polishing time on the embossed surface of the upper portion of the filling oxide film, but also to perform polishing in the polishing stop layer by secondary polishing with a highly selective abrasive. It can be stopped automatically. Therefore, it is possible to greatly reduce the time delay when polishing the upper surface by the highly selective abrasive, it is possible to significantly reduce the time required for the entire CMP process and at the same time smoothly achieve a high selectivity CMP process.

Claims (3)

A pattern structure of a semiconductor substrate formed of a trench formed on a semiconductor substrate, a polishing stop layer of a thin film formed on top of the trench, and a deposited oxide film formed on the polishing stop layer to fill the trench and filling the trench. In the chemical mechanical polishing method for polishing and removing a predetermined portion of the packed oxide film for a) a first polishing step of chemical mechanical polishing with a non-ceramic abrasive to smoothly polish the convex embossed surface on the filling oxide film; And b) a secondary polishing step of chemically mechanically polishing the charged oxide film from which the upper surface of the embossed shape is removed, with a highly selective polishing agent for the oxide film so as to automatically stop polishing in the polishing stop layer. Chemical mechanical polishing method for high selectivity polishing, characterized in that. The chemical mechanical polishing method of claim 1, wherein the polishing stop layer comprises a silicon nitride film, a boron nitride film, and a polysilicon film. The method of claim 1, wherein in the chemical mechanical polishing method, Ceria-based slurry is used as the highly selective abrasive.