KR20010019730A - Receiver circuit of infrared data associate core - Google Patents

Abstract

PURPOSE: A receiving circuit of an infrared ray semiconductor device is provided to reduce a size of a receiving unit first in first out buffer, and to prevent unnecessary CRC data and a stop plag from writing to the buffer by extracting only pure payload data among data inputted from an IrDA receiving unit. CONSTITUTION: An IrDA receiving unit includes 4 shift registers of n bytes(50) and a receiving unit first in first out buffer(60). The shift registers(50) receive infrared packet data from a transmitting unit, synchronize the data to a clock signal, and shift the data. The payload data inputted using the n bytes shift registers(50) are written to the shift registers(50). The n bytes data received from the IrDA core are stored in the receiving first in first out buffer(60).

Description

RECEIVER CIRCUIT OF INFRARED DATA ASSOCIATE CORE}

The present invention relates to a receiving circuit of an infrared semiconductor device, and more particularly to a receiving circuit of an IrDA core and a data processing method thereof.

In the conventional Infrared Data Association (IrDA) receiver, a data processing method includes a CRC data and a stop flag from a payload data portion except a start flag to process IrDA data packets provided from a transmitter. In order to remove the CRC data and the stop flag by storing the data in the receiver FIFO buffer (First In First Out buffer) (hereinafter called receiver buffer) in order, and reading the data in the receiver buffer from the software provided in the IrDA core. I use it.

As shown in FIG. 1, the configuration of the IrDA data packet data 2 includes a start flag, payload data 10, CRC data 20, and a stop flag 30 in the MIR (Medium Speed Infrared) mode. It consists of.

In the case of the FIR mode, a preamble, a start flag, payload data, CRC data, and a stop flag are included.

According to the above method, the following problems arise. That is, the size of the buffer increases by storing unnecessary CRC data and stop flags in the receiver buffer.

In order to clear the data additionally stored in the receiver buffer, the software included in the IrDA core reads payload data, CRC data, and a stop flag, and again, unnecessary CRC and stop flag data among the data read by the software. You have to remove them, which puts a lot of load on the software.

The method of clearing the receiver buffer may be cleared by reading the receiver buffer.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problem, and by extracting only pure payload data from the IrDA receiver and storing the pure payload data in the receiver buffer, the receiver buffer is reduced in size, and unnecessary CRC data and stop flags are stored in the receiver buffer. An IrDA receiver is provided to prevent the data from being written to.

1 is a diagram illustrating an IrDA packet data format according to an MIR mode case of an IrDA core; And

2 is a block diagram showing the configuration of a receiver of an IrDA core using a shift register according to the present invention.

* Explanation of symbols on the main parts of the drawing *

2: IrDA packet 10: Payload data

20: CRC data 30: Stop flag

40 IrDA receiver 50 Shift register

60: receiver buffer

According to an aspect of the present invention for achieving the above object, in a receiving circuit of an infrared data association (IrDA) core for receiving and processing infrared data from a writing line transmission circuit: an infrared ray from the transmitting circuit A plurality of shift registers for shifting the data to obtain a delay time according to an error detection operation of the data when data is input; A buffer circuit for writing the shifted data from the shift registers; The receiving circuit detects an error of the input data at every delay time according to the sheet operation, and when the last portion of the data is input to the first register of the shift register, terminates the error detection operation of the data. By outputting the result, unnecessary data in the data is prevented from being written to the buffer circuit.

In a preferred embodiment of this feature, the shift registers are: registers of 4 bytes in the high speed mode and registers of 2 bytes in the medium speed mode.

Therefore, according to the present invention, payload data input by using the N byte shift registers to the N byte data coming into the receiver of the IrDA core is written into the shift register, and then shifted N times and stored in the receiver buffer.

Since the last data of the payload data is shifted N times and stored in the receiver buffer, the N payload data and the CRC data are compared during the N shift delay time.

Therefore, when the last data of the payload data is input to the receiver buffer, the CRC data is input to check the payload data for errors and inform the software of the result.

(Example)

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In IrDA packet transmission, one packet is composed of a start flag, payload data, CRC data, and a stop flag and is transmitted from a transmitter to a receiver.

As described above, in the IrDA receiver, all data subsequent to the payload data are also stored in the receiver buffer.

However, this method increases the size of the buffer by storing RC data and even stop flags, which are not pure data, in the receiver buffer, and reads all the data to clear the receiver buffer from the software point of view. The process of removing them has become a heavy burden.

2 is a block diagram illustrating a portion of an IrDA receiver of an IrDA core according to an embodiment of the present invention.

Referring to the drawings, the IrDA receiver 40 includes four N byte shift registers 50 and a receiver buffer 60.

The shift registers 50 receive infrared packet data (Data Input) from a transmitter (not shown) and shift data in synchronization with a clock signal (Byte Clock). For example, shift 4 times in the MIR mode and twice in the FIR mode.

Therefore, the payload data, which is input using the N byte shift registers 50 to the receiver 40 of the IrDA core, is written to the shift register 50 using the N byte shift registers 50, and then shifted N times to receive the receiver buffer 60. Store in

The reason for shifting N times is to obtain the time required to check for a data error by comparing the CRC data portion at the end of IrDA packet data as described above.

Next, since the last data of the payload data is shifted N times and stored in the receiver buffer 60, during the N shift delay time, the N payload data and the CRC data are compared, and the last payload data is stored in the receiver buffer 60. When entered, CRC data can be entered to check for payload data errors and inform the software of the results.

Therefore, the payload data and the CRC data can be compared and inspected without writing the CRC data into the receiver buffer 60.

IrDA is divided into FIR mode with a transmission rate of 4 Mbps and MIR mode with a transmission rate of 1 Mbps. For example, in the FIR mode, it has 32-bit CRC data, which shifts four times using a four-byte shift register. In the MIR mode, since it has 16 bits of CRC data, it shifts twice using a 2-byte shift register.

Therefore, the first data of the packet data input to the IrDA receiver 40 is sent to the shift register 50. Subsequently, the first data input to the shift register 50 is shifted four times and input to the receiver buffer 60. When the last data of the payload data is input to the shift register 50, the CRDA data is input to the IrDA packet data during the fourth shift, thereby detecting the data error.

As described above, the present invention may reduce the size of the buffer by extracting only pure data from the data input to the IrDA receiver and storing the pure data in the receiver buffer.

It also reduces the load on the software by not storing unnecessary data in the receiver buffer, thereby increasing the execution speed.

Claims (2)

In a receiving circuit of an infrared data association (IrDA) core for receiving and processing infrared data from a write-in transmission circuit: A plurality of shift registers for shifting the data when the infrared data is input from the transmitting circuit to obtain a delay time according to an error detection operation of the data; A buffer circuit for writing the shifted data from the shift registers; The receiving circuit detects an error of the input data at every delay time according to the sheet operation, and when the last portion of the data is input to the first register of the shift register, terminates the error detection operation of the data. And outputting a result to prevent unnecessary data from being written into the buffer circuit. The method of claim 1, The shift registers are: The receiving circuit of the IrDA core, characterized in that provided in the high-speed mode is provided with a register of 4 bytes size, in the middle speed mode is provided with a register of 2 bytes size.