JPH0546516A - Reception control system - Google Patents

Abstract

PURPOSE:To attain the even and effective reception of date without being conscious of the communication speed in a reception control system for which the data are fetched from a reception buffer by generating the interruption levels in accordance with the number of data received from plural reception buffers and making a processor fetch the data. CONSTITUTION:The reception buffers 3 are provided on every communication port to store the received data in the FIFOs. An interruption generating circuit 4 generates the interruption levels in accordance with the number of date stored in the buffers 3. Then the data received at plural communication ports are stored in the buffers 3 respectively, and a processor accepts the interruption of the highest level among those interruptions received from the buffers 3. Then the processor fetches the data from the corresponding buffer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception control system for fetching data from a reception buffer. Along with the decentralization of computer usage patterns, the number of cases in which one host computer is shared by a plurality of terminals is increasing. Therefore, it is required that the communication control device on the host side control the plurality of communication ports efficiently and fairly.

[0002]

2. Description of the Related Art Conventionally, a communication control device for controlling a plurality of communication ports by one microprocessor is shown in the circuit configuration of FIG. 6 in order to avoid overrun when data is simultaneously received from a plurality of communication ports. As described above, a reception buffer FIFO for a plurality of characters is prepared for each communication port. Then, when data of one character or a plurality of characters is stored in the reception buffer FIFO, an interrupt is generated in the microprocessor, and the microprocessor reads the data from the reception buffer FIFO in the interrupt.

[0003]

In the conventional method of the circuit configuration shown in FIG. 6 described above, if valid data is stored in the reception buffer FIFO, even if one character is stored, an interrupt occurs in the processor, so that reception is performed at different communication speeds. If the received data is stored in each reception buffer FIFO, there is a problem that an overrun occurs in a communication port having a high communication speed. To solve this problem,
According to a preset communication speed, a program is given a priority order for reading data from the reception buffer FIFO of the communication port, and this priority order, that is, the reception buffer FIFO of the communication port having a high communication speed accepts an interrupt with a high priority. A method of importing the data may be considered. However, if the program accepts the interrupt and takes in the data in consideration of the priority, the load of the processor is increased and the complexity of performing the priority processing occurs.

An object of the present invention is to generate an interrupt level according to the number of data in a plurality of receiving buffers, allow a processor to fetch data, and perform fair and efficient data receiving processing without being aware of the communication speed. There is.

[0005]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, the reception buffer 3 is a buffer that stores received data in first-in first-out (FIFO).

The interrupt generation circuit 4 is a circuit for generating an interrupt level corresponding to the number of data stored in the reception buffer 3.

[0007]

According to the present invention, as shown in FIG. 1, the data received by a plurality of communication ports are respectively stored in the reception buffers 3, and the interrupt generation circuits 4 of these reception buffers 3 correspond to the number of the stored data. An interrupt of the specified level is generated, and the processor that receives the interrupt of the highest level fetches data from the corresponding receive buffer 3, for example, the receive buffer 3 corresponding to the vector address.

Therefore, an interrupt level corresponding to the number of data in the receiving buffer 3 is generated, and the processor fetches the data from the receiving buffer 3 having the highest level and performs the receiving process, so that the fairness can be obtained without considering the communication speed. Moreover, it becomes possible to efficiently perform the data reception processing.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be sequentially described in detail with reference to FIGS.

In FIG. 1, a receiver 1 is a transmission medium,
For example, it has a communication port (input port) for receiving serial data by RS232C via a line.

The S / P conversion circuit 2 is a circuit for converting serial data received by the receiver 1 into parallel data. The reception buffer 3 includes the S / P conversion circuit 2
It is a FIFO (first-in first-out) buffer for temporarily storing the data converted into parallel by.

The interrupt generation circuit 4 is a circuit for generating an interrupt level corresponding to the number of data stored in the reception buffer 3. For example, when the maximum number of data that can be stored in the reception buffer 3 is 4, the number of data is 1, 2
Interrupt levels 1, 2, 3, 4 corresponding to 3, 4,
(Highest interrupt level) is generated and the microprocessor 5 is caused to generate an interrupt.

The bus is an address bus, a data bus or the like. FIG. 2 shows an example of the receive buffer / interrupt generating circuit of the present invention. This is a specific circuit example of the reception buffer 3 and the interrupt generation circuit 4 of FIG.

In FIG. 2, a register 31 is a register for temporarily storing the data (8 bits) taken in from the input port, and corresponds to the FIFO type reception buffer 3 of FIG.

The flag 32 is a flag indicating that the data taken in from the input port is stored in the register 31 and has not been read from the output port. It is set to "1" when data is fetched from the input port and stored in the register 31, and reset to "0" when data is transmitted from the output port.

The input address counter 33 is for generating the address of the register 31 for storing the data taken in from the input port. For example, first register 3
8 bits of data from the input port are stored in 1, then 8 bits of data from the input port are stored in the next register 31, and so on. It generates an input address for doing so (described later with reference to FIG. 3).

The output address counter 34 is ...
, 31 to generate an output address for sending out the data from the output port (described later with reference to FIG. 3).

The decode circuit 35 decodes the number of valid data stored in the register 31, that is, the number of which the flag 32 is "1" in this case, and the interrupt level LEV.
This is a circuit for generating any of 1 to LEV4.

The OR circuit 36 determines whether any of the flags 32 is set to "1" and whether or not there is data to be captured.
It is a circuit that generates an RDY signal (output ready signal).

The comparison circuit 37 includes an input address counter 3
3 and the address of the output address counter 34 are compared,
It is a circuit that detects the fact that the IRDY (imp ready) signal is made inactive when the two coincide, that is, all the data is stored in the register 31 and no more data can be received, and notifies the input side.

The symbols in FIG. 2 represent the following. IRDY: input ready signal SIN: data shift impulse ORDY: output ready signal SOUT: data shift out pulse LEV1 to LEV4: level 1 to level 4 of interrupt signal Next, the operation of the configuration of FIG. 2 will be described in detail according to the flowchart of FIG. explain.

In FIG. 3, S1 determines whether or not the IRDY (input ready) signal is ON. This is a signal indicating that the comparison circuit 37 of FIG. 2 compares the input address counter 33 and the output address counter 34 and they do not match each other, and the register 31 is empty and ready to receive the received data. It is determined whether or not is on. If YES, the register 31 which is the reception buffer 3 has an empty space, and therefore one character of data is transmitted. On the other hand, if NO, the process waits until the IRDY signal turns on.

In S2, the data is stored in the register 31 pointed to by the input address counter, and the flag 32 is set.
This stores the data received from the input port of FIG. 2 in the register 31 pointed to by the input address counter 33 and sets the flag 32 of the register 31 to "1". In response to this, the decode circuit 35 of FIG. 2 generates an interrupt level and notifies the microprocessor 5 of the interrupt. At the same time, the ORDY (output ready) signal generated by the OR circuit 36 of FIG. 2 is notified to the microprocessor 5 to notify that the data output is ready.

In step S3, the input address counter 33 is incremented and the data is stored in the register 31.
To point to. In S4, it is determined whether or not the input count number ≧ the output count number. This is because the input count number (input address) counted by the input address counter 33 in FIG. 2 is compared with the output count number (output address) counted by the output address counter 34, and all the data is not stored in the register 31. It is determined whether or not the state. In the case of YES, one of the registers 31 in FIG. 2 is empty, so the IRDY signal of ON is sent to the receiving side. On the other hand, in the case of NO, since the data is stored in all the registers 31 and it is full, the OFF IRDY signal is transmitted, S4 is repeated, and it is repeatedly detected that the registers 31 are empty.

In S5, the microprocessor 5 sends a data read signal (SOUT signal) in response to the interrupt notification, and the register 31 pointed to by the output address counter 34.
Data is transmitted from the output port and the flag 32 is reset. As a result, the data is sent from the output port, and the microprocessor 5 takes it in the memory or the like at the predetermined address.

In step S6, the output address counter 34 is incremented. As described above, the received data is stored in the empty register 31, the flag 32 of this register 31 is set, and the interrupt of the level corresponding to the number of data stored in the register 31 is generated by the microprocessor 5.
Is notified and the data is fetched from the register 31 which is the reception buffer 3 in which the highest level interrupt is generated, the higher the number of data stored in the register 31, the higher the priority of the higher level interrupt. It becomes possible to take in the data and process it for reception. This allows the microprocessor 5 to fairly and efficiently fetch data from the register 31 constituting the reception buffer 3 without being aware of the receiving speed of the data fetched from the input port.

FIG. 4 shows a time chart of the present invention.
This is a time chart of the circuit of FIG. SIN
2 is a data shift impulse, which is a sync pulse signal to which data is input from the input side of FIG.

The input port is an input port for fetching the received data and storing it in the register 31.
The input address is an address generated by the input address counter 33 and which register 31 stores data.

Valid flags 1 to 4 are shown in FIG.
The flag 32 corresponds to or. LE
V1 to LEV4 are the LEV1 to LEV4 of FIG.
And the flag 32 corresponds to the number of "1" (a state in which data is set) corresponding to interrupt levels 1 to 4.

SOUT is a data shift-out pulse, which is a synchronizing pulse signal when the microprocessor 5 accepting the interrupt in FIG. 2 fetches data from the register 31.

The output address is the output address counter 3
4 is an address which is generated and is an address of the register 31 for reading data. Output port is register 3
1 is a port for sending the data read from the CPU 1 to the microprocessor 5.

Next, referring to the time chart of FIG.
The operation of the circuit will be described. Responds to the IRDY signal being turned on, while the data is being sent from the input side to the input port, the SIN signal is turned on and at the rising edge of this signal, the register () 31 of the input address “0” of the input address counter 33 The data is stored in the decoding circuit 35, and the decoding circuit 35 sends an interrupt signal of LEV1 to the microprocessor 5
To notify. At this time, the OR circuit 36 also notifies the microprocessor 5 of the ORDY signal.

At the falling edge of SIN rising at, the input address counter 33 is incremented to set the input address to "1". Similarly, ',', and so on
Repeatedly as shown in ",", LEV2, LEV3
To the microprocessor 5.

As described above, the received data is sequentially stored in the register 31 of FIG. 2 and the flag 32 is sequentially set, and the number of data stored in the register 31 (actually, the number in which the flag 31 is set to "1") is set. Any of the corresponding interrupt signals LEV1, LEV2, LEV3 is transmitted. Then, in the state in which the interrupt signal LEV3 is sent, the level becomes the highest priority, and the microprocessor 5 accepts this interrupt and starts the subsequent fetch processing.

In response to the microprocessor 5 accepting the level 3 interrupt and turning on the SOUT signal, the data read from the register () 31 having the output address "0" at the rising edge of the SOUT signal is read. At the same time as sending from the output port, the valid flag 1 (flag 32) is reset to off. In response to resetting the valid flag 1, LEV3 is turned off, and LEV3 is turned off.
2 is turned on.

At the falling edge of the SOUT signal, the output address counter 34 is incremented to "1". Similarly, perform ',' and output address “1”
The data of is sent from the output port.

FIG. 5 shows a block diagram of another embodiment of the present invention. In this system, an interrupt controller 6 is provided to notify the microprocessor 6 via the bus of the address of the receiving buffer 3 as a vector address when an interrupt occurs so that the data is read from the receiving buffer 3 of this vector address. ..

In FIG. 5, the interrupt controller 6 is
An LSI such as 259 notifies the microprocessor 5 of level 1, level 2, level 3, and level 4 interrupts, and sends the vector address of the receive buffer 3 to the bus during this interrupt process. By providing the interrupt controller 6, the microprocessor 5 accepts the highest level interrupt notified from the plurality of receiving buffers 3, refers to the vector address sent to the bus at that time, and The data is read from the address reception buffer 3.

[0039]

As described above, according to the present invention,
Since the processor adopts a configuration in which an interrupt level according to the number of data in the reception buffer 3 is generated and the processor fetches data from the reception buffer 3 having the highest level and performs reception processing, the program should be aware of the communication speed. Therefore, data reception processing can be performed fairly and efficiently from a plurality of reception buffers 3. As a result, compared to the conventional method of sequentially processing interrupts, it is not necessary to handle low-speed ports unnecessarily, and overruns on the high-speed port side are less likely to occur during concentrated load. Further, the program need not be aware of the communication speed set for the communication port at all, and an unnecessary load (priority order determination, etc.) can be prevented.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an example of a reception buffer / interrupt generation circuit of the present invention.

FIG. 3 is a control flowchart of the present invention.

FIG. 4 is a time chart of the present invention.

FIG. 5 is a configuration diagram of another embodiment of the present invention.

FIG. 6 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: Receiver 2: S / P conversion circuit 3: Reception buffer 31: Register 32: Flag 33: Input address counter 34: Output address counter 35: Decode circuit 36: OR circuit 37: Comparison circuit 4: Interrupt generation circuit 5: Microprocessor 6: Interrupt controller

Claims (2)

[Claims] 1. In a reception control method for fetching data from a reception buffer, first received data is received.
A reception buffer (3) provided for each communication port for storing in first-out, and an interrupt generation circuit (4) for generating an interrupt level corresponding to the number of data stored in the reception buffer (3), Data received by a plurality of communication ports are stored in the reception buffer (3) respectively, and the processor accepts the highest level interrupt among the interrupts from the interrupt generation circuit (4) of the reception buffer (3). A reception control system characterized in that the data is taken in from a corresponding reception buffer (3). 2. The structure according to claim 1, wherein when the processor receives the highest level interrupt, the data is fetched from the reception buffer (3) of the vector address transmitted to the data bus. The reception control method described.