CN101576867A - Extended universal asynchronous serial interface method, device and system - Google Patents
Extended universal asynchronous serial interface method, device and system Download PDFInfo
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- CN101576867A CN101576867A CNA200910086862XA CN200910086862A CN101576867A CN 101576867 A CN101576867 A CN 101576867A CN A200910086862X A CNA200910086862X A CN A200910086862XA CN 200910086862 A CN200910086862 A CN 200910086862A CN 101576867 A CN101576867 A CN 101576867A
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Abstract
The invention provides an extended universal asynchronous serial interface method, a device and a system. By arranging a first bit of data byte, the method, the device and the system can distinguish the data of two universal asynchronous serial interfaces, thus significantly reducing the cost and occupying no resources of other buses.
Description
Technical field
The present invention relates to a kind of extended universal asynchronous serial interface method, device and system, belong to data communication technology field.
Background technology
UART Universal Asynchronous Receiver Transmitter (Universal Asynchronous Receiver/Transmitter is called for short UART) can realize the lower duplex communication of speed between two equipment.
At present UART be personal computer (Personal Computer is called for short PC) with electronic communication in most widely used a kind of serial line interface, both can be used for communicating by letter between backboard and the interface card, also can be used for communicating by letter between PC and the system board.
The UART interface has only 3 signal wires, and as shown in Figure 1, device A sends data by sending data line TXD to opposite equip. B, and by the data of received signal line RXD reception from opposite equip. B, earth signal GND is a public earth signal that is used for the signal reference.
For data synchronization, device A must be provided with identical baud rate with B.If A sends data to B like this, A can put into data at interval according to regular time on TXD, and B then can be according to regular time interval reading of data on the TXD signal wire.
Device A at first dragged down the TXD signal beginning of expression transmission when data sent, and transmitted the data of 1 byte byte (promptly 8 bit bit represent a character) then on TXD at interval with regular time, afterwards TXD was drawn high the end of expression transmission.Transmit a byte if desired again and then need again TXD to be dragged down the expression beginning.When A receives, represented that transmission begins if discovery RXD drags down, A begins to read the data of 1 byte on the RXD.
UART is last, and general that send is ASCII (American StandardCode for Information Interchange, be called for short ASCII), ASCII character uses 7 bit to represent a character, and UART sends 8 bit, and 1 bit that then has more generally is set to 0.ASCII character is expressed as sky (Null) when being " 0x00 ", and is promptly meaningless.
The data of transmitting on UART at first need to be transformed to the ASCII character form, will become ASCII character " 0x30 " as character " 0 ".If receive " 0x30 " during reception, then corresponding A SCII code conversion is " 0 ".
Most of central processing units (Central Processing Unit is called for short CPU) all can have the UART interface, but UART interface quantity may be not enough in actual the use.At this moment Chang Yong method is to use special IC (Application Specific Intergrated Circuits, be called for short ASIC) realize from other buses, as local bus local bus or peripheral component interconnection (Peripheral Component Interconnect, be called for short PCI) change and expand UART, as shown in Figure 2.The shortcoming of doing like this is that cost is higher, and can take the resource of other buses.
Some chips can expand a plurality of UART from a UART, as patent " a kind of universal asynchronous serial extended chip of multi-bus interface " (application number 200610021607.3).Its main thought is to realize 2 big First Input First Output (First InputFirst Output for the serial ports that each expands in the chip, be called for short FIFO), as shown in Figure 3, all data are sent into FIFO when sending or receiving, send and receive by writing the corresponding registers control data then.Chip sends and reception condition by interrupt mode notice CPU.Owing to the data that receive all need be stored, receive by interrupt mode notice CPU again, therefore need bigger FIFO, cost is higher; And use interruption, software is complicated.
Patent " multichannel UART Universal Asynchronous Receiver Transmitter " (application number 03234618.2) proposes another method, as shown in Figure 4, additionally provide several address signals to be used to represent which serial ports passage is data are, data not in chip buffer memory directly receive or send, so just need not provide big FIFO, reduce cost.Because the equipment at female serial ports two ends all must be supported address decoding, otherwise can not use this circuit, has a serious limitation; Address decoding circuitry has also increased the complexity of circuit in addition.
Summary of the invention
The purpose of this invention is to provide a kind of extended universal asynchronous serial interface method, device and system, significantly reducing cost and can not take the expansion that realizes under the situation of other bus resources Asynchronous Serial Interface.
To achieve these goals, the invention provides a kind of extended universal asynchronous serial interface method of reseptance, described method comprises:
Receive the data that central processor CPU is sent from first Asynchronous Serial Interface, first bit of each data byte is 0 or 1 in the judgment data, if first bit is 0 then described data byte is sent to first interfacing equipment from second Asynchronous Serial Interface, if first bit is 1 then described data byte is sent to second interfacing equipment from the 3rd Asynchronous Serial Interface.
To achieve these goals, the invention provides a kind of extended universal asynchronous serial interface sending method, described method comprises:
Receive the data that first interfacing equipment is sent from second Asynchronous Serial Interface, first bit of each data byte in the data is replaced with 0, and send to CPU from first Asynchronous Serial Interface;
Receive the data that second interfacing equipment is sent from the 3rd Asynchronous Serial Interface, first bit of each data byte in the data is replaced with 1, and send to CPU from first Asynchronous Serial Interface.
To achieve these goals, the invention provides a kind of extended universal asynchronous serial interface receiving trap, described device comprises receiver module, judge module, the first interface sending module and the second interface sending module,
Described receiver module is used for receiving the data that CPU sends from first Asynchronous Serial Interface;
Described judge module is connected with receiver module, first bit that is used for each data byte of judgment data is 0 or 1, if first bit is 0 then gives the first interface sending module with data byte and handle, if first bit is 1 then gives the second interface sending module with data byte and handle;
The described first interface sending module is connected with judge module, is used for described data byte is sent to first interfacing equipment from second Asynchronous Serial Interface;
The described second interface sending module is connected with judge module, is used for described data byte is sent to second interfacing equipment from the 3rd Asynchronous Serial Interface.
To achieve these goals, the invention provides a kind of extended universal asynchronous serial interface dispensing device, described device comprises the first interface receiver module, the second interface receiver module and main sending module;
The described first interface receiver module is used for receiving the data that first interfacing equipment is sent from second Asynchronous Serial Interface, and gives main sending module and handle;
The described second interface receiver module is used for receiving the data that second interfacing equipment is sent from the 3rd Asynchronous Serial Interface, and gives main sending module and handle;
Described main sending module is connected with the second interface receiver module with the first interface receiver module, first bit that is used for each data byte of data that will receive from the first interface receiver module replaces with 0, to from the data that the second interface receiver module receives, replace with 1 by first bit of each data byte, and send to CPU from first Asynchronous Serial Interface.
To achieve these goals, the invention provides a kind of extended universal asynchronous serial interface device that comprises described extended universal asynchronous serial interface receiving trap and extended universal asynchronous serial interface dispensing device.
To achieve these goals, the invention provides a kind of extended universal asynchronous serial interface system that comprises described extended universal asynchronous serial interface device, described system also comprises and also comprises CPU, first interfacing equipment and second interfacing equipment,
Described CPU is connected with described extended universal asynchronous serial interface device, and first bit that is used for sending to each data byte of data of first interfacing equipment is set to 0, inserts a slack byte behind each data byte; First bit that sends to each data byte in the data of second interfacing equipment is set to 1, inserts a slack byte behind each data byte, and sends data from first Asynchronous Serial Interface; Also be used for respectively data being handled according to first bit of described data byte;
Described first interfacing equipment is connected with described extended universal asynchronous serial interface device by second Asynchronous Serial Interface;
Described second interfacing equipment is connected with described extended universal asynchronous serial interface device by the 3rd Asynchronous Serial Interface.
The present invention proposes a kind of new extended universal asynchronous serial interface method, device and system, distinguish the data of two universal asynchronous serial interfaces, can significantly reduce cost and can not take other bus resources by first bit that data byte is set.UART only needs 2 signal TXD and RXD can realize above function in addition, does not need other signal wire, does not also need to interrupt, and realizes more simple.
Description of drawings
Fig. 1 is a UART Universal Asynchronous Receiver Transmitter signal wire synoptic diagram
Fig. 2 is existing universal asynchronous serial interface extended method one synoptic diagram
Fig. 3 is existing universal asynchronous serial interface extended method two synoptic diagram
Fig. 4 is existing universal asynchronous serial interface extended method three synoptic diagram
Fig. 5 is a kind of extended universal asynchronous serial interface method of reseptance of the present invention embodiment one synoptic diagram
Fig. 6 is a kind of extended universal asynchronous serial interface method of reseptance of the present invention embodiment two synoptic diagram
Fig. 7 is a kind of extended universal asynchronous serial interface method of reseptance of the present invention embodiment three synoptic diagram
Fig. 8 is a kind of extended universal asynchronous serial interface sending method of the present invention embodiment one synoptic diagram
Fig. 9 is a kind of extended universal asynchronous serial interface sending method of the present invention embodiment two synoptic diagram
Figure 10 is a kind of extended universal asynchronous serial interface sending method of the present invention embodiment three synoptic diagram
Figure 11 is a kind of extended universal asynchronous serial interface sending method of the present invention embodiment four synoptic diagram
Figure 12 is a kind of extended universal asynchronous serial interface receiving trap of the present invention embodiment one synoptic diagram
Figure 13 is a kind of extended universal asynchronous serial interface receiving trap of the present invention embodiment two synoptic diagram
Figure 14 is a kind of extended universal asynchronous serial interface receiving system of the present invention embodiment synoptic diagram
Figure 15 is a kind of extended universal asynchronous serial interface dispensing device of the present invention embodiment one synoptic diagram
Figure 16 is a kind of extended universal asynchronous serial interface dispensing device of the present invention embodiment two synoptic diagram
Figure 17 is a kind of extended universal asynchronous serial interface transmitting system of the present invention embodiment synoptic diagram
Figure 18 is a kind of extended universal asynchronous serial interface device of the present invention embodiment synoptic diagram
Figure 19 is a kind of extended universal asynchronous serial interface system embodiment of the present invention synoptic diagram
Figure 20 is a kind of extended universal asynchronous serial interface system architecture of the present invention and annexation one synoptic diagram
Figure 21 is a kind of extended universal asynchronous serial interface system architecture of the present invention and annexation two synoptic diagram
Embodiment
The invention provides a kind of extended universal asynchronous serial interface method, device and system, the present invention will be described in detail below in conjunction with accompanying drawing.
Fig. 5 has provided a kind of extended universal asynchronous serial interface method of reseptance of the present invention embodiment one synoptic diagram, and described method comprises:
Step S1 receives the data that central processor CPU is sent from first Asynchronous Serial Interface;
Step S2, first bit of each data byte in the judgment data (be called for short bit1) is 0 or 1, if first bit is 0 then execution in step S3, if first bit is 1 then execution in step S4;
Step S3 sends to first interfacing equipment with described data byte from second Asynchronous Serial Interface;
Step S4 sends to second interfacing equipment with described data byte from the 3rd Asynchronous Serial Interface.
Wherein first Asynchronous Serial Interface can be original UART interface UART1, two UART interface UART2 that second Asynchronous Serial Interface and the 3rd Asynchronous Serial Interface can obtain for expansion and UART3.Described first interfacing equipment and second interfacing equipment can be equipment such as interface card or PC.
Distinguish the data of two universal asynchronous serial interfaces by first bit of data byte, can significantly reduce cost and can not take other bus resources.The data of two universal asynchronous serial interfaces that expansion obtains can receive at any time, also can not send invalid data simultaneously when two universal asynchronous serial interfaces have data to send, and can reduce the burden of CPU and related device.UART only needs 2 signal TXD and RXD can realize above function in addition, does not need other signal wire, does not also need to interrupt, and realizes more simple.
Fig. 6 has provided a kind of extended universal asynchronous serial interface method of reseptance of the present invention embodiment two synoptic diagram, and present embodiment also comprised before step S1 except the step that comprises method of reseptance embodiment one:
First bit that step S5, CPU send to each data byte in the data of first interfacing equipment is set to 0, and first bit that sends to each data byte in the data of second interfacing equipment is set to 1;
Step S6, CPU sends data from first Asynchronous Serial Interface.
The baud rate that for example can set the first Asynchronous Serial Interface UART2 and the second Asynchronous Serial Interface UART3 is a fixed value and identical, as 9600, represents that promptly p.s., the bit number of transmission was 9600.The baud rate of setting UART1 simultaneously is UART2 and UART3 2 times.
When CPU sends, if be provided with bit1 be 0 the expression data give UART2, if bit1 be 1 the expression data send to UART3.
Fig. 7 has provided a kind of extended universal asynchronous serial interface method of reseptance of the present invention embodiment three synoptic diagram, present embodiment except the step that comprises method of reseptance embodiment two,
Also comprise after step S5: step S7, CPU insert a slack byte behind each data byte; Before step S2, also comprise: step S8, detect whether each data byte is slack byte in the data that receive, if then abandon described data byte and continue to judge next data byte.
Described slack byte can be the ASCII character byte that is " 0x00 ", the speed of the actual transmission of CPU has only half of baud rate like this, also the speed that promptly sends is exactly the baud rate of UART2 and UART3, also can not cause losing of UART2 and UART3 data even send at full speed.
For example when receiving the data of CPU transmission, at first judge whether to be slack byte " 0x00 ", if just abandon this data byte.If then judgement bit1 is 0 then sends to UART2, if bit1 is 1 then sends to UART3.
Fig. 8 has provided a kind of extended universal asynchronous serial interface sending method of the present invention embodiment one synoptic diagram, and described method comprises:
Step T1 receives the data that first interfacing equipment is sent from second Asynchronous Serial Interface;
Step T2 receives the data that second interfacing equipment is sent from the 3rd Asynchronous Serial Interface;
Step T3, to from the data that second Asynchronous Serial Interface receives, replace with 0 by first bit of each data byte, to from the data that the 3rd Asynchronous Serial Interface receives, replace with 1 by first bit of each data byte, and send to CPU from first Asynchronous Serial Interface.
For example when receiving the data of UART2, its bit1 is replaced with 0 send to CPU, the data that receive UART3 replace with 1 with its bit1 and send to CPU.Because the baud rate of UART1 is 2 times of UART2 and UART3, therefore can not produce losing of data.
Step T1 can carry out before step T2, also can carry out after step T2, perhaps carried out synchronously with step T2.
Distinguish the data of two universal asynchronous serial interfaces by first bit of data byte, can significantly reduce cost and can not take other bus resources.The data of two universal asynchronous serial interfaces that expansion obtains can send at any time, also can not send invalid data simultaneously when two universal asynchronous serial interfaces have data to send, and can reduce the burden of CPU and related device.UART only needs 2 signal TXD and RXD can realize above function in addition, does not need other signal wire, does not also need to interrupt, and realizes more simple.
Fig. 9 has provided a kind of extended universal asynchronous serial interface sending method of the present invention embodiment two synoptic diagram, and present embodiment also comprises after step T3 except the step that comprises sending method embodiment one:
Step T4, CPU handles data respectively according to first bit of described data byte.
Figure 10 has provided a kind of extended universal asynchronous serial interface sending method of the present invention embodiment three synoptic diagram, present embodiment except the step that comprises sending method embodiment one,
After step T1, also comprise: step T5, carry out buffer memory according to the mode of first in first out to described data, according to proposing time of arrival of data first request for arbitration;
After step T2, also comprise: step T6, carry out buffer memory according to the mode of first in first out to described data, according to proposing time of arrival of data second request for arbitration.
Present embodiment can also carry out above-mentioned expansion except carrying out the above-mentioned expansion on the basis of sending method embodiment two on the basis of sending method embodiment one.
Can guarantee that by data being carried out buffer memory the data that receive do not lose, owing to do not need to receive by interrupt notification CPU, but data directly send to CPU when arriving, and cache size therefore required for the present invention is less.
Figure 11 has provided a kind of extended universal asynchronous serial interface sending method of the present invention embodiment four synoptic diagram, present embodiment is except the step that comprises sending method embodiment four, after step T5 and step T6, also comprise: step T7, if first request for arbitration and second request for arbitration arrive simultaneously, then will send from the high priority data that second Asynchronous Serial Interface receives.
Arbitrate by the data that different universal asynchronous serial interfaces are arrived, guaranteed that data can send to CPU in an orderly manner, prevent to produce the problem that causes because of data transmission collision.
This programme does not have the notion of time slot, because do not have clock and frame start-stop signal, have no idea to divide time slot, therefore the data of UART2 and UART3 can send and receive at any time, simultaneously when UART2 or UART3 have data to send, invalid data can be do not sent yet, the burden of CPU can be reduced.UART only needs 2 signal TXD and RXD can realize above function in addition, does not need other signal wire, does not also need to interrupt, and realizes more simple.
Figure 12 has provided a kind of extended universal asynchronous serial interface receiving trap of the present invention embodiment one synoptic diagram, and described device comprises receiver module M1, judge module M2, the first interface sending module M3 and the second interface sending module M4,
Described receiver module M1 is used for receiving the data that CPU sends from first Asynchronous Serial Interface;
Described judge module M2 is connected with receiver module M1, first bit that is used for each data byte of judgment data is 0 or 1, if first bit is 0 then gives the first interface sending module M3 with data byte and handle, if first bit is 1 then gives the second interface sending module M4 with data byte and handle;
The described first interface sending module M3 is connected with judge module M2, is used for described data byte is sent to first interfacing equipment from second Asynchronous Serial Interface;
The described second interface sending module M4 is connected with judge module M2, is used for described data byte is sent to second interfacing equipment from the 3rd Asynchronous Serial Interface.
Described extended universal asynchronous serial interface receiving trap can be at CPLD (Complex Programmable Logic Device, be called for short CPLD)/realize in field programmable gate array (field-programmable gate array the is called for short FPGA) device.
CPLD/FPGA is a kind of user according to needs separately and the digital integrated circuit of constitutive logic function voluntarily.Its basic design method is by the integrated platform that develops software, and with methods such as schematic diagram, hardware description languages, generates corresponding file destination, by download cable code is sent in the objective chip, realizes the digital display circuit of design.
Figure 13 has provided a kind of extended universal asynchronous serial interface receiving trap of the present invention embodiment two synoptic diagram, present embodiment is except the architectural feature that comprises receiving trap embodiment one, also comprise detection module M5, be connected with judging treatmenting module M2 with receiver module M1, be used for detecting whether each data byte of data that receives is slack byte, judge next data byte if then abandon described data byte and continue, handle otherwise give judging treatmenting module with data byte.
Figure 14 has provided a kind of extended universal asynchronous serial interface receiving system of the present invention embodiment synoptic diagram, present embodiment is except the architectural feature that comprises receiving trap embodiment one, also comprise CPU, be connected with described device, first bit that is used for sending to each data byte of data of first interfacing equipment is set to 0, inserts a slack byte behind each data byte; First bit that sends to each data byte in the data of second interfacing equipment is set to 1, inserts a slack byte behind each data byte, and sends data from first Asynchronous Serial Interface.
Present embodiment can also carry out above-mentioned expansion except can carry out above-mentioned expansion on the basis of receiving trap embodiment one on the basis of receiving trap embodiment two.
Figure 15 has provided a kind of extended universal asynchronous serial interface dispensing device of the present invention embodiment one synoptic diagram, and described device comprises the first interface receiver module N1, the second interface receiver module N2 and main sending module N3;
The described first interface receiver module N1 is used for receiving the data that first interfacing equipment is sent from second Asynchronous Serial Interface, and gives main sending module N3 and handle;
The described second interface receiver module N2 is used for receiving the data that second interfacing equipment is sent from the 3rd Asynchronous Serial Interface, and gives main sending module N3 and handle;
Described main sending module N3 is connected with the second interface receiver module N2 with the first interface receiver module N1, first bit that is used for each data byte of data that will receive from the first interface receiver module replaces with 0, to from the data that the second interface receiver module receives, replace with 1 by first bit of each data byte, and send to CPU from first Asynchronous Serial Interface.
Described extended universal asynchronous serial interface dispensing device can be realized in the CPLD/FPGA device.
Figure 16 has provided a kind of extended universal asynchronous serial interface dispensing device of the present invention embodiment two synoptic diagram, and present embodiment also comprises the first cache module N4, the second cache module N5 and arbitration modules N6 except the architectural feature that comprises dispensing device embodiment one;
The described first cache module N4 is connected with the first interface receiver module N1, is used for after the first interface receiver module receives data data being carried out buffer memory, according to proposing time of arrival of data first request for arbitration;
The described second cache module N5 is connected with the second interface receiver module N2, is used for after the second interface receiver module receives data data being carried out buffer memory, according to proposing time of arrival of data second request for arbitration;
Described arbitration modules N6 is connected with the second cache module N5 with main sending module N3, the first cache module N4, be used to arbitrate:, then will send from the high priority data that second Asynchronous Serial Interface receives if first request for arbitration and second request for arbitration arrive simultaneously.
Figure 17 has provided a kind of extended universal asynchronous serial interface transmitting system of the present invention embodiment synoptic diagram, present embodiment is except the architectural feature that comprises dispensing device embodiment one, also comprise CPU, be connected with described device, be used for respectively data being handled according to first bit of described data byte.
Present embodiment can also carry out above-mentioned expansion except can carry out above-mentioned expansion on the basis of dispensing device embodiment one on the basis of dispensing device embodiment two.
Figure 18 has provided a kind of extended universal asynchronous serial interface device of the present invention embodiment synoptic diagram, comprises above-mentioned any one extended universal asynchronous serial interface receiving trap and extended universal asynchronous serial interface dispensing device.
Described extended universal asynchronous serial interface device can be realized in the CPLD/FPGA device.
Figure 19 has provided a kind of extended universal asynchronous serial interface system embodiment of the present invention synoptic diagram, comprises above-mentioned extended universal asynchronous serial interface device, also comprises CPU, first interfacing equipment and second interfacing equipment,
Described CPU is connected with described extended universal asynchronous serial interface device, and first bit that is used for sending to each data byte of data of first interfacing equipment is set to 0, inserts a slack byte behind each data byte; First bit that sends to each data byte in the data of second interfacing equipment is set to 1, inserts a slack byte behind each data byte, and sends data from first Asynchronous Serial Interface; Also be used for respectively data being handled according to first bit of described data byte;
Described first interfacing equipment is connected with described extended universal asynchronous serial interface device by second Asynchronous Serial Interface;
Described second interfacing equipment is connected with described extended universal asynchronous serial interface device by the 3rd Asynchronous Serial Interface.
Figure 20 has provided a kind of extended universal asynchronous serial interface system architecture of the present invention and annexation one synoptic diagram, CPLD/FPGA is the extended universal asynchronous serial interface device among the present invention among the figure, UART1 is first Asynchronous Serial Interface, UART2 is second Asynchronous Serial Interface, UART3 is the 3rd Asynchronous Serial Interface, interface card is first interfacing equipment, and PC is second interfacing equipment.
Figure 21 has provided a kind of extended universal asynchronous serial interface system architecture of the present invention and annexation two synoptic diagram, CPLD/FPGA is the extended universal asynchronous serial interface device among the present invention among the figure, comprise: main receiving element, be used for receiving the data of CPU, and send to UART2 transmitting element or UART3 transmitting element from UART1 TXD signal wire; The UART2 transmitting element, the data that are used for receiving from main receiving element send to interface card 1 by UART2 TXD signal wire; The UART3 transmitting element, the data that are used for receiving from main receiving element send to interface card 2 by UART3 TXD signal wire; The UART2 receiving element is used for receiving data by UART2 RXD signal wire from interface card 1, and sends to main transmitting element; The UART3 receiving element is used for receiving data by UART3 RXD signal wire from interface card 2, and sends to main transmitting element; Main transmitting element is used for and will sends to CPU by UART2 RXD signal wire from UART1 receiving element and the single data of not having reception of UART2 reception; UART1 is first Asynchronous Serial Interface, and UART2 is second Asynchronous Serial Interface, and UART3 is the 3rd Asynchronous Serial Interface, and interface card 1 is first interfacing equipment, and interface card 2 is second interfacing equipment.
Concrete data processing step when CPU sends can for:
1, when CPU sends, if be provided with bit1 be 0 the expression data give UART2, if bit1 be 1 the expression data send to UART3; CPU inserts the slack byte that ASCII character is " 0x00 " after sending a byte.
2, whether be " 0x00 " to the main receiving element of CPLD/FPGA if receiving that data that CPU sends at first detect, if then abandon; If not then entering next step processing.
3, then detect bit1, if be 0 then give the first interface transmitting element and send; If be 1 then give the second interface transmitting element and handle.
4, the first interface transmitting element and the second interface transmitting element send out CPLD/FPGA with data.
Concrete data processing step when CPU receives can for:
1, the first interface receiving element and the second interface receiving element at first carry out buffer memory to the data that receive from UART2 and UART3 buffer unit, and application sends to main transmitting element then.
2, by arbitration unit the data in the buffer memory are handled, treatment principle is when the data of UART2 and UART3 arrive simultaneously, and the data of acquiescence UART2 send to main transmitting element earlier, send after the data of UART3.When the asynchronous arrival of data, the data that arrive first send earlier, after to wait in line.
3, main transmitting element replaces with 0 and 1 respectively with bit1 in the data of UART2 and UART3, sends to CPU.
4, CPU is that 0 or 1 pair of data is handled respectively according to bit1.
The present invention proposes a kind of new extended universal asynchronous serial interface method, device and system, can significantly reduce cost and can not take other bus resources.The data of two universal asynchronous serial interfaces that expansion obtains can send and receive at any time, simultaneously when two universal asynchronous serial interfaces have data to send, invalid data can be do not sent yet, the burden of CPU and related device such as CPLD/FPGA can be reduced.UART only needs 2 signal TXD and RXD can realize above function in addition, does not need other signal wire, does not also need to interrupt, and realizes more simple.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (13)
1. an extended universal asynchronous serial interface method of reseptance is characterized in that, described method comprises:
Receive the data that central processor CPU is sent from first Asynchronous Serial Interface, first bit of each data byte is 0 or 1 in the judgment data, if first bit is 0 then described data byte is sent to first interfacing equipment from second Asynchronous Serial Interface, if first bit is 1 then described data byte is sent to second interfacing equipment from the 3rd Asynchronous Serial Interface.
2. method according to claim 1 is characterized in that, the described data of sending from first Asynchronous Serial Interface reception CPU also comprise before:
First bit that CPU sends to each data byte in the data of first interfacing equipment is set to 0, and first bit that sends to each data byte in the data of second interfacing equipment is set to 1, and sends data from first Asynchronous Serial Interface.
3. method according to claim 2 is characterized in that,
First bit that sends to each data byte in the data of first interfacing equipment at described CPU is set to 0, and first bit that sends to each data byte in the data of second interfacing equipment also comprises after being set to 1: CPU inserts a slack byte behind each data byte;
First bit of each data byte is also to comprise before 0 or 1 in described judgment data: detect whether each data byte is slack byte in the data that receive, if then abandon described data byte and continue to judge next data byte.
4. an extended universal asynchronous serial interface sending method is characterized in that, described method comprises:
Receive the data that first interfacing equipment is sent from second Asynchronous Serial Interface, first bit of each data byte in the data is replaced with 0, and send to CPU from first Asynchronous Serial Interface;
Receive the data that second interfacing equipment is sent from the 3rd Asynchronous Serial Interface, first bit of each data byte in the data is replaced with 1, and send to CPU from first Asynchronous Serial Interface.
5. method according to claim 4 is characterized in that, described method also comprises:
CPU handles data respectively according to first bit of described data byte.
6. according to claim 4 or 5 described methods, it is characterized in that,
Describedly also comprise after second Asynchronous Serial Interface receives the data that first interfacing equipment sends: the mode according to first in first out is carried out buffer memory to described data, according to proposing time of arrival of data first request for arbitration;
Describedly also comprise after the 3rd Asynchronous Serial Interface receives the data that second interfacing equipment sends: the mode according to first in first out is carried out buffer memory to described data, according to proposing time of arrival of data second request for arbitration.
7. method according to claim 6 is characterized in that, also comprises: if first request for arbitration and second request for arbitration arrive simultaneously, then will send from the high priority data that second Asynchronous Serial Interface receives.
8. an extended universal asynchronous serial interface receiving trap is characterized in that, described device comprises receiver module, judge module, the first interface sending module and the second interface sending module,
Described receiver module is used for receiving the data that CPU sends from first Asynchronous Serial Interface;
Described judge module is connected with receiver module, first bit that is used for each data byte of judgment data is 0 or 1, if first bit is 0 then gives the first interface sending module with data byte and handle, if first bit is 1 then gives the second interface sending module with data byte and handle;
The described first interface sending module is connected with judge module, is used for described data byte is sent to first interfacing equipment from second Asynchronous Serial Interface;
The described second interface sending module is connected with judge module, is used for described data byte is sent to second interfacing equipment from the 3rd Asynchronous Serial Interface.
9. device according to claim 8, it is characterized in that, described device also comprises detection module, be connected with judging treatmenting module with receiver module, be used for detecting whether each data byte of data that receives is slack byte, judge next data byte if then abandon described data byte and continue, handle otherwise give judging treatmenting module with data byte.
10. an extended universal asynchronous serial interface dispensing device is characterized in that, described device comprises the first interface receiver module, the second interface receiver module and main sending module;
The described first interface receiver module is used for receiving the data that first interfacing equipment is sent from second Asynchronous Serial Interface, and gives main sending module and handle;
The described second interface receiver module is used for receiving the data that second interfacing equipment is sent from the 3rd Asynchronous Serial Interface, and gives main sending module and handle;
Described main sending module is connected with the second interface receiver module with the first interface receiver module, first bit that is used for each data byte of data that will receive from the first interface receiver module replaces with 0, to from the data that the second interface receiver module receives, replace with 1 by first bit of each data byte, and send to CPU from first Asynchronous Serial Interface.
11. device according to claim 10 is characterized in that, described device also comprises first cache module, second cache module and arbitration modules;
Described first cache module is connected with the first interface receiver module, is used for after the first interface receiver module receives data data being carried out buffer memory, according to proposing time of arrival of data first request for arbitration;
Described second cache module is connected with the second interface receiver module, is used for after the second interface receiver module receives data data being carried out buffer memory, according to proposing time of arrival of data second request for arbitration;
Described arbitration modules is connected with main sending module, first cache module and second cache module, is used to arbitrate: if first request for arbitration and second request for arbitration arrive simultaneously, then will send from the high priority data that second Asynchronous Serial Interface receives.
12. extended universal asynchronous serial interface device that comprises claim 8 or 9 described extended universal asynchronous serial interface receiving traps and claim 10 or 11 described extended universal asynchronous serial interface dispensing devices.
13. an extended universal asynchronous serial interface system that comprises the described device of claim 12 is characterized in that described system also comprises CPU, first interfacing equipment and second interfacing equipment,
Described CPU is connected with described extended universal asynchronous serial interface device, and first bit that is used for sending to each data byte of data of first interfacing equipment is set to 0, inserts a slack byte behind each data byte; First bit that sends to each data byte in the data of second interfacing equipment is set to 1, inserts a slack byte behind each data byte, and sends data from first Asynchronous Serial Interface; Also be used for respectively data being handled according to first bit of described data byte;
Described first interfacing equipment is connected with described extended universal asynchronous serial interface device by second Asynchronous Serial Interface;
Described second interfacing equipment is connected with described extended universal asynchronous serial interface device by the 3rd Asynchronous Serial Interface.
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| CN200910086862XA CN101576867B (en) | 2009-06-17 | 2009-06-17 | Extended universal asynchronous serial interface method, device and system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102313604A (en) * | 2011-07-12 | 2012-01-11 | 华南师范大学 | Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) |
| CN103049412A (en) * | 2011-10-15 | 2013-04-17 | 成都锐奕信息技术有限公司 | Asynchronous device with protection signal transmission function |
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2009
- 2009-06-17 CN CN200910086862XA patent/CN101576867B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102313604A (en) * | 2011-07-12 | 2012-01-11 | 华南师范大学 | Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) |
| CN102313604B (en) * | 2011-07-12 | 2014-04-09 | 华南师范大学 | Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) |
| CN103049412A (en) * | 2011-10-15 | 2013-04-17 | 成都锐奕信息技术有限公司 | Asynchronous device with protection signal transmission function |
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