KR100551168B1 - Packet error prevention device of CDM communication system - Google Patents

Abstract

The present invention extends the bit 8 signal indicating the start and end of the packet and minimizes packet breakage by preventing the loss of the bit 8 signal due to noise / error by assigning different start and end values of the extended bit 8 signal. The present invention relates to a packet error prevention device of a CD communication system which detects a packet error at a receiving end, and the present invention provides a receiving end when a packet start address output from a transmitting central processing unit is received at a packet start / end signal generation unit. It is generated by extending the bit 8 signal for notifying the start of the packet and the bit 8 signal for notifying the end of the packet so that the transport packet can be extracted. The signal is transmitted to the router indicating that the packet is ready for transmission. The router stores the data obtained by the first-in-first-out unit in packet units according to a signal indicating that the packet to be transmitted is obtained from the packet start / end signal generator, extracts the destination of the stored transport packet, and then transmits the packet to the corresponding destination. By routing the packet breakage can be minimized.

Description

Packet error prevention device of CDM communication system

The present invention relates to the prevention of packet errors in a code division multiple access (CDMA) communication system. In particular, the present invention extends the bit 8 signals indicating the start and end of a packet, and the start and end values of the extended bit 8 signal. The present invention relates to a packet error prevention device of a CD communication system which minimizes packet breakage by preventing a loss of a bit 8 signal due to noise / error and simultaneously detects a packet error at a receiving end.

In general, a code division multiple access system is a system for performing packet communication using a first-in first-out (FIFO). That is, the data is temporarily stored in packet units using the FIFO, and the stored data is output again in packet units.

In such a general CDMA communication system, packet data can be processed only by detecting the start and end of a packet during packet transmission. Therefore, the transmitting end transmits bit 8 (synchronous byte) set to "1" at the beginning and end of the packet. After receiving the sync byte, the receiving end detects the start "1" of the bit 8 and the end "1" of the bit 8 to extract the packet. That is, the receiving end recognizes data between the start "1" and the end "1" of the bit 8 as one packet.

In such a general CDMA communication system, if the receiving end is erroneously recognized by being deleted / added to bit 8 due to noise or other reasons, the receiving end is incorrectly recognized as both the start and the end of the received packet after the packet in error. Since the data cannot be processed, the call quality cannot be guaranteed.

That is, as shown in FIG. 1, when "1" is added to bit 8 by noise as shown in (b) in the normal packet as shown in (a), packet 1 is incorrectly recognized. , Packet 3, ..., packet n) are also misrecognized and data is lost, so the call quality cannot be guaranteed.

In addition, as shown in FIG. 2, the first packet (packet 1) is recognizable when "1" of bit 8 is deleted in the normal packet as shown in (a), for the reason of noise or other reasons as shown in (b). However, since the packet after the bit 8 is damaged cannot be extracted, data loss occurs, which causes a problem of degrading call quality.

Accordingly, the present invention has been proposed to solve various problems occurring in the general CDMA communication system as described above.

An object of the present invention is to extend a bit 8 signal indicating the start and end of a packet, and to give the start and end values of the extended bit 8 signal differently, thereby preventing loss of the bit 8 signal due to noise / error, thereby preventing the packet from being lost. It is to provide a packet error prevention device of a CD communication system that minimizes the break and at the same time to detect the packet error at the receiving end.

Technical idea of the present invention for achieving the above object,

In the case of packet communication using first-in-first-out, the transmission of bit 8 signal that indicates the start and end of the packet is extended from one to two times, and at the same time, the start and end of the bit 8 signal has continuity and the start and end with the continuity By differently assigning the bit 8 signal, it is possible to minimize packet breakage due to noise / error of the bit 8 signal during packet communication using the first-in, first-out.

An apparatus for preventing a packet error of the present invention according to the technical spirit as described above,

A transmitting central processing unit for generating packet data and an address to transmit;

When the packet transmission address is received from the transmitting central processing unit, the receiving end generates the extended bit 8 signal for notifying the beginning of the packet and the bit 8 signal for notifying the end of the packet so as to extract the transport packet, and notifies the router that the packet is ready for transmission. A packet start / end signal generator for transmitting a signal;

A first-in, first-out unit for inserting first-in first-out packet data by inserting a bit 8 signal generated by the packet start / end signal generator into the last bit of input byte unit data;

According to a signal indicating that a packet to be transmitted is obtained from the packet start / end signal generator, data obtained by the first-in-first-out unit is stored in packet units, the destination of the stored transport packet is extracted, and the transport packet is transmitted to the corresponding destination. It is characterized by its technical means consisting of routers that route.

In the above, when the packet transmission is completed to the extracted destination, the router transmits a signal indicating completion of packet transmission to the destination receiving central processing unit so that the destination receiving central processing unit accesses the transmitted packet.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above in detail.

3 is a block diagram of a packet error prevention apparatus of a CDMA communication system according to the present invention.

As shown in the drawing, when receiving the packet transmission address from the transmission central processing unit 10 generating the packet data (Data) and the address (Addr) to be transmitted, and receiving the packet transmission address from the transmission central processing unit 10, the receiving end may extract the transmission packet. A packet start / end signal generator 20 generating a start bit 8 signal and an end bit 8 signal extended so as to transmit a signal indicating that a packet to be transmitted to the router is ready, and the packet start / end signal generator A first-in, first-out unit 30 for first-in, first-out of the packet data by inserting the bit 8 signal generated in step 20 into the last bit of the input byte unit data, and the transmission start / end signal generation unit 20 to be transmitted. According to a signal indicating that the packet is ready, the data obtained by the first-in, first-out unit 30 are stored in packet units, and the destination of the stored transport packet is extracted and then sent to the corresponding destination. A router 40 for routing a song packet, a dual port RAM 50 for receiving and storing a packet transmitted through the router 40, and packet data received by the dual port RAM 50 are accessed and processed. It consists of a receiving central processing unit 60.

The operation of the packet error apparatus according to the present invention configured as described above will be described in detail with reference to FIGS. 4 to 6 as follows.

First, the transmitting central processing unit 10 of the transmitting end records packet data in units of bytes in the first-in, first-out unit 30 connected by a data bus for packet communication.

In this case, the transmission central processing unit 10 sets a specific address area (for example, 91000000 to 91000080) as an area of the first-in, first-out unit 30. At this time, the packet start / end signal generator 20 sets the specific address. A bit 8 signal is generated and transmitted to the first-in first-out section 30 so that " 1 " is written in bit 8 of the start address (91000000) in the area, and " 0 " is written in bit 8 of the address between the start address and the end address. Do it.

In addition, when the address obtained from the transmission central processing unit 10 is the end address, a bit 8 signal is generated such that "1" is recorded in the bit 8 of the last address 9100007f and the end address 91000080 before the end address 91000080. Then, the first-in, first-out unit 30 transmits a signal Pktrdy indicating that the packet is ready for transmission to the router 40.

That is, the packet start / end signal generation unit 20 has a bit 8 signal of " 1 " at the start address (91000000), the immediately preceding address (9100007F), and the end address (91000080) based on the timing as shown in FIG. Generate a bit 8 signal if possible. In this way, when the router 40 refers to the bit 8 signal when moving the packet from the first-in, first-out part 30, the flow of 10 (start)-> 11 (end)-> 10 (start)-> 11 (end) If the value of the bit 8 signal is different, the packet is regarded as damaged and discards the packet being transmitted, and the transmission first-in, first-out unit 20 is initialized to minimize damage and allow continuous communication.

Although not shown in the drawing, the timing of generating the bit 8 signal of the packet start / end signal generator 20 is shown in FIG. 4, and a program for implementing the bit 8 signal generating logic is as follows.

/ STCS = / TXFIFOCS * / PIAWE * / A7 * / A6 * / A5 * / A4 * / A3 * / A2 * / A1 * / A0 *;

/ ENDCS = / TXFIFOCS * / PIAWE * / A7 * / A6 * / A5 * / A4 * / A3 * / A2 * / A1 * / A0 *;

/ BEFOEND = / TXFIFOCS * / PIAWE * / A7 * / A6 * / A5 * / A4 * / A3 * / A2 * / A1 * / A0 *;

/ MIDCS = / TXFIFOCS * / PIAWE * / STCS * / ENDCS * / A7;

PKTRDY.D = 0;

PKTRDY.CLKF = ENDCS;

PKTRDY.SETF = / CHKEN * / RDYCLR + / RESET;

BIT.D = 1;

BIT.8CLKF = / (STCS * ENDCS * BEFOEND);

BIT8.RSTF = / MIDCS;

When the bit 8 signal is generated by the method of generating the bit 8 signal by the packet start / end signal generator 20 as described above, the packet is completed.

On the other hand, the first-in, first-out unit 30 outputs the input packet data by byte unit to the router 40 and at the same time transfers bit 8 data D [8] to the router 40.

Accordingly, when the signal Pktrdy indicating that the packet to be transmitted is asserted is asserted, the router 40 temporarily opens the internal buffer to temporarily store the packet data obtained from the first-in-first-out unit 30. Although not shown in the drawing, when the destination of the packet data is extracted from the destination extraction unit, the packet is transmitted to the destination.

In this case, since the router 40 cannot refer to the length of the packet during packet transmission, the router 40 starts from the beginning " 1 " with reference to the bit 8 signal D [8] obtained from the first-in, first-out part 30, and then the next " 1 " The first-in first-out section 30 fetches the transport packet data until it is detected. In this process, the Pktrdy signal is cleared at the start of packet transmission (to know when a new transport packet is prepared in the first-in, first-out), and at the end of packet transmission (end bit 8 signal is "1"). This signal (Done signal) is sent to the destination CPU to acknowledge the arrival of the packet and access the transport packet.

When the router 40 reads the packet recorded in the first-in-first-out unit 30, if the start flag is {10} and the end flag is not {11} and is detected as {10} due to noise, Since the bit 8 signal is damaged, the packet transmits a signal txfifoclr to the packet start / end signal generator 20 to clear the first-in, first-out part 30 of the transmitter.

At this time, in case of an error that can be considered, if there is an error in the start flag, {11} may be followed by {11} instead of {10}. In this case, the txfifoclr signal is transmitted to the packet start / end signal generator 20 so as to operate as described above to clear the first-in, first-out part 30 of the transmitter.

According to this logic, all the flags that can be referred to are only {10} and {11}, and the reference values by multiplication are only "1" and "0".

That is, the router 40 continues to transmit data after {10} comes in. When the next " 1 " arrives, the router 40 waits for the next bit 8 signal, and if the value of " 0 " In this case, the first-in, first-out unit clear control signal is transmitted to the packet start / end signal generator 20.

For example, assuming that a packet as shown in Fig. 6 is input to the router 40,

First, when a normal packet is transmitted (packet 0 of FIG. 6), three "1s" overlap each other, thereby minimizing an error due to noise. In the packet 1, the end flag becomes {10}, which is the same as the start flag. An error is detected and the first-in, first-out unit 30 is cleared, and at the same time, the reference value is also cleared.

In addition, when a noise enters the middle of a packet such as packet 2, an error is immediately detected in the case of a 1-bit error. In the case of a 2-bit error {11}, an error is detected by comparing with an end flag.

In addition, when the start flag is shifted 1 bit as in packet 3, no error is detected, whereas the error is limited to the packet, and the error does not affect the next packet, thereby minimizing the loss.

The following is a program for implementing a logic for clearing the first-in, first-out unit 30 after the router 40 references the bit 8 signal.

Bitdly.T = bit 8 Clocked by mclk;

bit 8 = D {8];

Compare_value = bit 8 * bitdly;

TXFIFOCLR = (compare_value o befo_value);

Befo_value rst_BY TXFIFOCLR;

The following is a program for implementing the logic for clearing the first-in, first-out unit 30 after the packet start / end signal generator 20 receives the first-in first-out unit 30 clear control signal from the router 40. .

TXCLR = / (/ TXIACLRB + / LRESETB + / TFCSB * / PIAWEB * A [7] * A [6] * A [5] * A [4] * A [3] * A [2] * A [1] * A [0];

Meanwhile, the dual port RAM 50 of the receiving end receives the packet data transmitted from the router 40 and temporarily stores the data, and when the data output request of the receiving central processing unit 60 requests the data bus, the data port is temporarily stored. It delivers to the receiving central processing unit 60 through.

In addition, when the Done signal indicating that the packet is transmitted from the router 40 is transmitted, the receiving central processing unit 60 accesses and processes the packet received by the dual port RAM 50.

7 is a diagram illustrating a packet structure for explaining another embodiment of the present invention.

When an error occurs in the bit 8 signal, the present invention can prevent the continuous breaking of the packet. However, at least one packet of data is discarded due to a bit or byte error.

The problem is that when the packet is transmitted, the central processing unit first writes a specific value (e.g., e7, 81) at the first-in, first-out address and end address, and checks the byte value (e &, 81) at that time. If there is a match, there may be a method of validly recognizing and transmitting the packet.

This method does a byte check only when an error is detected, and thus does not impede router performance.

The packet structure in the case of applying such complex error prevention first-in-first-out packet communication is as shown in FIG.

That is, if the end flag is detected and the value is not {11} but {10}, when byte data is read according to the flow, it matches the packet end data value 81. Therefore, the packet is recognized as the end of the packet and no error processing is performed. Send the packet.

As described above, the present invention has an effect of preventing continuous packet breaking even when an error occurs due to noise flowing into a bit 8 signal during packet communication using a first-in, first-out.

In addition, in the case of applying a packet structure for complex error prevention, it is possible to prevent the packet break even in the case of bit or byte error, thereby improving the communication quality of the system.

1 is a packet structure diagram for explaining data loss caused when " 1 " is added to bit 8 in a general CDMA communication system.

FIG. 2 is a packet structure diagram for explaining data loss occurring when " 1 " of bit 8 is deleted in a general CDMA communication system.

3 is a block diagram of an apparatus for preventing a packet error in a CDMA communication system according to the present invention;

4 is a timing diagram of a bit 8 signal in the present invention;

5 is a structural diagram of a transport packet for packet error prevention in the present invention;

Figure 6 is an example of a packet input to the router in the present invention,

7 is another structural diagram of a transport packet for packet error prevention in the present invention;

<Explanation of symbols for the main parts of the drawings>

10: transmitting central processing unit

20: packet start / end signal generation unit

30: first-in, first-out

40: router

50: dual port ram

60: receiving central processing unit

Claims (5)

In a CDA mobile communication system implementing packet communication using a first-in, first-out, A transmitting central processing unit for generating packet data and an address to transmit; When the packet transmission address is received from the transmitting central processing unit, the receiving end generates the extended bit 8 signal for notifying the beginning of the packet and the bit 8 signal for notifying the end of the packet so as to extract the transport packet, and notifies the router that the packet is ready for transmission. A packet start / end signal generator for transmitting a signal; A first-in, first-out unit for inserting first-in first-out packet data by inserting a bit 8 signal generated by the packet start / end signal generator into the last bit of input byte unit data; According to a signal indicating that a packet to be transmitted is obtained from the packet start / end signal generator, data obtained by the first-in-first-out unit is stored in packet units, the destination of the stored transport packet is extracted, and the transport packet is transmitted to the corresponding destination. Packet error prevention device of a CDA mobile communication system, characterized in that configured to include a router for routing. The bit start / end signal generation unit of claim 1, wherein the packet start / end signal generator generates a bit 8 signal as a bit 8 signal in addition to the packet start bit 8 signal and the packet end bit 8 signal. Packet error prevention device of a CDA mobile communication system, characterized in that generated by extending the bit 8 signal. The control signal according to claim 1, wherein the router stops packet transmission when an error occurs in the bit 8 signal after detecting the bit 8 signal, and sends a control signal to clear the first-in, first-out part to the packet start / end signal generation unit. Packet error prevention device of a CDA mobile communication system, characterized in that it generates. The method according to claim 1 or 3, wherein the router transmits a signal indicating completion of packet transmission to the destination receiving central processing unit when the packet transmission is completed to the extracted destination so that the destination receiving central processing unit can access the transmitted packet. Packet error prevention device of a CDA mobile communication system, characterized in that. The method of claim 1, wherein the packet start / end signal generator records specific values (e7, 81) at the start address and the end address of the packet so that the packet can be recognized effectively even when an error of the bit 8 signal occurs. Packet error prevention device of the CD M mobile communication system.