KR20010019279A - Method of forming pad electrodes using self-aligned contact - Google Patents

Abstract

PURPOSE: A method for forming a pad electrode by using a self-aligned contact is provided to reduce a loss of a nitride layer enclosing a gate electrode. CONSTITUTION: A gate insulating layer, a conductive layer(104,106) and a nitride mask layer(108) are formed in sequence on a semiconductor substrate(100). The nitride mask layer(108) and the conductive layer(104,106) are then patterned to form a gate electrode(107). Next, a nitride spacer(110) is formed on a sidewall of the gate electrode(107). Thereafter, an interlayer dielectric layer(112) and an etch stopping layer(114) are sequentially deposited on a resultant structure and partially etched. A polysilicon spacer(116) is then formed on sidewalls of the etch stopping layer(114) and the interlayer dielectric layer(112). Next, the interlayer dielectric layer(112) is etched by using the polysilicon spacer(116) as a mask, so that a self-aligned contact hole(117) is formed. Here, the polysilicon spacer(116) prevents a loss of the nitride mask layer(108) and the nitride spacer(110). Thereafter, a pad electrode is formed in the self-aligned contact hole(117).

Description

Method for forming pad electrodes using self-aligned contact

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a pad electrode using a self-aligned contact process.

The design rule of the highly integrated semiconductor memory device is decreasing from about 1 μm in the era of Mbit-class dynamic random access memory (DRAM) to about 0.15 μm in Gbit-class DRAM. Accordingly, the dimension of the contact hole, which is an electrical contact portion to the silicon substrate, is also gradually reduced, and the aspect ratio also tends to increase with the use of a three-dimensional capacitor structure in the vertical direction. The reduction of the contact hole diameter and the high aspect ratio are a great burden for the subsequent photolithography process. Design rules become a factor in defining process limits. Alignment tolerances in deep submicron design rules have become a major determinant of device fatal failures.

In particular, technological changes in DRAMs have concentrated all efforts to increase capacitance in a limited unit area, and thus have changed from an initial planar cell capacitor structure to a stacked or trenched capacitor structure. Meanwhile, even in the stacked capacitor structure, technological changes have been made in such a structure that the effective capacitor area can be increased, such as a cylinder type capacitor or a fin type capacitor.

In view of the process order, the change from the CUB (Capacitor Under Bit-line) structure in which the capacitor is formed before the bit line formation is changed from the Capacitor Over Bit-line (COB) structure in which the capacitor is formed after the bit line formation. It became. Since the COB structure forms the capacitor after the bit line is formed in comparison with the CUB structure, it is possible to form the capacitor irrespective of the margin of the bit line process, thereby having an excellent advantage of increasing the capacitance of the cell in a limited area. On the other hand, in the COB structure, since the gate, bit line, and interlayer insulating film are stacked, the contact hole is not opened because the aspect ratio of the buried contact hole for electrically connecting the storage node and the source region of the transistor is large. There is a problem. Accordingly, in order to easily form the bit line contact hole and the buried contact hole for electrically connecting the drain region and the bit line of the transistor, a landing pad on the active region of the memory cell, that is, the drain and source region of the transistor. A method of reducing the aspect ratio of contact holes by forming an electrode serving as a landing pad has been widely used. The pad electrode is typically formed of polysilicon doped with impurities.

1 and 2 are cross-sectional views illustrating a method of forming a pad electrode by a conventional pad contact process.

Referring to FIG. 1, the gate electrode 14 is formed on the semiconductor substrate 10, which is divided into an active region and a field region by the field oxide layer 12. After forming an oxide film or a nitride film (SiNx) spacer 16 on the sidewall of the gate electrode 14, source / drain regions (not shown) on the surface of the substrate 10 on both sides of the gate electrode 14 through an ion implantation process. To form.

An oxide film is deposited on top of the resultant to form an interlayer dielectric layer (ILD) 18. After the photoresist pattern 20 is formed to open a region where the contact hole is to be formed on the interlayer insulating layer 18 through a photolithography process, the interlayer insulating layer (using the photoresist pattern 20 as an etching mask) Etching 18) forms a contact hole 22 exposing the source / drain regions of the memory cell.

Referring to FIG. 2, foreign substances such as polymers existing on the sidewalls of the photoresist pattern 20 and the contact hole 22 are removed by an ashing and stripping process. After depositing a polysilicon layer on the resultant, the polysilicon layer is patterned by a photolithography process to form a pad electrode 24 electrically connected to the source / drain region through the contact hole 22.

In DRAM devices with a design rule of 0.15 μm or less, or MDL (Murged DRAM & Logic) devices in which DRAM cell areas and logic areas are formed on the same chip, bit line contact holes and investment contact holes are made to have ultra-fine dimensions of 0.1 μm or less. Should be implemented. According to the pad contact process described above, even when the photoresist flows during the photolithography process for defining the contact hole region, it is difficult to realize a contact hole of 0.2 μm or less.

Accordingly, a method of forming a pad electrode by a so-called self-aligned contact process for forming a contact hole using a step of a peripheral structure is currently applied. The self-aligned contact process does not require alignment margin because contact holes of various sizes can be formed without using a mask by the height of the surrounding structure, the thickness of the insulating layer at the position where the contact is to be formed, and the etching method. It is possible to form a fine contact hole without.

3 and 4 are cross-sectional views illustrating a method of forming a pad electrode by a conventional self-aligned contact process.

Referring to FIG. 3, a polysilicon layer 54, a tungsten silicide layer 56, and a nitride layer 58 are formed on the semiconductor substrate 50, which is divided into an active region and a field region by the field oxide layer 52. In order to deposit. After the nitride layer 58 is patterned by a photolithography process, the gate electrode 57 is formed by etching the tungsten silicide layer 56 and the polysilicon layer 54 using the patterned nitride layer 58 as an etching mask. do. After the nitride film spacers 56 are formed on the sidewalls of the gate electrode 57, source / drain regions (not shown) are formed on the surface of the substrate 50 on both sides of the gate electrode 57 through an ion implantation process. The nitride film spacer 56 acts as an etch stopping layer during the etching process for subsequent self-aligned contact formation.

An oxide film is deposited on the resultant to form an interlayer insulating layer 60. After the photoresist pattern 64 is formed to open the pad region on the interlayer insulating layer 60 through the photolithography process, the photoresist pattern 64 is used as an etch mask to have a high selectivity to the nitride film. The interlayer insulating layer 60 is etched under the conditions. As a result, a self-aligned contact hole 65 exposing the source / drain regions of the memory cell is formed.

Referring to FIG. 4, foreign substances such as the photoresist pattern 20 and the polymer are removed by an ashing and stripping process. After depositing a polysilicon film on top of the resultant, the polysilicon film is etched to the upper surface of the interlayer insulating layer 60 by etch back or chemical mechanical polishing (CMP) to self-align the contact hole 65. The pad electrode 66 is formed inside.

As the semiconductor device is highly integrated, not only the length of the gate electrode but also the space dimension between the gate electrode and the gate electrode is reduced, and accordingly, the thickness of the nitride spacer used as the etch stop layer must be reduced. In this case, since there is a limit in increasing the selectivity to the nitride layer during the etching process for forming the self-aligned contact, loss of the nitride layer spacer occurs. When the loss of the nitride spacer is severe, the thickness of the nitride film between the gate electrode and the self-aligned contact becomes very thin, resulting in an electrical short between the gate electrode and the self-aligned contact. In order to prevent such a problem, increasing the thickness of the nitride film spacer or the nitride film layer existing on the gate electrode, the space between the gate electrode and the gate electrode becomes narrow, voids when filling the oxide film as the interlayer insulating layer (void) ) Will occur.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the loss of a nitride film surrounding the gate electrode in forming the pad electrode by a self-aligned contact process.

1 and 2 are cross-sectional views illustrating a method of forming a pad electrode by a conventional pad contact process.

3 and 4 are cross-sectional views illustrating a method of forming a pad electrode by a conventional self-aligned contact process.

5 to 10 are cross-sectional views illustrating a method of forming a pad electrode using a self-aligned contact process according to the present invention.

<Description of the code | symbol about the principal part of drawing>

100 semiconductor substrate 102 field oxide film layer

104: polysilicon layer 106: tungsten silicide layer

108 nitride film mask layer 110 nitride film spacer

112: interlayer insulating layer 114: etch stop layer

116 polysilicon spacer 118 pad electrode

In order to achieve the above object, the present invention comprises the steps of sequentially forming a gate insulating layer, a conductive layer and a nitride film mask layer on the semiconductor substrate; Patterning the nitride mask layer and the conductive layer to form a gate electrode; Forming a nitride film spacer on sidewalls of the gate electrode; Sequentially depositing an interlayer insulating layer and an etch stop layer on top of the resultant; Partial etching the etch stop layer and the interlayer dielectric layer; Forming a polysilicon spacer on sidewalls of the etch stop layer and the interlayer insulating layer; Forming a self-aligned contact hole by etching the interlayer insulating layer using the polysilicon spacer as a mask; And depositing a polysilicon layer on top of the resultant, and etching the polysilicon layer to an upper surface of the interlayer insulating layer to form a pad electrode inside the self-aligned contact hole. It provides a method for producing.

Preferably, the partial etching of the etch stop layer and the interlayer insulating layer proceeds until the upper surface of the nitride mask layer is exposed.

Preferably, the etch stop layer is formed of a nitride film or a polysilicon film.

According to the present invention, by performing an etching process for forming a self-aligned contact using a polysilicon spacer having a selectivity to the nitride film, it is possible to prevent the loss of the nitride mask layer and the nitride film spacer surrounding the gate electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 to 10 are cross-sectional views illustrating a method of forming a pad electrode using a self-aligned contact process according to the present invention.

Referring to FIG. 5, the field oxide layer 102 is formed on the semiconductor substrate 100 by a conventional device isolation process, for example, a local oxidation of silicon (LOCOS) process or an improved LOCOS process. 100) is divided into an active area and a field area. After the gate oxide layer (not shown) is formed on the active region through the thermal oxidation process, the polysilicon layer 104, the tungsten silicide layer 106, and the nitride mask layer 108 are sequentially deposited on the gate oxide layer. do. The polysilicon layer 104 is doped with a high concentration of impurities by conventional doping processes such as diffusion processes, ion implantation processes or in-situ doping processes. Of course, other refractory metal silicides such as titanium silicide or tantalum silicide may be used instead of tungsten silicide.

After the photoresist pattern (not shown) defining the gate region is formed on the nitride mask layer 108 through a photolithography process, the nitride mask layer 108 is patterned using the photoresist pattern as an etching mask. After removing the photoresist pattern by an ashing and stripping process, the tungsten silicide layer 106 and the polysilicon layer 104 are etched using the patterned nitride mask layer 108 to form a gate electrode 107 having a polyside structure. do.

An oxide layer (not shown) is deposited to a thickness of about 50 to 200 kPa by a chemical vapor deposition (CVD) process at a temperature of about 750 占 폚 on top of the resultant on which the gate electrode 107 is formed. Subsequently, the nitride film 110 is deposited to a thickness of about 500 to 1000 Pa by a low pressure chemical vapor deposition (LPCVD) process on the oxide film layer, and the nitride film layer 110 is subjected to etching conditions having a high selectivity with respect to the oxide film. The entire surface is etched back to form nitride film spacers 110 on both sidewalls extending from the nitride film mask layer 108 to the gate electrode 107. In this case, the oxide layer acts as an etch stop layer when the nitride layer 110 is etched, thereby preventing the lower substrate 100 from being damaged.

Referring to FIG. 6, source / drain regions (not shown) are formed on the surface of the substrate 100 on both sides of the gate electrode 107 by implanting impurities using the nitride spacers 110 and the gate electrode 107 as ion implantation masks. ).

An oxide layer is deposited to a thickness of several thousand micrometers by a chemical vapor deposition process on top of the resultant to form an interlayer insulating layer 112. An etch stop layer 114 is formed by depositing a nitride film or a polysilicon film on the interlayer insulating layer 112 to a thickness of about 1000 mW by a low pressure chemical vapor deposition process. The etch stop layer 114 serves to prevent the underlying interlayer insulating layer 112 from being etched during the subsequent self-aligned contact etching process, and the polysilicon in consideration of the relationship with the layers to be formed in the subsequent process. It is preferable to form into a film.

Referring to FIG. 7, a photoresist pattern (not shown) is formed to open a self-aligned contact region on the etch stop layer 114 through a photolithography process. The etch stop layer 114 and the interlayer insulating layer 112 are partially etched using the photoresist pattern as an etch mask. Preferably, partial etching is performed until the upper surface of the nitride mask layer 108 is exposed.

Referring to FIG. 8, the polysilicon layer 116 is placed on top of the resultant by a low pressure chemical vapor deposition process at a thickness of 1/2 or less than the critical dimension of the self-aligned contact hole, for example, if the contact hole critical dimension is 0.3 μm, 1500 μs. It deposits with the following thickness. More preferably, polysilicon layer 116 is deposited to a thickness of about 1000-1500 GPa.

The polysilicon layer 116 is then etched back to form polysilicon spacers 116 on sidewalls extending from the etch stop layer 114 to the interlayer dielectric layer 112.

9, the self-aligned contact hole 117 is formed to expose the source / drain regions of the memory cell by etching the exposed interlayer insulating layer 112 using the polysilicon spacer 116 as an etching mask. do. In this case, the polysilicon spacer 116 having a high selectivity to the nitride layer serves to prevent the nitride mask layer 108 and the nitride layer spacer 110 from being lost. In addition, the etch stop layer 114 prevents the interlayer insulating layer 112 under the etching process during the etching process.

Referring to FIG. 10, a polysilicon layer 118 is deposited on top of the resultant to a thickness sufficient to fill the self-aligned contact hole 117, and then the top surface of the interlayer insulating layer 112 is exposed. The polysilicon layer 118 is etched by an etch back or chemical mechanical polishing process. As a result, the pad electrode 118 is formed in the self-aligned contact hole 117.

As described above, according to the present invention, an etching process for forming a self-aligned contact using a polysilicon spacer having a selectivity to a nitride film is performed to prevent loss of the nitride mask layer and the nitride film spacer surrounding the gate electrode. can do. Accordingly, even if the thickness of the nitride film spacer existing between the gate electrode and the self-aligned contact is reduced on the same design rule, the electrical insulation property can be enhanced.

In addition, since the space between the gate electrode and the gate electrode can be made wider by reducing the thickness of the nitride film spacer, the space can be filled with an interlayer insulating layer without generating voids.

In addition, reducing the thickness of the nitride spacer increases the bottom contact area of the self-aligned contact hole, thereby reducing the contact resistance.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (3)

Sequentially forming a gate insulating layer, a conductive layer, and a nitride film mask layer on the semiconductor substrate; Patterning the nitride mask layer and the conductive layer to form a gate electrode; Forming a nitride film spacer on sidewalls of the gate electrode; Sequentially depositing an interlayer insulating layer and an etch stop layer on top of the resultant; Partially etching the etch stop layer and the interlayer dielectric layer; Forming a polysilicon spacer on sidewalls of the etch stop layer and the interlayer insulating layer; Forming a self-aligned contact hole by etching the interlayer insulating layer using the polysilicon spacer as a mask; And Depositing a polysilicon layer on top of the resultant, and etching the polysilicon layer to an upper surface of the interlayer insulating layer to form a pad electrode in the self-aligned contact hole. Manufacturing method. The method of claim 1, wherein the etching of the etch stop layer and the interlayer insulating layer is performed until the upper surface of the nitride mask layer is exposed. The method of claim 1, wherein the etch stop layer is formed of a nitride film or a polysilicon film.