KR20000067132A - Method of manufacturing contact semiconductor device - Google Patents
Method of manufacturing contact semiconductor device Download PDFInfo
- Publication number
- KR20000067132A KR20000067132A KR1019990014667A KR19990014667A KR20000067132A KR 20000067132 A KR20000067132 A KR 20000067132A KR 1019990014667 A KR1019990014667 A KR 1019990014667A KR 19990014667 A KR19990014667 A KR 19990014667A KR 20000067132 A KR20000067132 A KR 20000067132A
- Authority
- KR
- South Korea
- Prior art keywords
- contact
- groove
- region
- semiconductor substrate
- insulating layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
Description
본 발명은 반도체 장치의 콘택 제조 방법에 관한 것으로서, 보다 상세하게는 메모리 셀 영역에 형성되는 셀 패드 콘택 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a contact of a semiconductor device, and more particularly, to a method for manufacturing a cell pad contact formed in a memory cell region.
일반적으로 고집적 메모리 장치의 디자인-룰은 1 메가비트(Mbit)-급 다이나믹 랜덤 억세스 메모리(dynamic random access memory; DRAM) 시대의 약 1μm 수준에서 기가비트(Gbit)-급 DRAM에서는 약 0.15μm 수준으로 작아지고 있다. 이에 따라, 실리콘 기판에 대한 전기적인 접촉부인 콘택홀의 치수도 점차 축소되고 있으며, 수직 방향으로는 3차원 캐패시터 구조 등을 사용함에 따라 종횡비(Aspect Ratio)도 점점 높아지는 경향을 보이고 있다. 이러한 콘택홀 직경의 축소 및 높은 종횡비는 후속의 사진식각 공정에 큰 부담이 되고 있다. 디자인-룰은 공정 한계를 나타내는 인자가 되는데, 딥-서브마이크론(deep submicron)급 디자인-룰에서의 정렬 공차(align tolerance)는 소자의 치명적인 오류(fail)를 결정하는 주된 요인이 되고 있다.In general, the design rules of high-density memory devices are as small as about 1μm in the age of 1 Mbit-class dynamic random access memory (DRAM) and about 0.15μm in Gbit-class DRAM. ought. Accordingly, the dimension of the contact hole, which is an electrical contact portion to the silicon substrate, is also gradually reduced, and the aspect ratio also tends to increase with the use of a three-dimensional capacitor structure in the vertical direction. The reduction of the contact hole diameter and the high aspect ratio are a great burden for the subsequent photolithography process. Design rules become a factor in defining process limits. Alignment tolerances in deep submicron-class design rules have become a major factor in determining device fatal failures.
특히, DRAM에서의 기술 변화는 한정된 단위 면적에서 캐패시턴스를 증대시키기 위해 모든 노력이 집중되어 왔고, 그에 따라 초기의 평면 셀 캐패시터 구조에서 스택형 또는 트렌치형 캐패시터 구조로 변화되어 왔다. 또한, 스택형 캐패시터 구조에서도 실린더(clyinder)형 캐패시터 또는 핀(fin)형 캐패시터 등과 같이 유효 캐패시터 면적을 증대시킬 수 있는 구조로 기술 변화가 이루어져 오고 있다.In particular, technological changes in DRAMs have concentrated all efforts to increase capacitance in a limited unit area, and thus have changed from an initial planar cell capacitor structure to a stacked or trenched capacitor structure. In addition, even in the stacked capacitor structure, technological changes have been made to a structure capable of increasing the effective capacitor area, such as a cylinder type capacitor or a fin type capacitor.
이러한 기술 변화를 공정 순서의 관점에서 살펴보면, 비트라인 형성 이전에 캐패시터가 형성되는 CUB(Capacitor Under Bit-line) 구조에서 비트라인 형성 이후에 캐패시터가 형성되는 COB(Capacitor Over Bit-line) 구조로 변경되었다. COB 구조는 CUB 구조와 대비하여 비트라인 형성 이후에 캐패시터를 형성하므로 비트라인 공정 마진에 관계없이 캐패시터를 형성하는 것이 가능하여 제한된 면적에서 셀의 캐패시턴스를 증대시킬 수 있다는 장점을 갖는다. 반면에, COB 구조는 게이트 전극과 비트라인 및 층간 절연막이 적층되어 있어 스토리지 전극과 트랜지스터의 소오스 영역을 전기적으로 접속시키기 위한 매몰 콘택홀(buried contact hole)의 종횡비가 크기 때문에 콘택이 오픈되지 못하는 문제가 발생한다. 이에 따라, 상기 매몰 콘택홀 및 트랜지스터의 드레인 영역과 비트라인을 전기적으로 접속시키기 위한 비트라인 콘택홀을 용이하게 형성하기 위하여, 메모리 셀 영역의 활성 영역 상부에 랜딩 패드(landing pad) 역할을 하는 도전층을 형성하여 이러한 콘택홀들의 종횡비를 감소시키는 셀 패드 콘택방법이 널리 사용되고 있다.In view of the process order, the change from the CUB (Capacitor Under Bit-line) structure in which the capacitor is formed before the bit line formation is changed from the Capacitor Over Bit-line (COB) structure in which the capacitor is formed after the bit line formation. It became. In contrast to the CUB structure, the COB structure forms a capacitor after the bit line is formed, so that a capacitor can be formed regardless of the margin of the bit line, thereby increasing the capacitance of the cell in a limited area. On the other hand, in the COB structure, since the gate electrode, the bit line, and the interlayer insulating layer are stacked, the contact cannot be opened because the aspect ratio of the buried contact hole for electrically connecting the storage electrode and the source region of the transistor is large. Occurs. Accordingly, in order to easily form a bit line contact hole for electrically connecting the buried contact hole and the drain region of the transistor and the bit line, a conductive pad may serve as a landing pad on the active region of the memory cell region. The cell pad contact method for forming a layer to reduce the aspect ratio of these contact holes is widely used.
도 1a 및 도 1b는 종래 방법에 따른 셀 패드 콘택 제조공정을 나타내는 단면도들이다.1A and 1B are cross-sectional views illustrating a cell pad contact manufacturing process according to a conventional method.
먼저 도 1a를 참조하면, 소자분리막(12)이 형성되어 있는 반도체 기판(10) 상에 폴리실리콘(14), 금속실리사이드(16), 측벽절연막(18)으로 구성된 게이트 영역(20)과 소오스 또는 드레인 영역으로서 기능하는 확산영역(도시되지 않음)을 형성하여 억세스 트랜지스터를 완성한다. 예컨대, 상기 금속실리사이드(16)는 티타늄(Ti)실리사이드 또는 코발트(Co)실리사이드이며, 측벽절연막(18)은 실리콘나이트라이드(SiN)로 이루어져 있다. 이어서, 상기 억세스 트랜지스터가 형성되어 있는 반도체 기판(10) 상에 층간절연막(22)을 증착한 뒤, 감광막 패턴(24)을 식각마스크로 이용하여 식각공정을 실시한다.Referring to FIG. 1A, the gate region 20 and the source or the gate region 20 including the polysilicon 14, the metal silicide 16, and the sidewall insulating layer 18 may be formed on the semiconductor substrate 10 on which the device isolation layer 12 is formed. A diffusion region (not shown) that functions as a drain region is formed to complete the access transistor. For example, the metal silicide 16 is titanium (Ti) silicide or cobalt (Co) silicide, and the sidewall insulating layer 18 is made of silicon nitride (SiN). Subsequently, after the interlayer insulating film 22 is deposited on the semiconductor substrate 10 on which the access transistor is formed, an etching process is performed using the photosensitive film pattern 24 as an etching mask.
그 결과, 상기 층간절연막(22)에는 상기 반도체 기판(10)의 소정영역, 보다 상세하게는 억세스 트랜지스터의 소오스 또는 드레인 영역을 노출시키는 개구(26)가 형성된다. 상기 개구(26)는 후속의 공정을 통해 상기 억세스 트랜지스터의 확산영역과 비트라인(또는 캐패시터의 하부전극)을 연결시키는 셀 패드 콘택이 형성되어질 영역이다.As a result, an opening 26 is formed in the interlayer insulating film 22 to expose a predetermined region of the semiconductor substrate 10, more specifically, a source or drain region of the access transistor. The opening 26 is a region where a cell pad contact is formed to connect the diffusion region of the access transistor and the bit line (or the lower electrode of the capacitor) through a subsequent process.
도 1b를 참조하면, 상기 개구(26)가 형성되어 있는 층간절연막(22) 상에 도전막, 예컨대 폴리실리콘을 증착한 뒤, 이를 사진식각공정으로 패터닝함으로써 셀 패드 콘택(28)을 완성한다.Referring to FIG. 1B, a conductive film such as polysilicon is deposited on the interlayer insulating layer 22 having the opening 26, and then patterned by a photolithography process to complete the cell pad contact 28.
그러나 상기와 같은 종래의 제조공정으로 셀 패드 콘택을 형성하기 위해서는, 통상적으로 패터닝된 감광막 패턴(24)의 리플로우 공정이 수행되며, 설령 감광막 리플로우 공정을 수행한다 하더라도 반도체 장치의 고집적화에 따른 미스얼라인으로 인하여 0.2㎛ 이하의 미세한 셀 패드 콘택은 구현하기 어려운 문제점이 있다. 또한, 상기한 제조공정을 통해서도 알 수 있듯이 두 번의 사진식각공정이 수반되어야 하므로 제조공정상의 번거로움이 있다.However, in order to form the cell pad contact in the conventional manufacturing process as described above, a reflow process of the patterned photoresist pattern 24 is generally performed, and even if the photoresist reflow process is performed, a miss due to high integration of the semiconductor device is performed. Due to the alignment, a fine cell pad contact of 0.2 μm or less is difficult to implement. In addition, as can be seen through the above-described manufacturing process, there are inconveniences in the manufacturing process because two photolithography processes must be involved.
도 2a 및 도 2b는 종래의 또 다른 방법에 따른 셀 패드 콘택 제조공정을 나타내는 단면도들이다.2A and 2B are cross-sectional views illustrating a cell pad contact manufacturing process according to still another conventional method.
먼저 도 2a를 참조하면, 반도체 기판(10)에 통상의 소자분리 공정을 실시하여 필드산화막(12)을 형성한 뒤, 폴리실리콘(14), 텅스텐 실리사이드(15), 실리콘나이트라이드(17) 및 절연막 스페이서(18)로 이루어진 게이트 영역(21)을 형성한다. 이어서, 도시되지는 않았으나 소오스/드레인 영역 및 비트라인을 형성한 뒤, 층간절연막(22)을 증착한다. 그리고 나서, 상기 층간절연막(22) 상부에 감광막(24) 패턴을 형성한 뒤, 이를 식각마스크로서 이용하여 상기 층간절연막(22)을 건식식각한다. 그 결과, 인접한 게이트 영역(21) 사이에 셀프-얼라인 개구(27)가 형성된다.Referring first to FIG. 2A, a field oxide film 12 is formed by performing a conventional device isolation process on a semiconductor substrate 10, and then polysilicon 14, tungsten silicide 15, silicon nitride 17, and the like. The gate region 21 made of the insulating film spacer 18 is formed. Subsequently, although not shown, the source / drain regions and the bit lines are formed, and then the interlayer insulating layer 22 is deposited. Then, after the photoresist layer 24 pattern is formed on the interlayer insulating layer 22, the interlayer insulating layer 22 is dry-etched using this as an etching mask. As a result, a self-aligned opening 27 is formed between the adjacent gate regions 21.
도 2b를 참조하면, 상기 개구(26)가 형성되어 있는 결과물의 상부에 폴리실리콘을 증착한 뒤, 이를 에치백함으로써 셀프-얼라인 셀 패드 콘택(29)을 형성한다.Referring to FIG. 2B, a self-aligned cell pad contact 29 is formed by depositing polysilicon on top of the resultant product in which the opening 26 is formed and then etching it back.
그러나 상기한 셀프-얼라인 셀 패드 콘택 제조방법에 따르면, 실리콘나이트라이드를 이용하여 측벽절연막을 형성하여야 하므로, 실리사이데이션(silicidation) 공정을 적용하기 어려운 문제점이 있다. 즉, 상기 방법으로는 실리콘나이트라이드와 같은 하드마스크를 사용하는 폴리사이드 게이트 또는 폴리실리콘 게이트를 형성할 경우에만 실시가능하므로, 코발트나 티타늄을 이용한 실리사이데이션 공정을 적용하는 제품에는 이용할 수 없는 단점이 있다.However, according to the above-described self-aligned cell pad contact manufacturing method, since the sidewall insulating layer must be formed using silicon nitride, it is difficult to apply a silicidation process. That is, the method can be performed only when forming a polyside gate or a polysilicon gate using a hard mask such as silicon nitride, and therefore cannot be used in a product applying a silicide process using cobalt or titanium. There is this.
따라서 본 발명의 목적은, 상기한 종래의 문제점을 해소할 수 있는 반도체 장치의 셀 패드 콘택 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a cell pad contact of a semiconductor device which can solve the above-mentioned conventional problems.
본 발명의 다른 목적은, 공정단계를 단순화시키면서도 보다 미세한 면적을 가지는 반도체 장치의 셀 패드 콘택 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method for manufacturing a cell pad contact of a semiconductor device having a smaller area while simplifying processing steps.
상기의 목적들을 달성하기 위해서 본 발명에서는, 트랜지스터가 형성되어 있는 반도체 기판 상에 층간절연막을 형성하는 단계와; 상기 층간절연막을 일정 두께만 식각하여 콘택을 형성하고자 하는 위치에 일정 깊이의 홈을 형성하는 단계와; 상기 홈의 내부에 측벽절연막을 형성한 뒤, 상기 측벽절연막을 구비한 홈의 패턴에 따라 상기 층간절연막을 하부로 완전히 식각하여 상기 반도체 기판의 소정영역에 이르는 콘택홀을 형성하는 단계와; 상기 콘택홀에 도전막을 채워넣음으로써, 미세한 콘택을 완성하는 단계를 포함함을 특징으로 하는 반도체 장치의 콘택 제조방법을 제공한다.In order to achieve the above objects, the present invention includes the steps of forming an interlayer insulating film on a semiconductor substrate on which a transistor is formed; Forming a groove having a predetermined depth at a position to form a contact by etching the interlayer insulating layer only by a predetermined thickness; Forming a contact hole reaching a predetermined region of the semiconductor substrate by forming a sidewall insulating film in the groove, and then completely etching the interlayer insulating film downward according to a pattern of the groove having the sidewall insulating film; And filling a conductive film into the contact hole, thereby completing a fine contact.
도 1a 및 도 1b는 종래 방법에 따른 셀 패드 콘택 제조공정을 나타내는 단면도들이다.1A and 1B are cross-sectional views illustrating a cell pad contact manufacturing process according to a conventional method.
도 2a 및 도 2b는 종래의 또 다른 방법에 따른 셀 패드 콘택 제조공정을 나타내는 단면도들이다.2A and 2B are cross-sectional views illustrating a cell pad contact manufacturing process according to still another conventional method.
도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 셀 패드 콘택 제조공정을 나타내는 단면도들이다.3A to 3D are cross-sectional views illustrating a cell pad contact manufacturing process according to an exemplary embodiment of the present invention.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다. 도면들중 동일한 구성요소들은 가능한한 어느 곳에서든지 동일한 부호들로 나타내고 있음에 유의해야 한다. 또한 본 발명의 요지를 불필요하게 흐릴 수 있는 공지 기능 및 구성에 대한 상세한 설명은 생략한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same elements in the figures are denoted by the same numerals wherever possible. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.
도 3a 내지 도 3e는 본 발명의 바람직한 실시예에 따른 콘택 제조방법을 나타내는 단면도들이다.3A to 3E are cross-sectional views illustrating a method for manufacturing a contact according to a preferred embodiment of the present invention.
먼저, 도 3a를 참조하면, 소자분리막(102)에 의해 활성영역 및 비활성영역이 정의되어 있는 반도체 기판(100)에 불순물이 도핑된 폴리실리콘등으로 이루어진 도전막(104), 금속실리사이드(106), 측벽절연막(108)으로 이루어진 게이트 영역(110) 및 소오스 및 드레인 영역으로서 기능하는 확산영역(도시되지 않음)을 형성하여 억세스 트랜지스터를 완성한다. 바람직하게는, 상기 금속실리사이드(106)는 티타늄, 코발트 또는 텅스텐등과 같은 고용융점 금속을 이용하여 형성한다. 그리고, 상기 측벽절연막(108)은 예컨대, 산화막 또는 실리콘나이트라이드등과 같은 절연물로 형성한다.First, referring to FIG. 3A, a conductive film 104 and a metal silicide 106 made of polysilicon doped with impurities in a semiconductor substrate 100 in which an active region and an inactive region are defined by an isolation layer 102. The gate transistor 110 formed of the sidewall insulating film 108 and a diffusion region (not shown) serving as the source and drain regions are formed to complete the access transistor. Preferably, the metal silicide 106 is formed using a high melting point metal such as titanium, cobalt or tungsten. The sidewall insulating film 108 is formed of an insulating material such as, for example, an oxide film or silicon nitride.
이어서, 상기 억세스 트랜지스터가 형성되어 있는 반도체 기판(100) 상에 예컨대, PSG(Phosphorus Silicon Glass), BPSG(Boron Phosphorus Silicon Glass) 또는 USG(Undoped Silicon Glass)등으로 층간절연막(112)을 형성한 뒤, 상기 층간절연막(112) 상에 제1폴리실리콘(114)을 증착한다. 그리고 나서, 감광막(116) 패턴을 식각마스크로서 이용하여 상기 제1폴리실리콘(114) 및 층간절연막(112)을 일부 하부로 식각한다. 그 결과 도시된 바와 같이, 상기 제1폴리실리콘(114)을 관통하며 층간절연막(112)의 소정영역에 이르는 얕은 홈(118)이 형성된다.Subsequently, the interlayer insulating layer 112 is formed on the semiconductor substrate 100 on which the access transistor is formed, for example, Phosphorus Silicon Glass (PSG), Boron Phosphorus Silicon Glass (BPSG), or Undoped Silicon Glass (USG). The first polysilicon 114 is deposited on the interlayer insulating layer 112. Then, the first polysilicon 114 and the interlayer insulating film 112 are etched to the lower part using the photosensitive film 116 pattern as an etching mask. As a result, a shallow groove 118 penetrating the first polysilicon 114 and reaching a predetermined region of the interlayer insulating film 112 is formed.
도 3b를 참조하면, 상기 결과물에 에싱(ashing) 및/또는 황산 스트립(strip) 공정을 실시하여 상기 감광막(116) 패턴 및 이물질을 완전히 제거한다. 그리고 나서, 상기 홈(118) 및 제1폴리실리콘(114) 상부에 전체적으로 제2폴리실리콘막을 증착한 뒤, 전면 에치백하여 상기 홈(118) 내부에 측벽절연막(120)을 형성한다.Referring to FIG. 3B, an ashing and / or sulfuric acid strip process may be performed on the resultant to completely remove the photoresist 116 pattern and the foreign matter. Then, the second polysilicon film is deposited on the groove 118 and the first polysilicon 114 as a whole, and then etched back to form a sidewall insulating film 120 in the groove 118.
도 3c를 참조하면, 상기 측벽절연막(120)이 형성되어 있는 홈(118) 하부로 상기 층간절연막(112)을 상기 반도체 기판(100)이 노출될때까지 완전히 식각한다. 이때, 식각공정은 C2F6또는 CH3F 가스를 이용하거나 C4F8/Ar/O2으로 이루어진 혼합가스를 이용하여 실시하는 것이 바람직하다.Referring to FIG. 3C, the interlayer insulating layer 112 is completely etched under the groove 118 in which the sidewall insulating layer 120 is formed until the semiconductor substrate 100 is exposed. In this case, the etching process is preferably carried out using a C 2 F 6 or CH 3 F gas or using a mixed gas consisting of C 4 F 8 / Ar / O 2 .
상기 식각공정을 완료한 결과, 상기 층간절연막(112)을 관통하며 상기 억세스 트랜지스터의 드레인 영역(또는 소오스)에 이르는 약 0.15㎛의 미세한 콘택홀(122)이 형성된다.As a result of completing the etching process, a fine contact hole 122 having a thickness of about 0.15 μm is formed through the interlayer insulating layer 112 and reaching the drain region (or source) of the access transistor.
도 3d를 참조하면, 콘택홀(122)이 형성되어 있는 상기 결과물의 상부에 예컨대, 폴리실리콘등의 도전물의 증착한다. 그리고 나서, 상기 도전물을 전면 에치백 또는 화학기계연마(Chemical Mechanical Polishing)를 실시하여 미세한 셀 패드 콘택(124)을 완성한다.Referring to FIG. 3D, a conductive material such as, for example, polysilicon is deposited on the resultant product in which the contact hole 122 is formed. Then, the conductive material is subjected to full etch back or chemical mechanical polishing to complete the fine cell pad contact 124.
상술한 바와 같이 본 발명에서는, 셀 패드 콘택을 형성하고자 하는 영역에 미리 스페이서를 구비한 홈을 형성한다. 그리고 나서, 상기 홈을 통해 셀 패드 콘택용 개구를 형성한 뒤, 도전물을 채움으로써 보다 미세한 셀 패드 콘택을 형성하게 된다.As described above, in the present invention, grooves having spacers are formed in advance in the region where the cell pad contacts are to be formed. Then, after the opening for the cell pad contact is formed through the groove, a finer cell pad contact is formed by filling the conductive material.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990014667A KR20000067132A (en) | 1999-04-23 | 1999-04-23 | Method of manufacturing contact semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990014667A KR20000067132A (en) | 1999-04-23 | 1999-04-23 | Method of manufacturing contact semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000067132A true KR20000067132A (en) | 2000-11-15 |
Family
ID=19581953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990014667A KR20000067132A (en) | 1999-04-23 | 1999-04-23 | Method of manufacturing contact semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000067132A (en) |
-
1999
- 1999-04-23 KR KR1019990014667A patent/KR20000067132A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5936272A (en) | DRAM transistor cells with a self-aligned storage electrode contact | |
| KR100726145B1 (en) | Method for fabricating semiconductor device | |
| KR100499175B1 (en) | Semiconductor device and method of manufacturing the same | |
| KR100363710B1 (en) | Semiconductor device with self-aligned contact structure and method of manufacturing the same | |
| KR20040067315A (en) | Semiconductor device and Method of manufacturing the same | |
| KR100327123B1 (en) | A method of fabricating dram cell capacitor | |
| KR20050000798A (en) | Semiconductor device and Method for manufacturing the same | |
| KR100383325B1 (en) | Wiring of semiconductor device for forming a self-aligned contact and Method of manufacturing the same | |
| US6184079B1 (en) | Method for fabricating a semiconductor device | |
| KR100448719B1 (en) | Semiconductor device and method for fabricating the same using damascene process | |
| GB2374458A (en) | Self aligned contact holes | |
| US6074955A (en) | Method of fabricating a node contact window of DRAM | |
| US6001682A (en) | Method of fabricating cylinder capacitors | |
| KR100273706B1 (en) | Method for manufacturing semiconductor device | |
| KR100906646B1 (en) | Semiconductor memory device and method for manufacturing the same | |
| KR20000007644A (en) | Fabricating method of nor flash memory device | |
| KR20000067132A (en) | Method of manufacturing contact semiconductor device | |
| KR0183742B1 (en) | Short nozzle for welding torch | |
| KR20000061305A (en) | Method for manufacturing semiconductor device | |
| KR20010046663A (en) | method of forming buried contact hole for use in capacitor lower electrode semiconductor memory device | |
| KR19990005450A (en) | Method of manufacturing semiconductor memory device | |
| JP2001230383A (en) | Method of manufacturing semiconductor integrated circuit device | |
| KR20050066164A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| KR100655071B1 (en) | semiconductor device fabricating method for reducing processing steps | |
| KR20020030173A (en) | Method for Fabricating of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |