KR20010018074A - a manufacturing method of a photo-mask for thin film transistor panels - Google Patents

Abstract

PURPOSE: A method of producing a photomask having a minute pattern smaller than resolving power of an exposure apparatus and used for a thin film transistor substrate is provided to realize great precision and a minimized producing time. CONSTITUTION: The method includes exposing one region, where the minute pattern(P') smaller than resolving power of the exposure apparatus and a slit(S') adjacent to the minute pattern(P') are to be formed, separately from the other regions for data lines(162,165,166) by differentiating spot sizes. A data on the minute pattern forms the first file, and a data on the other pattern forms the second file. After a photoresist layer is coated over an opaque layer formed on a transparent substrate, the photoresist layer is subjected to the primary exposing step like the pattern data in the second file and then subjected to the secondary exposing step like the minute pattern data in the first file. The photoresist layer is then patterned and the underlying opaque layer is etched. In particular, an electron beam has a spot size of 0.2 micrometer or more for the primary exposing step, but another spot size of 0.125 micrometer and less for the secondary exposing step.

Description

A manufacturing method of a photo-mask for thin film transistor panels

The present invention relates to a method for fabricating an optical mask for a thin film transistor substrate.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal is injected between two substrates, and the liquid crystal is moved by a voltage applied to an electrode formed on each of the two substrates.

One of the two substrates is a substrate including a thin film transistor, and a thin film transistor or a wiring is formed in the substrate by repeating a process of forming and photographing a thin film several times. In order to manufacture such thin film transistors, five or six masks are typically used, but a thin film transistor substrate is manufactured using four masks.

A method of reducing the number of masks by forming a film having a slit or transmittance having a smaller pattern than the resolution of an exposure machine in a mask, and forming a photosensitive film pattern having a medium thickness by using the same patterning pattern of one or more thin films in a single photolithography process Is being presented.

In the case of using a mask having a fine pattern, it is required to produce an optical mask in which a fine pattern having a high precision is formed in order to uniformly form a medium-thick photosensitive film pattern.

An object of the present invention is to produce a thin film transistor substrate photomask having a fine pattern smaller than the resolution of an exposure machine, while minimizing manufacturing time with high precision.

Another object of the present invention is to manufacture an optical mask for a thin film transistor substrate capable of leaving a photosensitive film of a specific portion in order to reduce the number of processes of the thin film transistor.

1 is a layout view of a thin film transistor substrate for a liquid crystal display device formed using a mask according to an embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor substrate shown in FIG. 1 taken along lines II-II 'and III-III';

4A is a layout view of a thin film transistor substrate in a first step of manufacturing in accordance with an embodiment of the invention,

4B and 4C are cross-sectional views taken along line IVb-IVb ′ and IVc-IVc ′ in FIG. 4A, respectively.

5A and 5B are cross-sectional views taken along the IVb-IVb 'line and the IVc-IVc' line in FIG. 4A, respectively, and are cross-sectional views of the next steps of FIGS. 4B and 4C.

6A is a layout view of a thin film transistor substrate in the next steps of FIGS. 5A and 5B;

6B and 6C are cross-sectional views taken along lines VIb-VIb ′ and VIc-VIc ′ in FIG. 6A, respectively.

7A, 8A, 9A and 7B, 8B, and 9B are cross-sectional views taken along the lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively, illustrating the following steps in the order of the process. ,

10A is a layout view of a thin film transistor substrate in the next steps of FIGS. 9A and 9B;

10B and 10C are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' in FIG. 10A, respectively.

FIG. 11 is a view illustrating a thin film transistor portion of a mask manufactured according to an embodiment of the present invention, and corresponds to portion A of FIG. 6A,

12A and 12B are diagrams each illustrating a file for a fine pattern of a data line unit and a channel unit for fabricating a mask according to an exemplary embodiment of the present invention.

In order to solve this problem, in the present invention, when exposing to form a mask pattern, the mask pattern is formed by exposing different portions of spots and portions to form a fine pattern smaller than the resolution of the exposure machine.

In the present invention, the first file forms information on the micro pattern portion corresponding to the mask pattern and smaller than the resolution of the exposure machine, and then forms a second file containing information on the other portions. After applying the photoresist film on the light shielding film formed on the transparent substrate, the photoresist film is first exposed according to the pattern information of the second file, and the photoresist film is second exposed according to the fine pattern information shown in the first file. The photoresist is patterned and the exposed light shielding layer is etched to form a mask pattern including a fine pattern.

In this case, the first and second exposures are preferably performed using an electron beam.

The electron beam used for the second exposure is preferably smaller in spot size than the electron beam used for the first exposure, the spot size of the electron beam used for the first exposure is 0.2 μm or more, and the electron used for the second exposure. The spot size of the beam is preferably 0.125 μm or less, which is half or less of the electron beam spot size used for the first exposure.

The pattern information of the first file and the second file is composed of a black portion and a white portion, the black portion of the file corresponds to a pattern, and the other portion is a white portion.

When exposing the photosensitive film by using an electron beam, when exposing to form a pattern of the second file, the photosensitive film is exposed by scanning the electron beam so that it touches other than the black portion of the second file, and exposing the fine pattern of the first file. When exposing to form, the electron beam reaches a black portion in the first pile so that the photosensitive film and the light shielding film corresponding to the portion can be removed. Therefore, since the slit is formed in the black pattern part of the first file in the mask, the first file is inverted with respect to the second file and exposed.

It is preferable that the width | variety of a fine pattern is 1.25 micrometers or less.

In the present invention, the file for the data wiring is formed and the file for the fine pattern portion is separately formed, exposing the entire shape of the data wiring to the electron beam of the usual spot size when manufacturing the mask, and then only the fine pattern portion for the spot size. Since light is exposed by a small electron beam, a precise mask pattern can be formed and the mask fabrication time is not required much.

First, a structure of a thin film transistor substrate for a liquid crystal display device formed using a mask according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

FIG. 1 is a layout view of a thin film transistor substrate for a liquid crystal display device formed using a mask according to an embodiment of the present invention, and FIGS. 2 and 3 are lines II-II ′ and III of the thin film transistor substrate shown in FIG. 1, respectively. A cross-sectional view taken along the line -III´.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22 and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. A gate electrode 26 of the thin film transistor that is part of the line 22, and a sustain electrode 28 that is parallel to the gate line 22 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. . The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

The gate wirings 22, 24, 26, and 28 may be formed as a single layer, but may be formed as a double layer or a triple layer. In the case where more than two layers are formed, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials, in particular, ITO used as a pixel electrode. This is because, in order to reinforce the pad part electrically connected to the outside, the pad part forms the wiring material and the pixel electrode material together. When the pixel electrode is formed of ITO, materials having good contact properties with ITO include chromium (Cr), molybdenum (Mo), titanium (Ti), tantalum (Ta), and the like, and Cr / Al (or Al alloy). The bilayer of or Al / Mo bilayer is mentioned as an example.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the contact layer patterns 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65, separated from the data line portions 62, 64, and 65, of the source electrode 65 with respect to the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 68 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 68 for the storage capacitor is also not formed. The channel portion between the source electrode 65 and the drain electrode 66 is formed in a bent open ring shape.

The data lines 62, 64, 65, 66, 68 may also be formed in a single layer like the gate lines 22, 24, 26, 28, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. have. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 forms the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. The contact holes 71, 73, and 74 are exposed, and the contact holes 72 are exposed to expose the gate pad 24 together with the gate insulating film 30. As shown in FIG. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO), and is physically and electrically connected to the drain electrode 66 through the contact hole 71 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 68 through the contact hole 74 to transmit an image signal to the conductor pattern 68. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact holes 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4A to 13C and FIGS. 1 to 3.

First, as shown in FIGS. 4A to 4C, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including a line 22, a gate pad 24, a gate electrode 26, and a sustain electrode 28 is formed.

Next, as shown in FIGS. 5A and 5B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. Continuously deposited to a thickness of 600 to 600 kPa, and then depositing a conductor layer 60 such as a metal to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then depositing a photoresist film 110 thereon at a thickness of 1 μm to 2 μm. Apply with

Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as illustrated in FIGS. 6B and 6C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. Preferably, the thickness of the first portion 114 is 1/4 or less of the thickness of the second portion 112, the thickness of the second portion is formed to be 1.6 to 1.9㎛, the thickness of the first portion is 4,000 It is good to form about 3,000Å which is below.

As such, there may be various methods of varying the thickness of the photoresist film according to the position, and a method of adjusting the dose of light by forming a slit with a fine pattern smaller than the resolution in the mask.

In this case, the fine pattern and the slit have a line width smaller than the resolution of the exposure machine, preferably a line width that is 1/2 or less of the resolution of the exposure machine, and may form the first portion 114 of the photoresist pattern by the light diffraction effect. Since the resolution of the exposure machine normally used in a liquid crystal display device is 2.4-4 micrometers, it is preferable to form the micro pattern or slit which has a line width of 1.25 micrometers or less in a mask.

When fabricating such a mask, the spot size of the electron beam is about 0.2 to 0.5 μm, and when such a spot size forms a fine pattern having a line width of 1.25 μm or less, it has an open ring shape. The fine pattern of the portion corresponding to the straight portion of the channel portion C can be formed smoothly, but the portion corresponding to the boundary of the oblique portion must be formed unevenly in a step shape. Therefore, it is not possible to form a precise mask pattern, it is difficult to uniformly form the thickness of the first portion 114 by using the mask thus manufactured.

In order to solve this problem, the pattern for the data wiring may be formed in the mask using the spot size of the electron beam of about 0.125μm, but in the case of using the electron beam with the spot size of 0.125μm, other parts except the fine pattern It takes a lot of time to scan the electron beam.

In order to solve such a problem, it is preferable to form the pattern by dividing the pattern into two steps when forming the data wiring pattern on the mask. That is, one step forms a fine pattern, and the other step forms a portion except the fine pattern. In this way, fine patterns can be formed precisely, and the time for scanning the electron beam can be saved.

Such a mask manufacturing method will be described in more detail later with reference to the drawings.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. At this time, the data line and the layers under the data line remain in the data wiring portion A, only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 in the remaining portion B. ) Must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 7A and 7B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in FIGS. 7A and 7B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, are used. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 68 have the same shape as the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 8A and 8B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

In this way, as shown in FIGS. 8A and 8B, the first portion 114 of the channel portion C is removed to reveal the source / drain conductor pattern 67 and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate the intermediate layer pattern under the source / drain conductor pattern 67 and the intermediate layer pattern under the storage capacitor conductor pattern 68, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C. As the method of ashing, plasma gas or microwave may be used, and the composition mainly used includes oxygen.

Next, as shown in FIGS. 9A and 9B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 under the etching are removed by etching. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 9B, a part of the semiconductor pattern 42 may be removed to reduce the thickness, and the second part 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

In addition, when the data line is formed of a material capable of dry etching, the thickness of the photoresist pattern is controlled to form the contact layer pattern, the semiconductor layer pattern, and the data line in one etching process without going through several intermediate processes as described above. can do. That is, during the etching of the metal layer 60, the contact layer 50, and the semiconductor layer 40 in the portion B, the photoresist pattern 114 and the contact layer 50 under the portion are etched in the C portion, and the photoresist pattern in the A portion. A condition for etching only part of the 112 may be selected and formed in one step.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 10A to 10C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 2,000 Å or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor, respectively. The exposed contact holes 71, 72, 73, 74 are formed.

Finally, as shown in FIGS. 1 to 3, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to form the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad. Form 86.

As described above, in the present exemplary embodiment, the data lines 62, 64, 65, 66, 68, the contact layer patterns 55, 56, 58, and the semiconductor patterns 42, 48 below them are formed using one mask. In this process, the source electrode 65 and the drain electrode 66 are separated to complete the channel portion C of the semiconductor pattern 42.

Next, as described above, a method for manufacturing a mask according to an embodiment of the present invention will be described in detail.

First, a mask manufactured according to an exemplary embodiment of the present invention will be described with reference to FIG. 11.

FIG. 11 is a plan view illustrating in detail a portion corresponding to portion A of FIG. 6A among the second masks.

As shown in FIG. 11, the mask includes data line portions 162, 165, and 166, and a channel portion on which fine patterns P ′ and slit S ′ are formed. At this time, the width of the fine pattern (P ′) and the slit (S ′) is formed to about 1.25μm smaller than the resolution of the exposure machine, leaving a thin photosensitive film pattern (114 in Fig. 6c) in the channel portion (C). However, in the manufacture of such a mask, the use of an electron beam having a spot size of 0.2 μm or more can provide a precise mask pattern, particularly in the bending portion when the channel portion C is formed in an open annular shape as in the present invention. If the mask pattern cannot be formed and an electron beam having a spot size of 0.125 µm is used, it takes a long time to form the mask pattern. In order to solve this problem, the optical mask is formed in two steps.

12A and 12B and FIG. 11 described above, a method of manufacturing a photomask for a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail.

12A and 12B are diagrams each illustrating a file for a data wiring part and a fine pattern of a channel part for fabricating a mask according to an exemplary embodiment of the present invention.

As shown in FIG. 12A, pattern information of the channel portion of the thin film transistor is formed as a first file. At this time, the pattern information in the file is displayed as a black part and a white part. In this file, the black pattern (S) becomes a slit in which the pattern information is inverted when making a mask, and the part between the black pattern (S) in the file ( P) is the part where a fine pattern will be formed in a mask. It is preferable to form the width of a pattern to 1.25 micrometers or less.

Next, as shown in FIG. 12B, a second file having information about the thin film transistors and the data lines 262, 265, and 266 is formed. Here, the portion corresponding to the channel of the thin film transistor is also black in one pattern connected to the data lines 262, 265, and 266, which is a portion in which a fine pattern and a slit are to be formed on the mask. Here, the pattern information of the second file is not reversed during mask preparation.

Subsequently, a mask is fabricated using the piles shown in FIGS. 12A and 12B. The mask substrate is one in which a chromium layer is formed on glass or quartz substrate.

A photosensitive film is applied on the chromium layer.

Next, the photosensitive film corresponding to the white portion is scanned and exposed with an electron beam having a spot size of 0.2 μm or more according to the pattern information as shown in FIG. 12B.

Next, the thin film transistor channel portion shown in FIG. 12A is exposed with an electron beam having a spot size of 0.125 μm or less. In this case, the electron beam reaches the black pattern S in FIG. 12A so that the photoresist film and the chromium layer corresponding to the black pattern S may be removed. Therefore, the pattern information of FIG. 12A is inverted with respect to FIG. 12B in the mask substrate. In other words, in FIG. 12B, portions except for the black portion are exposed, and the black portion is a pattern on the mask. In FIG. 12A, since the black pattern S is exposed, the portion P between the black patterns S of FIG. 12A is exposed. ) Becomes a fine pattern P 'of the transistor channel portion on the mask, and the black pattern S of FIG. 12A becomes a slit S' on the mask.

In the present embodiment, the pattern shown in FIG. 12B is first exposed and then the pattern shown in FIG. 12A is exposed. However, the pattern shown in FIG. 12A may be exposed first and then the pattern shown in FIG. 12B may be exposed.

Next, the photoresist film is developed, the exposed chromium layer is etched, and the remaining photoresist film is removed.

Then, a mask for the channel portion and the data lines 162, 165, and 166 as shown in FIG. 11 may be formed.

Such a mask manufacturing method has the following effects.

When fabricating a data wiring mask having a fine line width pattern smaller than the resolution of an exposure machine, it is formed in two steps, that is, forming a fine pattern portion and forming a portion except the fine pattern, so that it is precise and time consuming. Masks can be fabricated, and the number of manufacturing steps for the thin film transistor substrate can be reduced by using such a mask.

Claims (7)

Forming fine pattern information smaller than a resolution of the exposure machine into the first file, Forming pattern information other than the fine pattern into a second file; Applying a photoresist film on the photoresist film formed on the transparent substrate; First exposing the photosensitive film according to the pattern information of the second file, Second exposing the photosensitive film according to the fine pattern information of the first file, Patterning the photoresist to form a photoresist pattern; and And forming a mask pattern by etching the light shielding layer using the photoresist pattern as a mask. In claim 1, The photomask manufacturing method for thin film transistor substrates which exposes a said 1st exposure and a said 2nd exposure with an electron beam. In claim 2, The spot size of the electron beam used for the first exposure is larger than the spot size of the electron beam used for the second exposure. In claim 3, The spot size of the said electron beam used for the said 1st exposure is 0.2 micrometer or more, and the spot size of the electron beam used for the said 2nd exposure is 0.125 micrometer or less, The manufacturing method of the photomask for thin film transistor substrates. In claim 1, And said pattern information of said first file and said second file comprises a black portion and a white portion. In claim 5, And the second exposure inverts the pattern information of the first file and exposes the photomask. In claim 1, The photomask manufacturing method for thin film transistor substrates whose width | variety of the said micropattern is 1.25 micrometers or less.