KR20010011001A - Forming method for trench of semiconductor device - Google Patents
Forming method for trench of semiconductor device Download PDFInfo
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- KR20010011001A KR20010011001A KR1019990030176A KR19990030176A KR20010011001A KR 20010011001 A KR20010011001 A KR 20010011001A KR 1019990030176 A KR1019990030176 A KR 1019990030176A KR 19990030176 A KR19990030176 A KR 19990030176A KR 20010011001 A KR20010011001 A KR 20010011001A
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 56
- 125000006850 spacer group Chemical group 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 230000001939 inductive effect Effects 0.000 claims description 2
- 230000001052 transient effect Effects 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
Description
본 발명은 반도체소자의 트렌치 형성방법에 관한 것으로, 특히 트렌치를 이용한 소자분리공정에서 상기 트렌치의 상부를 라운딩시켜 소자의 전기적 특성을 향상시키는 반도체소자의 트렌치 형성방법에 관한 것이다.The present invention relates to a trench forming method of a semiconductor device, and more particularly to a trench forming method of a semiconductor device to improve the electrical characteristics of the device by rounding the upper portion of the trench in the device isolation process using a trench.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.
또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process is difficult to bury the trench region as the design rule is reduced as well as the complexity of the process, it will be difficult to apply the trench isolation process when the design rule approaches 0.1 ㎛.
상기와 같이 종래기술에 따른 반도체소자의 트렌치 형성방법은, 트렌치를 형성하는 경우 감광막 패턴을 식각마스크로 사용하여 트렌치식각공정을 실시하면 트렌치의 상부를 쉽게 라운딩시킬 수 있다. 그러나, 소자가 고집적화되어감에 따라 소자분리영역의 최소 크기가 0.18㎛ 이하에서는 감광막 패턴을 식각마스크로 이용한 식각공정을 실시하게 되면, 마이크로로딩(microloading)문제와 트렌치 깊이의 균일도 문제가 대두되어 하드마스크를 이용한 트렌치 식각이 요구된다. 이때, 하드마스크의 경우 트렌치상부 코너를 라운딩시키기 어렵기 때문에 소자의 전기적 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, in the trench forming method of the semiconductor device according to the related art, when the trench is formed, the trench may be easily rounded by performing the trench etching process using the photoresist pattern as an etching mask. However, as the device is highly integrated, if the device isolation region has a minimum size of 0.18 µm or less, an etching process using a photoresist pattern as an etching mask causes microloading problems and uniformity of trench depth. Trench etching using a mask is required. In this case, since the hard mask is difficult to round the upper corners of the hard mask, there is a problem of deteriorating the electrical characteristics and the reliability of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 반도체기판 상부에 소자분리영역을 노출시키는 절연막 패턴을 형성하되, 폴리머를 이용한 식각공정으로 상기 절연막 패턴의 식각면을 경사지게 형성한 다음, 상기 절연막 패턴의 식각면에 산화막 스페이서를 형성한 후 상기 절연막 및 산화막 스페이서를 식각마스크로 반도체기판을 식각하여 트렌치를 형성하되, 상기 트렌치의 식각면을 경사지게 형성시키고, 후속 열공정을 실시하여 트렌치의 상부 코너를 라운딩하게 형성함으로써 소자의 전기적 특성 및 공정수율을 향상시키는 반도체소자의 트렌치 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, an insulating film pattern for exposing a device isolation region is formed on a semiconductor substrate, and the etching surface of the insulating film pattern is inclined by an etching process using a polymer, and then the insulating film After the oxide spacer is formed on the etch surface of the pattern, the semiconductor substrate is etched using the insulating layer and the oxide spacer as an etch mask to form a trench, the etching surface of the trench is formed to be inclined, and a subsequent thermal process is performed to form an upper corner of the trench. It is an object of the present invention to provide a method for forming a trench in a semiconductor device that improves the electrical characteristics and the process yield of the device by forming a round.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 트렌치 형성방법을 도시한 단면도.1 to 6 are cross-sectional views showing a trench forming method of a semiconductor device according to the present invention.
〈 도면의 주요부분에 대한 부호의 설명 〉<Description of the reference numerals for the main parts of the drawings>
11 : 반도체기판 13 : 패드산화막11 semiconductor substrate 13 pad oxide film
15 : 질화막 17 : 제1산화막15 nitride film 17 first oxide film
19 : 감광막 패턴 21 : 제2산화막19 photosensitive film pattern 21 second oxide film
23 : 제2산화막 스페이서 25 : 트렌치23: second oxide film spacer 25: trench
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 트렌치 형성방법은,Trench forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 제1절연막을 형성하고, 상기 제1절연막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴을 형성하는 공정과,Forming a first insulating film on the semiconductor substrate, and forming a photoresist pattern on the first insulating film to expose a portion intended as an isolation region;
상기 감광막 패턴을 식각마스크로 사용하여 상기 제1절연막을 식각하되, 폴리머를 유발시키면서 식각공정을 실시하여 상기 제1절연막의 식각면이 경사지도록 패터닝하는 공정과,Etching the first insulating layer using the photoresist pattern as an etching mask, and performing an etching process while inducing a polymer to pattern the etching surface of the first insulating layer to be inclined;
상기 감광막 패턴을 제거한 다음, 전체표면 상부에 제2절연막을 형성하는 공정과,Removing the photoresist pattern, and then forming a second insulating layer over the entire surface;
상기 제2절연막을 전면식각하여 상기 제1절연막의 측벽에 제2절연막 스페이서를 형성하는 공정과,Forming a second insulating film spacer on the sidewall of the first insulating film by etching the entire surface of the second insulating film;
상기 제2절연막 스페이서와 제1절연막 패턴을 식각마스크로 상기 반도체기판을 식각하여 트렌치를 형성하되, 상기 제2절연막 스페이서의 형태를 전사하여 트렌치의 식각면을 경사지게 형성하는 공정과,Forming a trench by etching the semiconductor substrate using the second insulating layer spacer and the first insulating layer pattern as an etching mask, and transferring the shape of the second insulating layer spacer to form an inclined etching surface of the trench;
상기 트렌치의 표면을 습식식각하여 소정 두께의 제2절연막 스페이서를 제거함으로써 트렌치 상부 코너를 라운딩시키는 공정과,Rounding the upper corner of the trench by wet etching the surface of the trench to remove a second insulating spacer having a predetermined thickness;
상기 트렌치의 표면을 산화시키는 공정을 포함하는 것을 특징으로 한다.And oxidizing the surface of the trench.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 트렌치 형성방법을 도시한 단면도이다.1 to 6 are cross-sectional views showing a trench forming method of a semiconductor device according to the present invention.
반도체기판(11) 상부에 패드산화막(13), 질화막(15) 및 제1산화막(17)의 적층구조를 형성한 다음, 상기 제1산화막(17) 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴(19)을 형성한다. 상기 적층구조는 70 ∼ 200㎚ 두께로 형성한다. 이때, 상기 질화막(15) 상부에 제1산화막(17)을 형성하거나, 적층구조에서 상기 제1산화막(17)을 형성하지 않고 상기 제1산화막(17)의 두께 만큼 질화막(15)을 형성하는 것은 후속 트렌치를 형성하기 위한 식각공정시 상기 질화막(15)이 제거되서 트렌치를 형성한 다음, 갭필(gap fill)공정후 CMP공정에서 상기 질화막(15)이 식각장벽으로서의 역할을 할 수 있도록 하는 것이다. (도 1 참조)A stack structure of the pad oxide film 13, the nitride film 15, and the first oxide film 17 is formed on the semiconductor substrate 11, and then a portion of the pad oxide film 13, the nitride oxide film 15, and the first oxide film 17 is exposed on the first oxide film 17. The photosensitive film pattern 19 is formed. The laminated structure is formed to a thickness of 70 ~ 200nm. At this time, the first oxide film 17 is formed on the nitride film 15, or the nitride film 15 is formed by the thickness of the first oxide film 17 without forming the first oxide film 17 in a stacked structure. In the etching process for forming a subsequent trench, the nitride film 15 is removed to form a trench, and then the nitride film 15 may serve as an etching barrier in a CMP process after a gap fill process. . (See Figure 1)
다음, 상기 감광막 패턴(19)을 식각마스크로 사용하여 상기 적층구조를 식각하되, 상기 적층구조의 식각면이 경사지도록 패터닝한다. 상기 식각공정은 10 ∼ 500mTorr의 압력에서 CHF3, CF4, C4F8및 C3F8등의 플루오린계 가스를 식각가스로 사용하여 실시하되, 상기 감광막 패턴에 대하여 식각선택비를 2 ∼ 6로 하여 식각공정을 실시한다.Next, the layered structure is etched using the photoresist pattern 19 as an etch mask, and the patterned layer is etched so that the etched surface of the layered structure is inclined. The etching process may be performed using a fluorine-based gas such as CHF 3 , CF 4 , C 4 F 8, and C 3 F 8 as an etching gas at a pressure of 10 to 500 mTorr, with an etching selectivity of 2 to 5 for the photoresist pattern. The etching process is performed at 6.
상기 식각공정후 적층구조의 식각면은 80 ∼ 87。의 경사를 갖는다.The etching surface of the laminated structure after the etching process has an inclination of 80 to 87 degrees.
그 다음, 상기 감광막 패턴(19)을 제거한다. (도 2참조)Next, the photoresist pattern 19 is removed. (See Fig. 2)
다음, 전체표면 상부에 제2산화막(21)을 10 ∼ 50㎚ 두께로 형성한다. (도 3 참조)Next, a second oxide film 21 is formed to a thickness of 10 to 50 nm over the entire surface. (See Figure 3)
그 다음, 상기 제2산화막(21)을 전면식각하여 상기 적층구조의 식각면에 제2산화막 스페이서(23)를 형성한다. 상기 전면식각공정은 20 ∼ 50%의 과도식각공정으로 실시하되, 상기 제1산화막(17)이 5 ∼ 20㎚의 범위에서 손실되도록 실시한다. 상기 제2산화막 스페이서(23)는 10 ∼ 40㎚ 두께로 형성된다. (도 4 참조)Next, the second oxide film 21 is etched entirely to form a second oxide film spacer 23 on the etching surface of the stacked structure. The front surface etching process is performed by a 20 to 50% transient etching process, but the first oxide film 17 is performed in a range of 5 to 20nm. The second oxide film spacer 23 is formed to have a thickness of 10 to 40 nm. (See Figure 4)
그 후, 상기 제2산화막 스페이서(23)와 제1산화막(17) 패턴을 식각마스크로 사용하여 상기 반도체기판(11)을 식각하여 트렌치(25)를 형성한다. 상기 식각공정후 형성된 트렌치(25)의 식각면은 상기 제2산화막 스페이서(23)의 형태가 전사되어 82 ∼ 87。로 경사지게 형성되고, 상기 트렌치(25)의 상부 코너는 반도체기판(11)의 표면에 대하여 92 ∼ 100。의 각도로 형성된다. (도 5 참조)Thereafter, the semiconductor substrate 11 is etched using the second oxide spacer 23 and the first oxide layer 17 as an etch mask to form the trench 25. The etching surface of the trench 25 formed after the etching process is formed to be inclined at 82 to 87 ° by transferring the shape of the second oxide film spacer 23, and an upper corner of the trench 25 is formed on the semiconductor substrate 11. It is formed at an angle of 92 to 100 degrees with respect to the surface. (See Figure 5)
그 다음, 상기 트렌치(25)의 표면을 습식식각하되, 상기 습식식각공정은 BOE(buffered of etchant)용액 또는 불산용액으로 실시하여 상기 제2산화막 스페이서(23) 두께의 1/3 ∼ 1 을 제거한다.Next, the surface of the trench 25 is wet etched, and the wet etching process is performed using a buffered of etchant (BOE) solution or hydrofluoric acid solution to remove 1/3 to 1 of the thickness of the second oxide spacer 23. do.
그 후, 상기 트렌치(25)의 표면을 산화시킨다. (도 6 참조)Thereafter, the surface of the trench 25 is oxidized. (See Figure 6)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 트렌치 형성방법은, 반도체기판 상부에 소자분리영역으로 예정되는 부분을 노출시키는 절연막 패턴을 형성하되, 상기 절연막 패턴의 식각면을 경사지게 형성하고, 상기 절연막 패턴의 식각면에 절연막 스페이서를 형성한 다음, 트렌치식각공정을 실시하면, 트렌치의 식각면이 상기 절연막 스페이서의 형태가 전사되어 경사지게 형성되고, 후속 열공정으로 상부 코너가 라운딩된 트렌치가 형성되어 반도체소자의 고집적화를 가능하게 하고, 식각공정후 결함을 감소시켜 소자의 공정마진 및 전기적 특성을 향상시키는 이점이 있다.As described above, in the trench forming method of the semiconductor device according to the present invention, an insulating film pattern is formed on the semiconductor substrate to expose a predetermined portion as a device isolation region, and the etching surface of the insulating film pattern is formed to be inclined. After forming the insulating film spacer on the etching surface of the pattern, and then performing a trench etching process, the etching surface of the trench is formed to be inclined by transferring the shape of the insulating film spacer, and a trench with a rounded upper corner is formed by a subsequent thermal process. It is possible to increase the integration of the device and to reduce defects after the etching process, thereby improving the process margin and the electrical characteristics of the device.
Claims (12)
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KR20040050632A (en) * | 2002-12-10 | 2004-06-16 | 주식회사 하이닉스반도체 | Method for forming isolation of semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20040050632A (en) * | 2002-12-10 | 2004-06-16 | 주식회사 하이닉스반도체 | Method for forming isolation of semiconductor device |
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