KR20010009223A - A method of device isolation in semiconductor device - Google Patents

A method of device isolation in semiconductor device Download PDF

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Publication number
KR20010009223A
KR20010009223A KR1019990027497A KR19990027497A KR20010009223A KR 20010009223 A KR20010009223 A KR 20010009223A KR 1019990027497 A KR1019990027497 A KR 1019990027497A KR 19990027497 A KR19990027497 A KR 19990027497A KR 20010009223 A KR20010009223 A KR 20010009223A
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South Korea
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trench
oxide film
insulating material
substrate
silicon
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KR1019990027497A
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Korean (ko)
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KR100361520B1 (en
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장명준
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김영환
현대반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Abstract

PURPOSE: A method for isolating a semiconductor device is provided to reduce a leakage current by increasing an absolute path of a diffusion current, and to guarantee a sufficient process margin by etching a trench broader than a design rule. CONSTITUTION: A substrate(21) on a field region is eliminated by a predetermined depth to form a trench on a semiconductor substrate wherein an active region and the field region are defined. The surface of the trench is made irregular to increase a surface area. The trench is filled with an insulating material(25).

Description

반도체장치의 소자격리방법{A method of device isolation in semiconductor device}A method of device isolation in semiconductor device

본 발명은 반도체장치의 소자격리방법에 관한 것으로서, 특히, 소자격리를 위한 절연물질이 매립되기 전단계에서 반도체기판의 트렌치 표면에 반구형 돌출부를 형성한 다음 트렌치를 절연물질로 매립하므로서 확산전류의 절대 경로를 증가시켜 누설전류를 감소시키며, 또한, 트렌치를 디자인 룰 보다 넓게 식각하므로서 충분한 공정 마진을 확보하도록 한 반도체장치의 소자격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to forming a hemispherical protrusion on a trench surface of a semiconductor substrate before the insulating material is buried, and then filling the trench with an insulating material, thereby providing an absolute path for diffusion current. The present invention relates to a method for isolating a device of a semiconductor device in which a leakage current is increased to reduce the leakage current, and a sufficient process margin is obtained by etching the trench wider than the design rule.

반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

BOX(buried oxide)형 얕은트렌치소자격리(shallow trench isolation) 기술은 반도체기판에 트렌치를 형성하고 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 산화실리콘 또는 불순물이 도핑되지 않은 다결정실리콘을 매립한 구조를 갖는다. 그러므로, 버즈 비크가 발생되지 않아 활성영역의 손실이 전혀 없으며, 또한, 산화막을 메립하고 에치 백(etch back)하여 평탄한 표면을 얻을 수 있다.BOX (buried oxide) shallow trench isolation technology is a polycrystalline silicon that is not doped with silicon oxide or impurities by forming a trench in a semiconductor substrate and chemical vapor deposition (hereinafter referred to as CVD). It has a structure buried. Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.

특히, 소자의 게이트 길이가 감소함에 따라 트렌치 소자격리 산화막을 채용하는 구조에서 발생하는 누설전류성분은 확산전류(diffusion current)와 드리프트 전류(drift current)로 대별된다. 드리프트 전류는 소자 사이의 최단 거리를 통해 흐르는 반면, 확산전류는 STI와 산화막의 계면을 통해 흐른다. 그러나, 소자의 스케일 다운으로 트렌치의 폭 역시 ??아져서 공정 마진이 부족해진다.In particular, as the gate length of the device decreases, the leakage current component generated in the structure employing the trench isolation layer oxide film is roughly classified into a diffusion current and a drift current. The drift current flows through the shortest distance between the devices, while the diffusion current flows through the interface between the STI and the oxide film. However, as the device scales down, the width of the trench also decreases, resulting in insufficient process margin.

도 1a 내지 도 1d는 종래 기술에 따른 얕은 트렌치를 이용한 소자격리방법을 도시하는 공정도이다.1A to 1D are process diagrams illustrating a device isolation method using a shallow trench according to the prior art.

도 1a를 참조하면, 반도체기판(11)인 실리콘기판 상에 열산화 방법으로 버퍼산화막(도시안함)을 형성하고, 이 버퍼산화막 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화실리콘을 증착하여 마스크층(12)을 형성한다.Referring to FIG. 1A, a buffer oxide film (not shown) is formed on a silicon substrate, which is a semiconductor substrate 11, by a thermal oxidation method, and chemical vapor deposition (hereinafter, referred to as CVD) method is performed on the buffer oxide film. Silicon nitride is deposited to form a mask layer 12.

그리고, 마스크층(12) 및 버퍼산화막을 포토리쏘그래피 방법으로 마스크층으로 보호되 아니하는 반도체기판(11) 표면이 노출되도록 순차적으로 패터닝하여 소자격리영역과 활성영역을 한정한다.The mask layer 12 and the buffer oxide film are sequentially patterned to expose the surface of the semiconductor substrate 11 that is not protected by the mask layer by photolithography to define the device isolation region and the active region.

그다음, 마스크층(12)을 식각마스크로 사용하여 반도체기판(11)의 노출된 소자격리영역을 소정 깊이로 식각하여 트렌치(13)를 형성한다. 상기에서 트렌치(13)를 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함)이나 플라즈마 식각 등으로 이방성 식각하여 형성한다.Next, the trench 13 is formed by etching the exposed device isolation region of the semiconductor substrate 11 to a predetermined depth by using the mask layer 12 as an etching mask. The trench 13 may be formed by anisotropic etching by reactive ion etching (hereinafter referred to as RIE) or plasma etching.

도 1b를 참조하면, 노출된 트렌치(13)의 표면을 산화(light oxidation)시켜 산화막(14)을 형성한다.Referring to FIG. 1B, the surface of the exposed trench 13 is oxidized to form an oxide film 14.

도 1c를 참조하면, 트렌치 및 마스크층(12) 상에 절연물질층(15)으로 산화실리콘층(15)을 트렌치를 충분히 매립하도록 CVD 방법으로 증착한다. 이때, 절연물질은 증착 후 일반적인 산화막과 동일한 물리적 특성을 갖도록 고온에서 덴시파이(densify) 시킨다.Referring to FIG. 1C, the silicon oxide layer 15 is deposited on the trench and mask layer 12 by the CVD method to sufficiently fill the trench with the insulating material layer 15. In this case, the insulating material is densified at a high temperature to have the same physical properties as the general oxide film after deposition.

그리고, 돌출 부위를 포함하는 절연물질층을 마스크층(12) 표면이 노출되도록 화학-기계적연마(Chemical-Mechanical Polishing : 이하, CMP라 칭함) 방법 또는 RIE 방법으로 에치 백하여 트렌치 내에만 잔류되도록 한다. 이 때, 트렌치 내에 잔류하는 산화실리콘층인 절연물질층(15)은 소자를 분리하는 필드산화막(15)이 된다.Then, the insulating material layer including the protruding portion is etched back by chemical-mechanical polishing (hereinafter referred to as CMP) method or RIE method so that the surface of the mask layer 12 is exposed to remain only in the trench. . At this time, the insulating material layer 15, which is a silicon oxide layer remaining in the trench, becomes a field oxide film 15 separating the devices.

도 1d를 참조하면, 마스크층(12) 및 버퍼산화막을 습식 식각 방법으로 순차적으로 제거하여 반도체기판(11)의 활성영역을 노출시킨다.Referring to FIG. 1D, the mask layer 12 and the buffer oxide film are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 11.

상술한 종래의 반도체장치의 소자격리방법은 확산전류의 이동경로가 편평한 필드산화막(15) 계면을 따라 흐르므로 그 길이가 짧아 누설전류를 줄이기 곤란하고, 또한, 소자가 고집적화됨에 따라 트렌치 소자격리방법의 트렌치 식각공정의 마진이 부족한 문제점이 있다.The device isolation method of the conventional semiconductor device described above is difficult to reduce the leakage current due to its short length because the movement path of the diffusion current flows along the flat field oxide film 15 interface. There is a problem that the margin of the trench etching process is insufficient.

따라서, 본 발명의 목적은 소자격리를 위한 절연물질이 매립되기 전단계에서 반도체기판의 트렌치 표면에 반구형 돌출부를 형성한 다음 트렌치를 절연물질로 매립하므로서 확산전류의 절대 경로를 증가시켜 누설전류를 감소시키며, 또한, 트렌치를 디자인 룰 보다 넓게 식각하므로서 충분한 공정 마진을 확보하도록 한 반도체장치의 소자격리방법을 제공하는데 있다.Therefore, an object of the present invention is to form a hemispherical protrusion on the trench surface of the semiconductor substrate before the insulating material is embedded in the device isolation and then to fill the trench with the insulating material to increase the absolute path of the diffusion current to reduce the leakage current In addition, the present invention provides a device isolation method of a semiconductor device in which a trench is etched wider than a design rule to secure sufficient process margin.

상기 목적을 달성하기 위해 본 발명에 따른 반도체장치의 소자격리방법은 활성영역과 필드영역이 정의된 반도체기판에 상기 필드영역의 상기 기판을 소정 깊이로 제거하여 트렌치를 형성하는 단계와, 트렌치의 표면을 불규칙하게 하여 표면적을 증가시키는 단계와, 트렌치를 절연물질로 매립하는 단계를 포함하는 공정으로 이루어진다. 이때, 상기 표면적을 증가시키는 단계는, 트렌치 표면에 반구형 그레인 실리콘층을 형성하는 단계와, 반구형 그레인 실리콘층 표면에 산화막을 형성하는 단계를 더 포함하여 이루어진다.In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention includes forming a trench by removing the substrate of the field region to a predetermined depth on a semiconductor substrate in which an active region and a field region are defined, and forming a trench; Irregularly increasing the surface area, and filling the trench with an insulating material. In this case, the step of increasing the surface area may further include forming a hemispherical grain silicon layer on the trench surface and forming an oxide film on the surface of the hemispherical grain silicon layer.

도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 소자격리방법을 도시하는 공정단면도1A to 1D are process cross-sectional views showing a device isolation method of a semiconductor device according to the prior art.

도 2a 내지 도 2f는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정단면도2A to 2F are process cross-sectional views showing a device isolation method for a semiconductor device according to the present invention.

본 발명에서는 트렌치 형성 후 노출된 실리콘 기판의 표면에 반구형 실리콘 그레인을 형성한 후 그레인 표면을 가볍게 열산화(light oxidation) 시키므로서 산화막을 형성하는데 이러한 산화막의 표면적은 편평한(flat) 형태의 표면을 갖는 종래 기술의 트렌치 필드산화막의 표면적 보다 최소한 두 배 이상 증가한다. 이는, 확산전류 성분의 절대 경로 길이가 두 배 이상 증가함을 의미한다.In the present invention, after forming the trench, hemispherical silicon grains are formed on the exposed surface of the silicon substrate, and lightly oxidizes the grain surface to form an oxide film. The surface area of the oxide film has a flat surface. It is at least twice as large as the surface area of the prior art trench field oxide. This means that the absolute path length of the diffusion current component is more than doubled.

이때, 반구형 실리콘 그레인은 1.0 × 10-7 ∼ 5.0 × 10-8torr 정도의 진공 상태에서 SiH4 가스를 흘리면서 열처리하면 노출된 실리콘 기판의 표면에 실리콘이 반구형으로 증착되므로써 형성된다.At this time, the hemispherical silicon grains are formed by depositing silicon in a hemispherical shape on the surface of the exposed silicon substrate when the heat treatment is carried out while flowing SiH4 gas in a vacuum of about 1.0 × 10 -7 to 5.0 × 10 -8 torr.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정단면도이다.2A to 2F are process cross-sectional views showing a device isolation method of a semiconductor device according to the present invention.

도 2a를 참조하면, 반도체기판(21)인 실리콘기판 상에 열산화 방법으로 버퍼산화막(도시안함)을 형성하고, 이 버퍼산화막 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화실리콘을 증착하여 마스크층(22)을 형성한다.Referring to FIG. 2A, a buffer oxide film (not shown) is formed on a silicon substrate, which is a semiconductor substrate 21, by a thermal oxidation method, and a chemical vapor deposition (hereinafter, referred to as CVD) method is performed on the buffer oxide film. Silicon nitride is deposited to form a mask layer 22.

그리고, 마스크층(22) 및 버퍼산화막을 포토리쏘그래피 방법으로 마스크층으로 보호되 아니하는 반도체기판(21) 표면이 노출되도록 순차적으로 패터닝하여 소자격리영역과 활성영역을 한정한다. 이때, 노출되는 기판 부위는 디자인 룰(design rule) 보다 넓게 하여 공정 마진을 확보한다.The mask layer 22 and the buffer oxide film are sequentially patterned to expose the surface of the semiconductor substrate 21, which is not protected by the mask layer, by photolithography to define the device isolation region and the active region. In this case, the exposed substrate portion is wider than the design rule to secure the process margin.

그다음, 잔류한 마스크층(22)을 식각마스크로 사용하여 반도체기판(21)의 노출된 소자격리영역을 소정 깊이로 식각하여 트렌치(23)를 형성한다. 상기에서 트렌치(23)를 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함)이나 플라즈마 식각 등으로 이방성 식각하여 형성한다.Next, the trench 23 is formed by etching the exposed device isolation region of the semiconductor substrate 21 to a predetermined depth by using the remaining mask layer 22 as an etching mask. The trench 23 is formed by anisotropic etching by reactive ion etching (hereinafter referred to as RIE) or plasma etching.

도 2b를 참조하면, 잔류한 마스크층과 버퍼산화막을 습식식각으로 제거하여 실리콘기판(21)의 상부 표면을 노출시킨다. 이때, 트렌치(23) 부위의 기판 표면은 이미 노출되어 있다.Referring to FIG. 2B, the remaining mask layer and the buffer oxide film are removed by wet etching to expose the upper surface of the silicon substrate 21. At this time, the substrate surface of the trench 23 portion is already exposed.

도 2c를 참조하면, 트렌치(23) 내부 표면을 포함하는 기판(21)의 표면에 반구형 그레인(hemispherical grain) 실리콘층(26)을 형성한다. 이때, 반구형 그레인 실리콘층(26)은 1.0 × 10-7∼ 5.0 × 10-8torr 정도의 진공 상태에서 SiH4가스를 기판(21) 표면에 흘리면서 열처리하면 노출된 실리콘 기판의 표면에 실리콘이 반구형으로 증착되므로써 형성된다.Referring to FIG. 2C, a hemispherical grain silicon layer 26 is formed on the surface of the substrate 21 including the inner surface of the trench 23. At this time, the hemispherical grain silicon layer 26 is heat treated while flowing SiH 4 gas on the surface of the substrate 21 in a vacuum state of about 1.0 × 10 -7 to 5.0 × 10 -8 torr. It is formed by deposition.

도 2d를 참조하면, 노출된 반구형 그레인 실리콘층의 표면을 산화(light oxidation)시켜 반구형 산화막(24)을 형성한다. 따라서, 트렌치 계면의 산화막의 표면적이 편평한 경우 보다 최소한 두배 이상 증가하였다.Referring to FIG. 2D, the surface of the exposed hemispherical grain silicon layer is light oxidized to form a hemispherical oxide film 24. Therefore, the surface area of the oxide film at the trench interface is increased at least twice as much as that of the flat surface.

도 2e를 참조하면, 트렌치 부위를 포함하는 반구형 산화막(24) 상에 절연물질층(25)으로 산화실리콘층(15)을 트렌치를 충분히 매립하도록 CVD 방법으로 증착한다. 이때, 절연물질로 HDP를 사용할 수 있으며, 절연물질로 에스오지(silicon on glass)를 상기 기판에 도포한 후 덴시피케이션(densification) 시켜서 형성할 수 있다.Referring to FIG. 2E, the silicon oxide layer 15 is deposited by the CVD method to sufficiently fill the trench with the insulating material layer 25 on the hemispherical oxide film 24 including the trench portion. In this case, HDP may be used as the insulating material, and may be formed by applying a silicon on glass to the substrate as an insulating material and then densification.

도 2f를 참조하면, 돌출 부위를 포함하는 절연물질층, 반구형 산화막 그리고 산화되지 않은 반구형 그레인 실리콘층을 실리콘 기판(21) 표면이 노출되도록 화학-기계적연마(Chemical-Mechanical Polishing : 이하, CMP라 칭함) 방법 또는 RIE 방법으로 에치 백하여 트렌치 내에만 잔류되도록 한다. 이 때, 트렌치 내에 잔류하는 산화실리콘층인 절연물질층(25)은 소자를 분리하는 필드산화막(25)이 된다.Referring to FIG. 2F, an insulating material layer including a protruding portion, a hemispherical oxide film, and an unoxidized hemispherical grain silicon layer are referred to as chemical-mechanical polishing (hereinafter, referred to as CMP) to expose the surface of the silicon substrate 21. Etch back by the RIE method or the RIE method so that it remains only in the trench. At this time, the insulating material layer 25, which is a silicon oxide layer remaining in the trench, becomes a field oxide film 25 separating the devices.

그 다음, 게이트산화막, 게이트, 소스/드레인, 실리사이드 등의 형성공정을 실시하여 모스 소자를 완성한다.Then, a process of forming a gate oxide film, a gate, a source / drain, a silicide, or the like is performed to complete the MOS device.

따라서, 본 발명은 소자격리를 위한 절연물질이 매립되기 전단계에서 반도체기판의 트렌치 표면에 반구형 돌출부를 형성한 다음 트렌치를 절연물질로 매립하므로서 확산전류의 절대 경로를 증가시켜 누설전류를 감소시키며, 또한, 트렌치를 디자인 룰 보다 넓게 식각하므로서 충분한 공정 마진을 확보하는 장점이 있다.Therefore, the present invention reduces the leakage current by increasing the absolute path of the diffusion current by forming a hemispherical protrusion on the trench surface of the semiconductor substrate and then filling the trench with an insulating material before the insulating material for embedding the device is embedded. By etching the trench wider than the design rule, sufficient process margin is secured.

Claims (5)

활성영역과 필드영역이 정의된 반도체기판에 상기 필드영역의 상기 기판을 소정 깊이로 제거하여 트렌치를 형성하는 단계와,Forming a trench by removing the substrate in the field region to a predetermined depth in a semiconductor substrate in which an active region and a field region are defined; 상기 트렌치의 표면을 불규칙하게 하여 표면적을 증가시키는 단계와,Irregularizing the surface of the trench to increase its surface area; 상기 트렌치를 절연물질로 매립하는 단계로 이루어진 반도체장치의 소자격리방법.Isolating the trench with an insulating material. 청구항 1에 있어서, 상기 표면적을 증가시키는 단계는,The method of claim 1, wherein the step of increasing the surface area, 상기 트렌치 표면에 반구형 그레인 실리콘층을 형성하는 단계와,Forming a hemispherical grain silicon layer on the trench surface; 상기 반구형 그레인 실리콘층 표면에 산화막을 형성하는 단계를 더 포함하여 이루어진 것이 특징인 반도체장치의 소자격리방법.And forming an oxide film on the surface of the hemispherical grain silicon layer. 청구항 2에 있어서, 상기 산화막은 상기 반구형 그레인 실리콘층을 열산화시켜 형성하는 것이 특징인 반도체장치의 소자격리방법.The device isolation method of claim 2, wherein the oxide film is formed by thermally oxidizing the hemispherical grain silicon layer. 청구항 1에 있어서, 상기 절연물질은 에스오지(silicon on glass)를 상기 기판에 도포한 후 덴시피케이션 시켜서 형성하는 것이 특징인 반도체장치의 소자격리 방법.The method of claim 1, wherein the insulating material is formed by applying a silicon on glass to the substrate and densifying the insulating material. 청구항 1에 있어서, 상기 트렌치 폭은 디자인 룰 보다 크게 형성하는 것이 특징인 반도체장치의 소자격리방법.The method of claim 1, wherein the trench width is larger than a design rule.
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