KR20010008502A - Method for forming capacitor of semiconductor device - Google Patents
Method for forming capacitor of semiconductor device Download PDFInfo
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- KR20010008502A KR20010008502A KR1019990026378A KR19990026378A KR20010008502A KR 20010008502 A KR20010008502 A KR 20010008502A KR 1019990026378 A KR1019990026378 A KR 1019990026378A KR 19990026378 A KR19990026378 A KR 19990026378A KR 20010008502 A KR20010008502 A KR 20010008502A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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Abstract
Description
본 발명은 반도체 장치의 커패시터 제조방법에 관한 것으로서, 특히 커패시터의 유전체막을 TaON으로 형성할 경우 이 막에 대한 상부 전극과의 계면 안정성을 도모할 수 있도록 상부전극으로서 TaN막을 형성하여 고커패시턴스를 달성할 수 있는 반도체장치의 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor manufacturing method of a semiconductor device. In particular, when a dielectric film of a capacitor is formed of TaON, a high capacitance can be achieved by forming a TaN film as an upper electrode so as to achieve interfacial stability with the upper electrode for the film. The present invention relates to a capacitor manufacturing method of a semiconductor device.
현재 반도체 소자의 고집적화를 달성하기 위하여 셀 면적의 감소 및 동작 전압의 저전압화에 관한 연구/개발이 활발하게 진행되고 있다. 더구나 반도체 소자의 고집적화가 이루어질수록 커패시터의 면적이 급격하게 감소되지만 기억소자의 동작에 필요한 전하 즉, 단위 면적에 확보되는 커패시턴스는 증가되어야만 한다.In order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices increases, the area of the capacitor decreases drastically, but the charge required for the operation of the memory device, that is, the capacitance secured in the unit area must be increased.
이를 위해 커패시터의 충분한 용량을 확보하기 위해서 통상의 실린더 구조 변경을 통해 커패시터 면적을 증가하거나 유전체막의 두께 감소를 통해 충분한 커패시턴스를 확보시키는 방법이 이루어지고 있으며, 기존 실리콘 산화막으로 사용하던 유전체막을 NO(Nitride-Oxide) 구조 또는 ONO(Oxide-Nitride-Oxide)구조라든지 Ta2O5또는 BST(BaSrTiO3) 등으로 대체하려는 재료적인 연구가 진행되고 있다.To this end, in order to secure a sufficient capacity of the capacitor, a method of securing a sufficient capacitance by increasing the capacitor area or reducing the thickness of the dielectric film by changing a conventional cylinder structure is being performed. The dielectric film used as a conventional silicon oxide film is NO (Nitride). Material studies are attempting to replace -Oxide structure or ONO (Oxide-Nitride-Oxide) structure or Ta 2 O 5 or BST (BaSrTiO 3 ).
더욱이 최근에는 향후 256M 이상의 디바이스에 적용할 수 있도록 커패시터 용량 확보에 어려움이 있는 NO, ONO의 저유전체막보다는 높은 커패시턴스(유전상수=20∼25)를 확보할 수 있는 Ta2O5내지 TaON의 고유전체막을 더 많이 사용하고 있다.Moreover, in recent years, Ta 2 O 5 to TaON inherent in high capacitance (dielectric constant = 20-25) than the low dielectric film of NO and ONO, which have difficulty in securing capacitor capacity, can be applied to devices of 256M or more in the future. The entire membrane is being used more.
최근에 개발이 이루어지고 있는 TaON박막은 도프트 폴리실리콘이 증착된 하부전극 위에 기존에 유전체박막으로 자주 이용되던 Ta2O5의 근원물질인 Ta(OC2H5)5에 O2와 NH3을 첨가하여 금속유기화학기상증착법(metal-organic chemical vapor deposition)으로 증착해서 형성된다. 우수한 유전율을 가지는 TaON박막을 형성하려면, 박막 형성시에 근원물질의 분해 반응이 원활하게 일어나야 하고, 또 분해된 근원 물질과 첨가된 반응가스(O2,NH3)사이의 생성반응이 박막표면에서 활발하게 이루어져 밀도가 높은 박막이 형성되는데, 이는 어떤 근원 물질과 반응가스를 선택하느냐에 따라서 크게 달라진다.Recently developed TaON thin film is O 2 and NH 3 to Ta (OC 2 H 5 ) 5 which is a source material of Ta 2 O 5 which is often used as a dielectric thin film on the bottom electrode on which doped polysilicon is deposited It is formed by the deposition by the addition of metal-organic chemical vapor deposition (metal-organic chemical vapor deposition). In order to form a TaON thin film having excellent dielectric constant, the decomposition reaction of the source material should occur smoothly when forming the thin film, and the formation reaction between the decomposed source material and the added reaction gas (O 2 , NH 3 ) is performed on the thin film surface. It is actively formed to form a dense thin film, which depends greatly on the source material and the reaction gas selected.
그리고, 이러한 TaON박막에 대한 상부 전극으로는 대체로 TiCl4와 NH3을 이용한 화학기상증착법으로 증착된 티타늄질화박막(TiN)과 도프트 폴리실리콘막의 이중 구조가 자주 사용되고 있다. 하지만, 유전특성이 우수한 TaON박막의 특성을 후속공정에서도 그대로 유지하기 위해서는 상부전극 형성시 안정된 계면 특성을 가지는 전극 물질을 사용해야만 한다.As the upper electrode for the TaON thin film, a double structure of a titanium nitride thin film (TiN) and a doped polysilicon film, which are generally deposited by chemical vapor deposition using TiCl 4 and NH 3 , is frequently used. However, in order to maintain the characteristics of the TaON thin film having excellent dielectric properties in the subsequent process, an electrode material having stable interfacial properties must be used in forming the upper electrode.
그러나, TiCl4과 NH3을 사용한 TiN 전극증착법은 증착온도가 650℃이상의 고온이기 때문에 증착과정에서 TaON의 유전물질과 하부전극인 도프트 폴리실리콘 사이의 계면 반응이 발생할 수 있을 뿐만 아니라, 이 과정에서 생성된 계면 산화막은 전체 커패시턴스를 낮추는 직접적인 원인으로 작용한다.However, the TiN electrode deposition method using TiCl 4 and NH 3 has a high deposition temperature of 650 ° C. or higher, so that the interfacial reaction between the dielectric material of TaON and the doped polysilicon, which is a lower electrode, may occur during the deposition process. The interfacial oxide film formed in X is acted as a direct cause of lowering the total capacitance.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 커패시터의 유전체막을 TaON으로 형성하면서 그 유전체박막 위에 상부전극으로서 TaN막을 형성하되, PEMAT, PDMAT 내지 PDEAT 등의 동일한 금속유기물질을 근원물질로 사용하고, 각 막의 고밀도화를 위하여 질화처리함으로써 고유전체 TaON막과 상부전극의 계면에서 발생하는 산화반응을 억제하는 반도체장치의 커패시터 제조방법을 제공하는데 있다.An object of the present invention is to form a TaN film as an upper electrode on the dielectric thin film while forming a dielectric film of the capacitor TaON to solve the problems of the prior art as described above, the same material as the organic material such as PEMAT, PDMAT to PDEAT source material The present invention provides a method of manufacturing a capacitor of a semiconductor device which suppresses oxidation reaction occurring at an interface between a high dielectric TaON film and an upper electrode by nitriding for increasing the density of each film.
상기 목적을 달성하기 위하여 본 발명은 반도체기판의 활성영역과 접촉하는 하부 전극과 그 위의 상부전극 및 상기 전극들 사이에 내재된 고유전체 박막으로 이루어진 커패시터의 제조 공정에 있어서, 반도체 소자를 구비한 반도체기판 상부에 소자간 절연을 위한 층간절연막의 콘택홀을 통해서 반도체 소자와 접하며 도전층으로 이루어진 하부전극을 형성하는 단계와, 하부전극 상부면에 PEMAT(Ta(N(CH3C2H5))5), PDEAT(Ta(N(C2H5)2)5) 내지 PDMAT(Ta(N(CH3)2)5) 중의 어느 한 금속유기물질을 가지고 TaON을 증착하여 고유전체 박막을 형성하는 단계와, 고유전체 박막 상부면에 상기 제조 공정과 동일한 금속 유기물질을 가지고 TaN박막을 증착하여 제 1상부전극을 형성하는 단계와, 제 1상부전극 상부면에 도전층으로 이루어진 제 2상부전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a capacitor comprising a lower electrode in contact with an active region of a semiconductor substrate, an upper electrode thereon, and a high dielectric thin film embedded between the electrodes. Forming a lower electrode made of a conductive layer in contact with the semiconductor device through a contact hole of an interlayer insulating film for inter-device insulation on the semiconductor substrate, and PEMAT (T (N (CH 3 C 2 H 5 )) on the upper surface of the lower electrode. 5 ), PDEAT (Ta (N (C 2 H 5 ) 2 ) 5 ) to PDMAT (Ta (N (CH 3 ) 2 ) 5 ) to deposit TaON with metal organic material to form high dielectric thin film And forming a first upper electrode by depositing a TaN thin film on the upper surface of the high dielectric thin film with the same metal organic material as the manufacturing process, and a second upper electrode including a conductive layer on the upper surface of the first upper electrode. Forming steps Characterized in that comprises a.
본 발명의 원리에 따르면, 고유전체 TaON막과 제 1상부전극인 TaN막을 금속유기물의 형태인 PEMAT, PDEAT 내지 PDMAT 중에서 선택된 어느 한 물질을 근원물질(source)로 사용한다. 액체상태인 근원물질을 챔버내로 운반하는 방법은 운반 가스가 직접 근원물질을 버블링하거나 마이크로펌프에 의해 증기화된 근원물질을 운반가스가 운반하도록 한다. 이때, TaON막과 TaN막의 증착 압력은 10mTorr∼ 10Torr이며 증착온도는 300∼450℃로 하는 것이 바람직하다.According to the principle of the present invention, a material selected from PEMAT, PDEAT, and PDMAT, which is a form of a metal organic material, is used as a source of the high dielectric TaON film and the first upper electrode TaN film. The method of transporting a liquid source material into the chamber allows the carrier gas to carry the source material directly by bubbling the source material or vaporized by the micropump. At this time, the deposition pressure of the TaON film and the TaN film is 10 mTorr to 10 Torr, and the deposition temperature is preferably 300 to 450 ° C.
이에 따라 금속유기물인 PEMAT, PDEAT와 PDMAT는 그 물질 내부가 결합력이 약한 카본으로 연결되어 있으므로 400℃이하의 저온에서 근원물질이 분해되면서 증착이 이루어진다. 이러한 특성은 기존의 상부전극인 TiN의 근원물질인 TiCl4의 분해가 600℃이상의 고온에서 이루어지는 것에 비해 장점으로 작용한다. 즉, 600℃이상의 고온은 유전체 박막내에 불완전한 상태로 결합되어 있던 산소원자들이 하부전극으로 확산되는데 충분한 활성에너지를 공급하기 때문이다.Accordingly, the metal organic materials, PEMAT, PDEAT and PDMAT, are connected by carbon with weak bonding strength, so that the source material is decomposed at a temperature lower than 400 ° C. to be deposited. This property is an advantage compared to the decomposition of TiCl 4 , a source material of the existing upper electrode TiN, at a high temperature of more than 600 ℃. That is, the high temperature of more than 600 ℃ is because the oxygen atoms that are incompletely coupled in the dielectric thin film supply sufficient active energy to diffuse to the lower electrode.
또한, 본 발명은 도프트 폴리실리콘막 형성 이전에 상부전극으로서 TaN을 증착한 후에 N2와 H2의 혼합기체를 사용한 플라즈마처리를 실시하여 박막의 조밀화를 이루며 동시에 불순물을 제거한다.In addition, the present invention performs a plasma treatment using a mixed gas of N 2 and H 2 after depositing TaN as an upper electrode prior to the formation of the doped polysilicon film to achieve compactness of the thin film and simultaneously remove impurities.
도 1 내지 도 8은 본 발명에 따른 고유전체 TaON을 갖는 반도체장치의 커패시터 제조방법을 순서적으로 설명하기 위한 공정 순서도.1 to 8 are process flowcharts for sequentially explaining a capacitor manufacturing method of a semiconductor device having a high dielectric TaON according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 실리콘기판 20: 층간절연막10: silicon substrate 20: interlayer insulating film
22: 사이드월 스페이서 30: 하부 전극22: side wall spacer 30: lower electrode
32: 고유전체 TaON박막 34: 제 1상부전극32: high dielectric TaON thin film 34: first upper electrode
36: 제 2상부전극36: second upper electrode
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 8은 본 발명에 따른 고유전체 TaON을 갖는 반도체장치의 커패시터 제조방법을 순서적으로 설명하기 위한 공정 순서도이다.1 to 8 are process flowcharts for sequentially explaining a capacitor manufacturing method of a semiconductor device having a high dielectric TaON according to the present invention.
본 발명의 반도체장치의 커패시터 제조방법은, 도 1에 도시된 바와 같이 반도체기판으로서 실리콘기판(10)의 활성 영역 상부면에 게이트 전극, 소스/드레인 등을 갖는 반도체소자(도시하지 않음)를 형성하고, 그 기판(10) 전면에 USG(Undoped Silicate Glass), BPSG(Boro Phospho Silicate Glass) 및 SiON 중에서 선택한 물질을 증착하고 화학적기계적연마(Chemical Mechanical Polishing) 공정을 실시하여 층간절연막(20)을 형성한다. 기판(10)의 활성영역 즉, 드레인 영역과 접촉하는 커패시터의 단면적을 확보하기 위하여 사진 및 식각 공정으로 상기 층간절연막(20)을 선택 식각하여 콘택홀(도시하지 않음)을 형성하고, 콘택홀 내측벽에 절연물질로된 사이드월 스페이서(22)를 형성한다.In the capacitor manufacturing method of the semiconductor device of the present invention, as shown in FIG. 1, a semiconductor device (not shown) having a gate electrode, a source / drain, or the like is formed on the upper surface of the active region of the silicon substrate 10 as a semiconductor substrate. Then, the interlayer insulating film 20 is formed by depositing a material selected from USG (Undoped Silicate Glass), BPSG (Boro Phospho Silicate Glass) and SiON on the entire surface of the substrate 10 and performing a chemical mechanical polishing process. do. In order to secure the cross-sectional area of the capacitor in contact with the active region of the substrate 10, that is, the drain region, the interlayer insulating layer 20 is selectively etched by photolithography and etching to form a contact hole (not shown), and to form a contact hole in the contact hole. Sidewall spacers 22 made of an insulating material are formed on the sidewalls.
그 다음 사이드월 스페이서(22)가 형성된 콘택홀내에 실린더 구조의 하부 전극의 제조공정을 실시하는데, 평면적을 늘리기 위하여 상부면이 HSG(Hemi Sperical Grain) 형태를 갖는 하부전극을 형성한다. 즉, 상기 콘택홀을 갖는 층간절연막(20) 전면에 도전물질로서 비정질의 도핑 실리콘을 매립하도록 증착하고 식각 공정을 이용하여 실리콘층을 실리더 구조 형태로 패터닝한 후에 결정화 온도 이하 상태에서 전극의 상부면에 비정질 상태의 시드(seed)를 반구형 요철형태로 성장시켜서 HSG 구조의 하부전극(30)을 형성한다. 그리고 나서, 하부전극(30)에 충분한 P(phosphorus)를 공급, 예를 들어 1×10E20/㎤ 이상의 농도를 가지도록 하기 위하여 PH3처리를 실시해준다.Next, a manufacturing process of the lower electrode of the cylinder structure is performed in the contact hole in which the sidewall spacers 22 are formed. In order to increase the planar area, a lower electrode having an HSG (Hemi Sperical Grain) shape is formed. In other words, after the deposition of the doped silicon as a conductive material on the entire surface of the interlayer insulating film 20 having the contact hole and patterning the silicon layer in the form of a cylinder structure using an etching process, the upper part of the electrode at a temperature below the crystallization temperature An amorphous seed on the surface is grown in a hemispherical irregular shape to form the lower electrode 30 of the HSG structure. Then, a sufficient P (phosphorus) is supplied to the lower electrode 30, for example, PH 3 treatment is performed to have a concentration of 1 × 10 E 20 / cm 3 or more.
이어서 도면에 도시되지는 않았지만, 후속 공정시 하부전극의 산화를 방지하기 위해 반응챔버를 상압, NH3분위기 조건에서 800℃, 60초동안 급속 열처리공정(rapid thermal process)을 실시하여 하부전극(30) 상부면에 얇은 실리콘질화막(Si3N4)을 증착한다.Subsequently, although not shown in the drawing, in order to prevent oxidation of the lower electrode in a subsequent process, the reaction chamber was subjected to a rapid thermal process at 800 ° C. for 60 seconds under atmospheric pressure and NH 3 atmosphere, and then the lower electrode 30. A thin silicon nitride film (Si 3 N 4 ) is deposited on the upper surface.
그 다음 도 2에 도시된 바와 같이, PEMAT(Pentakis Ethyl Methyl Amido Tantalum, Ta(N(CH3C2H5))5), PDEAT(Pentakis Di Ethyl Amido Tantalum, Ta(N(C2H5)2)5) 내지 PDMAT(Pentakis Di Methyl Amido Tantalum, Ta(N(CH3)2)5) 중의 어느 한 금속유기물질을 가지고 TaON을 증착하여 고유전체 TaON박막(32)을 형성한다. 이때, 액상의 금속 유기물질과 N2O와 O2의 반응 가스를 사용하여 TaON 박막(32)을 증착할 경우 그 두께를 80Å∼200Å으로 한다. 근원물질의 전달은 비활성 전달가스(N2, Ar, He)를 이용한 근원물질 버블링 방법 또는 마이크로펌프를 이용하여 근원물질을 증기화시킨 후 운반가스를 전달하는 방법을 사용한다. 증착공정시 압력은 10mTorr∼ 10Torr이며 또한, 증착온도는 300∼450℃의 표면반응 지배영역(surface reaction controlled region)으로 제한한다.Then, as shown in FIG. 2, PEMAT (Pentakis Ethyl Methyl Amido Tantalum, Ta (N (CH 3 C 2 H 5 )) 5 ), PDEAT (Pentakis Di Ethyl Amido Tantalum, Ta (N (C 2 H 5 )) 2 ) TaON is deposited using a metal organic material of any one of 5 ) to PDMAT (Pentakis Di Methyl Amido Tantalum, Ta (N (CH 3 ) 2 ) 5 ) to form a high dielectric TaON thin film 32. At this time, when the TaON thin film 32 is deposited using a liquid metal organic material and a reaction gas of N 2 O and O 2 , the thickness thereof is 80 kPa to 200 kPa. Source material delivery uses a method of bubbling source material using inert delivery gas (N 2 , Ar, He) or a method of delivering a carrier gas after vaporizing the source material using a micropump. The pressure during the deposition process is 10 mTorr to 10 Torr and the deposition temperature is limited to a surface reaction controlled region of 300 to 450 ° C.
고유전체 TaON박막(32)의 고밀도화를 위해서는 도 3 내지 도 5에 도시된 바와 같이, 고유전체 TaON박막(32)의 증착이 40Å∼100Å 정도 이루어진 후와 증착이 모두 완료된 후에 각각 N2O, H2, O2혼합기체를 이용한 1차의 플라즈마처리를 실시한다. 그리고, 도 4 및 도 5에서 같이 TaON박막(32')의 증착이 완료된 후에 동일한 챔버에서 2차의 플라즈마처리를 실시한다.In order to increase the density of the high-k dielectric TaON thin film 32, as shown in FIGS. 3 to 5, after the deposition of the high-k dielectric TaON thin film 32 is about 40 kPa to 100 kPa and the deposition is completed, N 2 O and H, respectively. The first plasma treatment using 2 , O 2 mixed gas is performed. 4 and 5, after the deposition of the TaON thin film 32 'is completed, the secondary plasma treatment is performed in the same chamber.
그 다음 도 6에 도시된 바와 같이, 2차례의 플라즈마 처리된 고유전체 TaON 박막(32'')위에 금속유기화학기상증착법으로 TaN막을 200∼500Å의 두께로 증착하여 제 1상부전극(34)을 형성한다. 이때, TaN의 근원물질은 상기 유전체 TaON박막(32)과 동일한 금속유기물질(PEMAT, PDEAT, PDMAT)을 사용한다. 역시 제 1상부전극(34)의 금속 유기물질의 증착공정은 300∼450℃의 온도범위와 10mTorr∼10Torr의 압력하에서 실시한다. 이에 따라, TaN 증착 공정을 400℃이하의 저온에서 실시함으로써 하부에 적층된 박막들이 받게 될 열적인 손상을 방지할 뿐만 아니라, TiCl4+NH3분해과정(650℃)에서 생성되는 파티클 발생을 막을 수 있어 박막의 균일도와 계단 도포성이 향상된다.Then, as shown in FIG. 6, the TaN film was deposited on the plasma-treated high dielectric TaON thin film 32 ″ by metal organic chemical vapor deposition to a thickness of 200 to 500 Å to form the first upper electrode 34. Form. At this time, the source material of TaN uses the same metal organic materials (PEMAT, PDEAT, PDMAT) as the dielectric TaON thin film (32). Also, the deposition process of the metal organic material of the first upper electrode 34 is carried out under a temperature range of 300 to 450 ° C. and a pressure of 10 mTorr to 10 Torr. Accordingly, the TaN deposition process is performed at a low temperature of 400 ° C. or lower to prevent thermal damage to the thin films stacked below, and to prevent particle generation generated during TiCl 4 + NH 3 decomposition (650 ° C.). This improves the uniformity and stair coatability of the thin film.
계속해서 도 7에 도시된 바와 같이, 제 1상부전극(34)을 형성한 후에 TaN박막을 조밀화하고 불순물 제거를 위해 저온에서 N2와 H2의 혼합기체를 사용한 플라즈마처리를 인-시튜(in-situ)로 실시한다. 즉, N2플라즈마 처리에 의해서는 박막의 조밀화가 이루어지고, H2플라즈마 처리에 의해서는 박막내 잔존해 있는 카본이 제거된다.Subsequently, as shown in FIG. 7, after forming the first upper electrode 34, the TaN thin film was densified and plasma treatment using a mixed gas of N 2 and H 2 at low temperature for removing impurities was performed in-situ. -situ). That is, the thin film is densified by the N 2 plasma treatment, and the carbon remaining in the thin film is removed by the H 2 plasma treatment.
도 8에 도시된 바와 같이, 제 1상부전극(34) 상부면에 도전층으로서 도프트 폴리실리콘을 1000Å정도 증착하여 제 2상부전극(36)을 형성한다. 이때, SiH4또는 Si2H6가스를 실리콘에 대한 근원가스로 사용하고 PH3가스를 도핑가스로 사용하여 1E20/㎤ 이상의 P농도를 가지게 한다.As shown in FIG. 8, a doped polysilicon is deposited on the upper surface of the first upper electrode 34 as a conductive layer at about 1000 m to form the second upper electrode 36. In this case, SiH 4 or Si 2 H 6 gas is used as the source gas for silicon and PH 3 gas is used as the doping gas to have a P concentration of 1E20 / cm 3 or more.
한편, 본 발명의 플라즈마 처리방법은 증착이 이루어진 챔버내에서 인-시튜로 실시하거나 그리드(grid)를 이용한 이온 가속법으로 반응성을 높인 시스템을 이용한다.On the other hand, the plasma processing method of the present invention uses a system that is performed in-situ in the chamber in which the deposition is performed, or the system which has increased the reactivity by the ion acceleration method using a grid (grid).
상기한 바와 같이, 고유전체막으로서 TaON을 증착할 때 종래에는 Ta2O5의 증착시 사용되었던 Ta(OC2H5)5근원물질을 동일하게 사용하고 여기에 NH3와 O2반응 가스를 첨가하여 TaON 박막을 형성하기 때문에 근원물질내의 산소 성분이 하부전극인 폴리실리콘과 반응하여 그 계면에 산화막을 형성한다. 그러나, 본 발명은 근원물질로서 산소성분이 없는 '아민'기로만 구성된 금속 유기물질을 사용하고 증착시 첨가되는 O2가스량을 조절하여 하부전극과 유전체 박막사이에 보다 안정한 계면을 생성한다.As described above, when depositing TaON as a high dielectric film, the same Ta (OC 2 H 5 ) 5 source material that was conventionally used for the deposition of Ta 2 O 5 is used, and NH 3 and O 2 reactant gases are used. Since the TaON thin film is added to form a TaON thin film, the oxygen component in the source material reacts with polysilicon as the lower electrode to form an oxide film at the interface. However, the present invention uses a metal organic material composed only of 'amine' groups having no oxygen component as a source material and controls the amount of O 2 gas added during deposition to create a more stable interface between the lower electrode and the dielectric thin film.
그리고, 본 발명은 고유전체 TaON박막과 그 위의 TaN 상부전극을 동일한 금속 유기물질로 형성함으로써 유전체막과 상부전극 사이에 열적으로 안정된 계면을 확보할 수 있으며 유전체 계면이 접착력이 향상되어 후속 열공정시 발생하는 계면 반응이 억제되어 전체 커패시터의 열화를 방지하고 낮은 누설 전류를 유지할 수 있는 효과가 있다.In addition, the present invention forms a thermally stable interface between the dielectric film and the upper electrode by forming the high-k dielectric TaON thin film and the TaN upper electrode thereon with the same metal organic material, and the dielectric interface is improved in the subsequent thermal process. The generated interfacial reaction is suppressed to prevent deterioration of the entire capacitor and to maintain a low leakage current.
또한, 본 발명의 커패시터 제조 방법은 동일한 챔버내에서 유전물질과 전극 물질을 인시튜로 연속 증착함으로써 계면 불순물에 의한 전기적 특성의 열화를 방지할 수 있는 장점을 가지고, 런 진행시 시간 지연을 막을 수 있으며 유전물질과 전극 물질을 따로 증착할 때 소요되는 장비 구입 및 유지 비용을 절감할 수 있다.In addition, the capacitor manufacturing method of the present invention has the advantage of preventing the deterioration of the electrical characteristics due to the interfacial impurities by continuously depositing dielectric material and electrode material in situ in the same chamber, it is possible to prevent time delay during run progress This reduces the cost of equipment acquisition and maintenance when depositing dielectric and electrode materials separately.
Claims (9)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100401503B1 (en) * | 2001-04-30 | 2003-10-17 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| US7005392B2 (en) * | 2001-03-30 | 2006-02-28 | Advanced Technology Materials, Inc. | Source reagent compositions for CVD formation of gate dielectric thin films using amide precursors and method of using same |
| KR100599440B1 (en) * | 2000-06-30 | 2006-07-12 | 주식회사 하이닉스반도체 | Method for manufacture capicitor |
| KR100772685B1 (en) * | 2001-06-26 | 2007-11-02 | 주식회사 하이닉스반도체 | A fabricating method of capacitor |
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1999
- 1999-07-01 KR KR1019990026378A patent/KR20010008502A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100599440B1 (en) * | 2000-06-30 | 2006-07-12 | 주식회사 하이닉스반도체 | Method for manufacture capicitor |
| US7005392B2 (en) * | 2001-03-30 | 2006-02-28 | Advanced Technology Materials, Inc. | Source reagent compositions for CVD formation of gate dielectric thin films using amide precursors and method of using same |
| KR100401503B1 (en) * | 2001-04-30 | 2003-10-17 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR100772685B1 (en) * | 2001-06-26 | 2007-11-02 | 주식회사 하이닉스반도체 | A fabricating method of capacitor |
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