KR20010005149A - Interface method for flash memory - Google Patents

Abstract

PURPOSE: An interface method between a flash controller and a flash memory is provided to perform an adequate interface control according to the size of a program buffer of the flash memory. CONSTITUTION: According to an interface method of a flash controller(10) which is connected to the first and the second flash memory(21,22) through the first and the second data bus(A,B), the flash controller transmits data in an amount of one page to the first flash memory continuously through the first data bus. And, after that, if a program execution of the first flash memory is performed by a program start command of the flash controller, the flash controller records data into the first and the second flash memory in turn by repeating a procedure of ordering the program start command by transmitting data of the next page to the second flash memory continuously through the second data bus.

Description

Interface method of flash memory {INTERFACE METHOD FOR FLASH MEMORY}

The present invention relates to an interface method of writing or reading data into a flash memory. More particularly, the present invention provides a method of writing data at a faster speed by reducing the access time of a flash memory having two memory locations. The present invention relates to an interface method of a flash memory that can access two types of flash memories having different sizes.

In general, a memory is composed of a plurality of memory cells arranged in a predetermined size and a program buffer of a predetermined size (520 bytes or 1040 bytes), and after inputting predetermined data into the program buffer, a program start command is given. The buffer data is stored in the memory cell. On the contrary, in the case of reading data, after moving the data stored in the memory cell to the program buffer, the external controller reads the data from the program buffer.

However, in recording data in a memory, the program buffer cannot hold other data because the data buffer has to maintain the data value for a certain time while storing the data input to the program buffer in a memory cell. Time is a significant part of the total recording time.

Therefore, there is a problem that the controller inevitably needs to be idle during the program time as described above.

In addition, the flash memory is divided into two types of program buffers that input / output data, that is, 528 bytes and 1040 bytes. However, when data is written in the same way regardless of the size of the program buffer, it is inefficient for a 1040 byte size. There is a problem that is.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The object of the present invention is to reduce the access time to the memory so that data can be written more quickly, and according to the program buffer size of the flash memory, appropriate flash control is performed. It provides an interface method between the controller and the flash memory.

1 is a schematic diagram showing the configuration of a controller and a flash memory.

FIG. 2 is a block diagram illustrating in detail the configuration of the controller in FIG. 1.

FIG. 3 is a flowchart showing a procedure of writing data to a 528-byte flash memory according to the present invention.

FIG. 4 is a flowchart showing a procedure of writing data to a 1040 byte flash memory according to the present invention.

5 is a timing diagram showing an operation state of the A bus and the B bus for transmitting data in each operation mode according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: controller 11: buffer

12: error correction parity generating unit 13: flash interface unit

20: flash memory 21: first memory

22: second memory section 31, 32: bus

As a construction means for achieving the above object of the present invention, the present invention provides a flash memory interface method of the flash controller connected to the first and second flash memory through the first and second data bus,

? It features.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.

Fig. 2 is a block diagram schematically showing the configuration of the memory controller and the memory. The buffer 11 temporarily stores data to be written or read data in the memory, and errors in data to be written from the buffer 11; An error correction parity generation unit 12 for generating correction parity, checking error correction parity in the read data, and transmitting the error correction parity to the buffer 11 and the error correction parity generated in the error correction parity generation unit 12 are included. A controller 10 comprising a flash interface unit 13 for inputting data to or reading data from the memory 20 through the data buses 31 and 32, and a plurality of memory cells are arranged. First and second memory units 21 and 22 which store the data in a predetermined unit (for example, 528 bytes or 1040 bytes) and read out the stored data in a predetermined unit (1 block = 16 Kbytes). A and B, which are data transmission paths for transferring data between the lash memory 20, the interface unit 13 of the controller 10, and the first and second memory units 21 and 22 of the flash memory 20. It consists of buses 31 and 32.

3 is a flowchart showing an operation flow of the interface unit 20 according to the present invention when the program buffer size of the flash memory is 528 bytes.

4 is a flowchart illustrating an operation flow of the interface unit 20 according to the present invention when the program buffer size of the flash memory is 1040 byte mode.

In the above-described apparatus, a case of writing data in the flash memory will be described. The data to be recorded is temporarily stored in the unit of a buffer (512 bytes) in the buffer 11 provided in the controller. The buffer 11 is a cache memory.

The data is read in order from the buffer 11 in page units, and this data is generated by the error correction parity generation unit 12 to generate error correction parity for each page. In general, the data size of one page is 512 bytes, and the error correction parity for each page is 6 bytes. Therefore, a total of 518 bytes of data and error correction parity are transmitted to the flash interface unit 13.

In addition, the flash interface unit 13 transfers and stores the data of which the error correction (ECC) encoding has been completed as described above to the flash memory 20 through the A bus 31 and the B bus 32 in turn. The controller 10 checks the program buffer size of the flash memory 20 and changes the data transmission order accordingly. Normally, the flash memory 20 stores a value indicating the size of the program buffer at a specific address. Therefore, the controller 10 requests information about the size of the program buffer from the flash memory 20 before the operation, and receives the size value of the program buffer stored at the specific address. Then, it is checked whether the data represents 528 bytes or 1040 bytes, and transfer control is carried out as follows according to the determination result.

First, in the case of 528 bytes, as shown in FIG. 3, a signal area (1 byte) for selecting whether to store data in the program area to store data, that is, the first memory unit 21 or the second memory unit 22, is stored. Send (301).

Then, after transmitting a command (1 byte) for inputting continuous data (302), a start address (3 bytes) is transmitted (303), and then ECC encoded by the error correction parity generation unit 12 to obtain error correction parity ( Data (6 bytes in total) including 6 bytes is transferred to the selected memory section (ie, the first memory section 21 or the second memory section 22). When the transfer is completed, a page program start command is issued to the corresponding memory unit (305). At this time, the memory unit (the first memory unit 21 or the second memory unit 22) starts a page program, which refers to a process of storing the received data in the corresponding memory cell. The data must be held in the buffer of the memory section for a predetermined time. Then, the program for one sector is completed by instructing a status read command (2 bytes) to confirm that the program has been properly performed.

In the series of processing as described above, after inputting 518 bytes of data consecutively in step 304, another data cannot be input at the moment when the page program proceeds to the next step 306. In the meantime, the controller 10 plays unnecessarily. Accordingly, in the present invention, as shown in FIG. 5A, the first page F1 is transferred to the first memory unit 21 via the A bus 31, and then a page program start command is transmitted to transmit the first page unit 1. When the page program is started at 21), the next page F2 is read and transferred to the second memory 22 via the B bus 32. When the transfer is completed, the program start command is issued as described above to allow the second memory 22 to program the transferred data. When the program of the first memory unit 21 is completed, the next page F3 is transferred to the first memory unit 21 by the A bus 31, and then the program is instructed. When the program is started at 21), the next page F4 is transmitted to the second memory unit 22 where the program for the second page F2 is completed via the B bus 32, and then the program is instructed. Therefore, odd-numbered pages are sequentially stored in the first memory unit 21, and even-numbered pages are sequentially stored in the second memory unit 22.

Therefore, the time taken to program one sector is the time taken to transfer one sector of data (518 bytes) to the programming time (about 200 ms) and the time taken to transmit one byte is 50 ms, so the actual time taken per sector. Becomes 200.545 ms + 518 bytes * 50 ms = 226.4 ms.

When the program buffer size of the flash memory 20 to be controlled is 1040 bytes, as shown in FIG. 4, first, the two memory units 21 and 22 constituting the flash memory 20 in the controller 10. Sends a region for storing data, i.e., a program region selection signal (1 byte), instructs the selected memory unit of the first continuous data input command (1 byte) (402), followed by a start address (3 bytes). In this case, pages 518 bytes in the corresponding order among the data recorded therein are transmitted and input (403, 404). When the transfer is completed, a second continuous data input command is then sent (405), followed by a start address (3 bytes) followed by continuous data (518 bytes) of the next page (406, 407).

When data is stored in a 1040 byte sized flash memory, two pages of data are continuously transmitted as much as two sectors of the corresponding flash memory, and then a page program start command is sent (408). Accordingly, the flash memory 20 starts the operation of programming the input data, and when the program is completed, the program for the two sectors is completed at the same time by sending a status read command to check whether the program is recorded (409).

During the program, the controller 10 performs a control operation to transfer the next two pages of data to another memory through another bus and program the same according to the above procedure.

As such, an embodiment of an operation state of two data buses 31 and 32 connecting the controller 10 and the flash memory 20 is shown in a timing diagram in FIG. 5B. First, the data recorded in the buffer 11 is shown. The first page F1 is transmitted to the first memory unit 21 via the A bus 31. When the transfer command and data transfer are performed for the first page F1, the next second page F2 is transferred to the second memory unit 22 via the B bus 32, and the third page F3 is the first page. The transfer is completed again to the first memory unit 21 via the A bus 31 where the transfer of F1 is completed. In this way, when the transfer of the third page F3 is completed and the input for one sector is completed, the controller 10 instructs the first memory unit 21 to start the program, so that the first memory unit 21 While executing the program, the next page F4 is transferred to the second memory section 22 via the B bus 32. Subsequently, the second memory unit 22 immediately instructs the program to be executed, and the second memory unit 22 executes a program for two pages F2 and F4. Since both the first memory unit 21 and the second memory unit 22 cannot execute input of another page while the program is being executed, the program remains in the idle state and the program is completed in the first memory unit 21. When the next page F5 is input to the first memory unit 21 via the A bus 31 in the same manner as described above, the B bus 32 is input to the second memory unit 22 where the program execution is completed. Enter the next page (F6) through.

As described above, the odd-numbered pages are sequentially stored in the first memory unit 21, and the even-numbered memories are sequentially stored in the second memory unit 22.

By doing so, the rest periods of the controller 10 and the data buses 31 and 32 are reduced, thereby reducing the recording time.

As described above, in the case of a control operation in the controller 10, the access time for two sectors in the 1040 byte mode is 200 ms (basic programming time) + 1036 bytes * 50 ns (transmission time per byte), about 252 ms. Becomes

As such, reading the data of the written flash memory into the buffer of the controller only needs to read in the input order. In the case of writing, the program takes a lot of time, but in the case of reading, it is only read and transmitted.

Basically, the time taken to read is about 300 ms + 7 ms with read command transfer (1 byte) + start address (3 bytes) + time from memory cell to register (7 ms) + WE BUSY (100 ms).

Therefore, when reading one page, it is necessary to continuously read 512 bytes + 6 bytes from the flash memory, calculate the EDC for the sector read by the error correction parity generator 22, and correct the error contained in the data read. In comparison with parity, the time taken to read one sector is approximately 33.2 ms based on the basic time + 518 bytes * 50 (transmission time per byte).

Even when all of one block (32 sectors) is read, as described above, when data are read alternately from the first and second memory units 21 and 22, the time taken for the data to move from the memory cell to the register (Ready / Busy interval = max 7 ms) and the time required to specify the read address (0.3 ms) can be saved, so it takes (33.2 ms (base time) -7.3) * 32 sectors = 828.8 ms. This is shorter than 33.2㎲ * 32 sectors = 1062 경우 when reading sequentially instead of reading.

Also, in the case of modifying and recording a part of the recorded data, the first and second memory units 21 and 22 alternately read data one by one, and have original data values. The contents are corrected and data of one block is alternately recorded in the first and second memory sections 21 and 22.

As described above, according to the interface method between the flash controller and the flash memory of the present invention, it is possible to reduce unnecessary idle time of the controller, to reduce access time, and to make the memory more quickly.

Claims (3)

In the flash memory interface method of the flash controller connected to the first and second flash memory through the first and second data bus, A first process of checking a program buffer size of the first and second flash memories; If the program buffer size of the first and second flash memory is 528 bytes, a second process of alternately transferring data for one page to the data proxy first and second flash memories and then programming the data; When the program buffer size of the first and second flash memory is 1040 bytes, a third process of alternately transferring data of two pages to the data proxy first and second flash memories and then starting the program is performed. Flash memory interface method. 2. The method of claim 1, wherein the second process includes transferring data for one sector to the first flash memory continuously through a first data bus, and then executing a program start command to execute a program of the first flash memory. Interface of flash memory, characterized in that alternately writing data to first and second flash memory by repeating the process of issuing program start command by continuously transferring next data for sector to second flash memory through second data bus. Way. The method of claim 1, wherein the third process continuously inputs one sector of data to the first flash memory through the first data bus, and then inputs data of the next sector to the second flash memory through the second data bus. After continuous input, the next data is continuously input to the first flash memory through the first data bus, and then the start of the program for the first flash memory is instructed, and the next data is input to the second flash memory through the second data bus. Instructing a program to the second flash memory and inputting data of two sectors alternately to write the data into the first and second flash memories.