JP2006164305A - External storage device and its memory access control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate memory access while performing error detection and correction by a single error correcting means in an external storage device that continuously accesses sector data. <P>SOLUTION: Sector data that is written by a host 2 is temporarily stored in a write buffer 7. A microprocessor 8 stores the sector data stored in the write buffer in a first memory when the sector data is odd number sector data and the sector data in a second memory 5 when the sector data is even number sector data. When the host 2 reads the sector data, a data switching means 11 outputs the N-th sector data read from the first memory to a system bus and simultaneously outputs the (N+1)-th sector data (next sector data to be read by host computer) read from the second memory to an error correcting means. Consequently, a time required for error detection and error correction of the (N+1)-th sector data is apparently shortened. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an external storage device of a computer using a static storage device. In particular, when sector data having an arbitrary byte width is continuously accessed in units of sectors, error detection and error correction of the sector data is performed at high speed. The present invention relates to an external storage device for processing.

  Conventionally, as a technique for simultaneously improving reliability and high-speed access in memory control, as described in Japanese Examined Patent Publication No. 6-105443, x-byte width data output from a memory is converted into an odd-numbered part (x / 2 bits wide) and even parts (x / 2 bytes wide), error detection and error correction are performed for each of odd parts and even parts using error correction codes, and output from odd parts and even parts. There is a system in which x / 2 byte wide data is continuously output to an x / 2 byte wide system bus by interleave control.

  By the way, in order to perform error detection and error correction on sector data having a width of m bytes (for example, 512 bytes), the sector data having a width of m bytes is divided into n bytes (for example, 1 byte) by m / n times (m Is a multiple of n) and must be input to the error correction means.

  However, the error detection and error correction in the above prior art is performed on data having the same byte width as that of the system bus, and error detection and sector data having a width of m bytes larger than the byte width of the system bus It cannot be applied as it is to those that perform error correction. In addition, the above-described prior art requires separate error correction means for both odd and even portions.

  The object of the present invention is to shorten the time required for error detection and error correction when performing error detection and error correction on sector data having a width of m bytes larger than the byte width of the system bus, thereby enabling high-speed memory access. It is to provide an external storage device to be realized.

  Another object of the present invention is to provide an external storage device that uses a single error correction means to reduce the time required for error detection and error correction and realize high-speed memory access.

In order to achieve the above object, the present invention provides:
A system interface unit that controls an interface with a host computer, and error detection and error correction for sector data composed of data having a number of bytes larger than the bus width of a system bus connecting the system interface unit and the host computer. Error correction means to perform,
A first memory and a second memory as static storage devices each having a memory bus having the same bus width as that of the system bus and storing sector data;
Control means for controlling read and write operations of sector data from the host computer to the first and second memories,
In response to a write command from the host computer, the control means stores a plurality of sector data accompanying the write command alternately in the first and second memories in units of sectors,
In response to the read command from the host computer, the control means reads the first sector data from the first memory among the plurality of sector data requested by the read command, and sends it to the error correction means. Then, while transferring the Nth sector data (N is a natural number) from one of the first and second memories to the system interface unit, the N + 1th sector data from the other is transferred to the error correction means. An external storage device is provided, wherein the sector data of the first and second memories are read simultaneously so as to be transferred.

  In this external storage device, preferably, the memory bus of the first memory is selectively connected to one of the system interface unit and the error correction means, and the memory bus of the second memory is connected to the other. Data switching means to be connected is provided, and the control means reads the sector data of the first and second memories while switching the data switching means at the time of read access from the host computer.

  A write buffer for temporarily storing sector data in a write access of sector data from the host computer to the first and second memories; and a sector to the first and second memories via the write buffer Data may be stored.

  Instead of the first and second memories, a memory having a memory bus having a bus width twice the bus width of the system bus and storing sector data may be used. In this case, in response to the write command from the host computer, the control means stores odd-numbered sector data among the plurality of sector data accompanying the write command in the memory on the upper side of the memory bus. In addition, the even-numbered sector data is stored in the memory on the lower side of the memory bus, and in response to the read command from the host computer, the first sector data among the plurality of sector data requested by the read command is stored. Sector data is read from the upper side of the memory and supplied to the error correction means, and then the Nth (N is a natural number) sector data from one of the upper side and the lower side of the memory is transferred to the system interface unit. In between, the (N + 1) th sector data from the other is transferred to the error correction means. The upper side of the memory and reading out the lower side of the sector data at the same time.

In addition, the memory access control method of the external storage device according to the present invention includes:
An external storage device having a static storage device for storing sector data, wherein the static storage device is a first memory for storing sector data of odd-numbered sectors among a plurality of consecutive sectors to be accessed; And having a second memory for storing sector data of even-numbered sectors, and error correction means for performing error detection and error correction on the sector data,
When write access is performed from the host computer to the plurality of consecutive sectors, the odd-numbered sector data is stored in the first memory together with the error correction code alternately for each sector, and the even-numbered sector data is also stored. Stored in the second memory together with the error correction code,
When performing read access to the plurality of consecutive sectors from the host computer, the first sector data is read from the first memory, error detection / correction is performed by the error correction means, and the error detection / correction is completed. During the transfer of the first sector data from the first memory to the host computer, the second sector data is read from the second memory and transferred to the error correction means, and then the error detection / correction is performed. While transferring the completed second sector data from the second memory to the host computer, the third sector data is read from the first memory and transferred to the error correction means, and error detection is performed in the same manner. -N + 1st sector data while transferring the corrected Nth sector data to the host computer The read out and performs control to be transferred to said error correcting means.

  According to the present invention, the control means (for example, a microprocessor) can store a plurality of write target sector data in the memory so that the Nth sector data and the N + 1th sector data can be read simultaneously. . Thus, the data switching means can output the Nth sector data to the system bus and simultaneously output the (N + 1) th sector data to the error correction means. Therefore, the time required for error detection and error correction for the (N + 1) th sector data can be simultaneously performed when the Nth sector data is output to the system bus. It is possible to apparently reduce the time required.

  Further, since error detection / correction is always executed only for the sector data next to the sector data transferred to the host computer, a single error correction means may be used.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a system configuration of an embodiment of an external storage device according to the present invention.

  Reference numeral 1 denotes a memory control device for writing or reading sector data to or from the first memory 4 and the second memory 5 in accordance with a command from the host computer 2, and the host computer is controlled by a control signal 22 and an external bus 32. 2 commands are accepted.

  The host computer 2 is connected to the system bus 3 by the host computer bus 31, and uses the control signal 22 and the system bus 3 to write and read sector data to the memory control device 1. The first memory 4 and the second memory 5 are storage means for storing sector data, respectively, and flash memory is used in this embodiment. A flash memory is known as a non-volatile semiconductor memory capable of electrically erasing and rewriting data in sectors of a predetermined number of bytes (for example, 512 bytes). However, the present invention can also be applied to other writable memories that are static storage devices. The local bus 6 is a bus connecting the memory control device 1, the write buffer 7 and the microprocessor 8. The write buffer 7 is storage means for temporarily storing the sector data written by the host computer 2, and is connected to the local bus 6 by the write buffer bus 61. The microprocessor 8 is connected to the local bus 6 by a microprocessor bus 62, analyzes a command set in the memory control device 1 by the host computer 2, and sets an operation to be performed by the memory control device 1.

  Here, when the bus width of the system bus 3 is M bytes, the bus width of the local bus 6 is the same M bytes as the system bus 3, and the bus widths of the first memory bus 111 and the second memory bus 112 are also The same M bytes as the system bus 3.

  The data switching unit 11 switches the sector data from the first memory bus 111 and the second memory bus 112 to the ECC bus 113 and the internal data bus 114. The error correction unit 12 generates an error correction code for the sector data from the internal data bus 114, and performs error detection and error correction for the sector data from the ECC bus 113. The system interface unit 13 receives a command for memory access from the host computer 2 through the control signal 22 and the external bus 32. At this time, the system interface unit 13 outputs an interrupt signal 131 to the microprocessor 8. Further, the system interface unit 13 generates a read signal 132, a write signal 133, a transfer end signal 134, and a timing signal 135 for the sector data from the read / write by the control signal 22.

  When the host computer 2 writes sector data, a write signal 133 is output, and the sector data from the host computer 2 is stored in the write buffer 7 from the internal data bus 114 at the timing of the timing signal 135. When the host computer 2 reads the sector data, a read signal 132 is output, and the sector data of the first memory bus 111 or the second memory bus 112 is read at the timing of the timing signal 135, and data switching means 11 to switch to the internal data bus 114 and output from the system interface unit 13 to the host computer 2. Further, at the same time as the sector data is output to the host computer 2, the sector data of the first memory bus 111 or the second memory bus 112 is switched to the ECC bus 113 by the data switching means 11, and the error correction means 12 Perform error correction.

  In FIG. 1, the portion shown below the system interface unit 13 can be incorporated in a memory card whose appearance is shown in FIG.

  FIG. 2 is a block diagram showing a configuration of the system interface unit 13.

  The data buffer 136 buffers sector data from the external bus 32 and sector data from the internal data bus 114. A command from the host computer 2 is set in the access setting register 137. The command indicates the start address of the sector data to be accessed, the type of access (read or write), and the number of sectors to be accessed. When the host computer 2 sets a command in the access setting register 137, the access setting register 137 outputs an interrupt signal 131. The access setting register 137 outputs a read signal 132 or a write signal 133 according to the set command. The control signal decoding unit 138 outputs a transfer end signal 134 and a timing signal 135 from the control signal 22. The transfer end signal 134 is output when access to one sector data is completed. The timing signal 135 is generated from the control signal 22 when the host computer 2 reads or writes sector data. The status register 139 stores data indicating the state of the memory control device 1. When the interrupt signal 131 is output and when the transfer end signal 134 is output, the status register 139 is set to the busy state. The microprocessor 8 sets the status register 139 to the ready state. When the status register 139 is busy, the host computer 2 does not read or write sector data.

  FIG. 3 is a block diagram showing the configuration of the data switching means 11.

  The data selection setting register 115 is storage means set by the microprocessor 8 and is information for selecting data to be output to the ECC bus 113 and the internal data bus 114 from the first memory bus 111 or the second memory bus 112. Is set. The read data selection circuit 116 selects data to be output to the internal data bus 114 from the first memory bus 111 or the second memory bus 112 according to the contents of the data selection setting register 115. The error correction means input data selection circuit 117 selects data to be output to the ECC bus 113 from the first memory bus 111 or the second memory bus 112 according to the contents of the data selection setting register 115.

  FIG. 4 shows a truth table of the read data selection circuit 116. Data to be output to the internal data bus 114 is selected from the first memory bus 111 or the second memory bus 112 in accordance with the contents of the data selection setting register 115.

  FIG. 5 shows a truth table of the error correction means input data selection circuit 117. Data to be output to the ECC bus 113 is selected from the first memory bus 111 or the second memory bus 112 according to the contents of the data selection setting register 115.

  Hereinafter, an operation in which the host computer 2 reads or writes sector data when the bus width of the system bus 3 is 1 byte will be described with reference to a flowchart.

  FIG. 6 is a flowchart when the host computer 2 reads or writes sector data.

  First, in S001, a command is set in the access setting register 137 in the system interface unit 13. This command includes the sector number of the access start sector and the number of sectors to be continuously accessed. Thereafter, the status register 139 is monitored (S002). When the status register 139 is set to the ready state, the host computer 2 reads or writes the data buffer 136 in units of 1 byte (S003). The operation of S003 is repeated until one sector data is read or written (S004). When reading or writing has not been completed for all sector data (S0005, No), the operations from S002 to S004 are repeated, and when reading or writing has been completed for all sector data, the host computer 2 read or write operation is completed.

  7 to 11 are flowcharts showing the operation of the microprocessor 8.

  First, in S <b> 101, the microprocessor 8 monitors whether the interrupt signal 131 indicating that the host computer 2 has set a command in the access setting register 137 has been output. When the interrupt signal 131 is output, the microprocessor 8 reads the access setting register 137 and analyzes the command set by the host computer 2 (S102).

  Next, in S103, if the access type is “write”, S104 is executed, and if it is “read”, the operation of the flowchart shown in FIG. 9 is executed.

  When the command of the access setting register 137 indicates “write”, the microprocessor 8 outputs an address 81 to the write buffer 7 in order to store the sector data to be written by the host computer 2 in the write buffer 7 ( S104), ready status is set in the status register 139 (S105).

  Thereafter, when one sector data is stored in the write buffer 7 from the host computer 2, the transfer end signal 134 is output from the control signal decoding unit 138. When the microprocessor 8 detects in S106 that the transfer end signal 134 has been output, the microprocessor 8 reads the error correction code stored in the error correction means 12 (S107). Next, the microprocessor 8 executes the operation of the flowchart shown in FIG.

  When the sector data stored in the write buffer 7 is the 2N-1th (that is, odd-numbered) sector data, the first memory address 82 for the first memory 4 is output (S109). The sector data is transferred to the first memory 4, and the error correction code is stored in the first memory 4 (S110). If the sector data stored in the write buffer 7 is the 2Nth (ie, even-numbered) sector data, the second memory address 83 for the second memory 5 is output (S111). The sector data is transferred to the second memory 5, and the error correction code is stored in the second memory 5 (S112).

  FIG. 17 shows the state of data stored in the first memory 4 and the second memory 5. As can be seen from the figure, each sector of the first and second memories stores data of one sector (here, 512 bytes) and an error correction code generated for the data. The error correction code in this embodiment is one in which one (here, 3 bytes) code is assigned to the data of one sector.

  When the writing of all the sector data from the host computer 2 is completed, the microprocessor 8 repeats the operation from S101, and when not completed, the microprocessor 8 repeats the operations from S104 to S112 (S113).

  When the command of the access setting register 137 indicates “read”, the operation of the flowchart shown in FIG. 9 is executed.

  First, the host computer 2 performs error detection and error correction on the sector data read first. Since the 2N-1st sector data is stored in the first memory 4, in order to input the first sector data to the error correction means 12, the microprocessor 8 sets “1” in the data selection setting register 115. 'Is set (S114). As a result, in the memory control device 1, the sector data read from the first memory 4 is switched and output to the ECC bus 113 by the data switching means 11, and error detection and error are detected for the sector data read from the first memory 4. Correction is performed by the error correction means 12. Here, the error correction code is also output from the first memory 4 following the sector data, and the error correction code is input to the error correction means 12. As a result, the error correction means 12 decodes the sector data read from the first memory 4 and can detect an error. In the memory control device 1, when the output of the sector data read from the first memory 4 is completed to the error correction unit 12, a transfer end signal 134 is output to the microprocessor 8. When the microprocessor 8 detects that the transfer end signal 134 has been output (S115), it reads the decoding result stored in the error correction means 12 (S116) and determines whether an error has occurred (S117). . If an error has occurred, the microprocessor 8 activates error correction processing for the error correction means 12 to know the error position and the correction pattern, and the error stored in the first memory 4 is detected. The correction result is written back to the generated sector data (S118). If no error has occurred, the process proceeds to S119 in FIG.

  Next, the microprocessor 8 performs the operation of the flowchart shown in FIG. In S119, the microprocessor 8 confirms whether the sector data to be output to the host computer 2 is the 2N-1th. In S120, the microprocessor 8 outputs “2N−1” -th sector data to the host computer 2 and simultaneously sets “0” in the data selection setting register 115 to input the 2N-th sector data to the error correction means 12. Set. In the next S121, the address of the sector data to be output to the host computer 2 is output to the first memory address 82, and the address of the sector data for error detection and error correction is output to the second memory address 83. In S122, the microprocessor 8 sets the data selection setting register 115 to “1” in order to output the 2N + 1st sector data to the error correction means 12 at the same time as outputting the 2Nth sector data to the host computer 2. . In S123, the address of sector data for error detection and error correction is output to the first memory address 82, and the address of sector data to be output to the host computer 2 is output to the second memory address 83. Thereafter, the microprocessor 8 sets the status register 139 to the ready state (S124).

  When the status register 139 is set to the ready state, the host computer 2 reads sector data from the memory control device 1. In S125, it is determined whether or not the transfer end signal 134 is output. When reading of one sector data is completed, a transfer end signal 134 is output from the control signal decoding unit 138 of the memory control device 1. When the transfer end signal 134 is output, the microprocessor 8 reads the decoding result stored in the error correction unit 12 (S126), and determines whether an error has occurred (S127 in FIG. 11). If an error has occurred, the microprocessor 8 activates error correction processing for the error correction means 12 to know the error position and the correction pattern, and stores them in the first memory 4 or the second memory 5. The correction result is written back to the stored sector data where the error has occurred (S128). If not, the process proceeds to S129.

  When the host computer 2 has finished reading all the sector data, the microprocessor 8 repeats the operation from S101, and when it has not finished, it repeats the operations from S119 to S128 (S129).

  Next, a specific processing example of the apparatus shown in FIG. 1 will be described with reference to timing charts shown in FIGS.

  FIG. 16 shows a write operation for writing sector data from the host computer 2 to the memories 4 and 5. When a write command is set in the access setting register 137 from the host computer 2 at time t0, an interrupt signal 131 is generated at time t1 to interrupt the microprocessor 8. At time t1, the status register 139 generates a busy signal. Thereafter, at time t2, the status register 139 generates a ready signal, and the microprocessor 8 generates an address 81 for the write buffer 7. After time t3, 512 bytes of data 1 to 512 are sequentially written to the designated address position of the write buffer 7 in accordance with the timing signal 135, byte by byte. Further, in accordance with the timing signal 135, 512 bytes of data 1 to 512 are input from the internal data bus 114 to the error correction unit 12, and the error correction unit 12 generates an error correction code. When the last data 512 is written at time t4, a transfer end signal 134 is output at time t5. Thereafter, the sector data thus stored in the write buffer 7 is written into the first or second memory 4 or 5 as described with reference to FIG. The results stored in the memories 4 and 5 are as shown in FIG.

  18 and 19 show a read operation for reading the sector data in the memories 4 and 5 from the host computer 2. First, in FIG. 18, when a read command is set from the host computer 2 to the access setting register 137 at time t6, an interrupt signal 131 is generated at the next time t7 to interrupt the microprocessor 8. Here, it is assumed that data of a plurality of sectors after the address “100” is read continuously. At time t8, the address “100” of the first sector to be read is given to the first memory address 82, and after time t8, 512 bytes of data from the first memory bus 111 and the accompanying 3-byte error correction code. Are sequentially read out byte by byte in accordance with the timing signal 135. These data are output as they are to the ECC bus 113 and input to the error correction means 12.

  Next, moving to FIG. 19, in order to output the data of the first sector for which the error check has been completed to the internal data bus 114 (that is, to the host computer 2 side), the switching state of the data switching means 11 is reversed. At time t9, the address of the first memory address 82 remains “100”, and the address of the second memory address 83 becomes “101”. After the time t10, the sector data at the address “100” is read from the first memory 4 again. This sector data is output to the internal data bus 114 side. In parallel with this, the 512-byte data of the second sector and the accompanying 3-byte error correction code are sequentially read out one byte at a time from the address “101” of the second memory 5, and this is read to the error correction means 12. Output to the connected ECC bus 113. After the reading of both sector data is completed, at time t11, the address “101” of the second memory 5 for which the error check has been completed is output to the memory address 82 of the first memory 4 and the second memory The address remains as “101”. The switching state of the data switching unit 11 is reversed. Thus, after time t12, the sector data at the address “101” is output to the internal data bus 114, and at the same time, the sector data at the address “102” as the next sector is output to the ECC bus 113 side.

  In this way, when reading data of consecutive sectors, sector data is continuously obtained on the internal data bus 114, and as a result, there is time for error check processing by the error correction means 12 from the host computer 2. Looks like not.

  As described above, according to the present embodiment, the microprocessor 8 stores the odd-numbered sector data stored in the write buffer 7 in the first memory 4 and the even-numbered sector data in the second memory 5. By storing the data, the host computer 2 can read the Nth sector data and at the same time output the (N + 1) th sector data to the error correction means 12, so that error detection and error correction can be performed for the (N + 1) th sector data. The time required can be apparently reduced.

  FIG. 12 is another example of a block diagram showing a system configuration of an external storage device according to the present invention.

  Except for the memory 9, the memory bus 91, and the data switching means 92, the configuration is the same as in FIG. The memory 9 has a bus width twice that of the first memory 4 and the second memory 5 shown in FIG. 1 and is connected to the data switching means 92 and the local bus 6 of the memory control device 1 by the memory bus 91. Connected. The data switching unit 92 switches the upper data and lower data from the memory bus 91 to the internal data bus 114 and the ECC bus 113.

  FIG. 13 is a block diagram showing a configuration of the data switching unit 92.

  The data selection setting register 115, the read data selection circuit 116, and the error correction means input data selection circuit 117 perform the same operations as those shown in the block diagram of FIG. Data from the memory bus 91 is input to the read data selection register 116 and the error correction means input data selection circuit 117 as upper data 911 and lower data 912. The read data selection register 116 outputs the upper data 911 or the lower data 912 to the internal data bus 114 according to the contents of the data selection setting register 115. Similarly, the error correction means input data selection circuit 117 also outputs upper data 911 or lower data 912 to the ECC bus 113.

  That is, even for the memory 9 having a bus width twice that of the system bus 3, the microprocessor 8 transfers the 2N-1st sector data stored in the write buffer 7 to the upper rank on the same memory bus. By storing the nth sector data in the lower order, the host computer 2 can read the Nth sector data and simultaneously output the (N + 1) th sector data to the error correction means 12, so that the N + 1th sector data The time required for error detection and error correction can be apparently reduced.

  FIG. 14 is another embodiment of the block diagram showing the system configuration of the external storage device according to the present invention.

  In FIG. 14, the write buffer 7 shown in the block diagram of FIG. 1 is not used. That is, the sector data written by the host computer 2 is directly stored in the first memory 4 or the second memory 5 instead of being temporarily stored in the write buffer. Therefore, the data switching means 93 switches the data from the internal data bus 114 to the first memory bus 111 or the second memory bus 112 and outputs the data when the host computer 2 writes sector data. FIG. 15 is a block diagram showing the configuration of the data switching means 93.

  The data selection setting register 115, the read data selection circuit 116, and the error correction means input data selection circuit 117 perform the same operations as those shown in the block diagram of FIG. The write data selection circuit 118 switches the sector data of the internal data bus 114 to the first memory bus 111 or the second memory bus 112 according to the contents of the data selection setting register 115 and outputs the data. When the data selection setting register 115 is “0”, the sector data of the internal data bus 114 is output to the first memory bus 111. When the data selection setting register 115 is “1”, the sector data of the internal data bus 114 is output. Output to the second memory bus 112.

  That is, the write data selection circuit 118 of the data switching unit 11 outputs the 2N-1st sector data to the first memory bus 111 and the 2Nth sector data to the second memory bus 112, thereby outputting the first The memory 4 stores 2N-1st sector data, and the second memory 5 stores 2Nth sector data. Thus, since the host computer 2 can read the Nth sector data and simultaneously output the (N + 1) th sector data to the error correction means 12, the time required for error detection and error correction for the (N + 1) th sector data. Apparently it can be shortened.

  As described above, according to the present invention, when the host computer writes sector data having an arbitrary byte width, the 2N-1th memory is formed in the first memory composed of a plurality of (one or more) memories. The 2Nth sector data can be stored in the second memory in the sector data. Thus, when the host computer reads the sector data, the 2N + 1-th sector data read from the first memory is output to the host computer, and at the same time, the 2N-th sector data read from the second memory (the next host computer It is possible to perform error detection and error correction in the error correction means. In addition, the 2Nth sector data read from the second memory is output to the host computer, and at the same time, the 2N-1st sector data read from the first memory (the sector data read by the host computer next) is error-corrected. It is possible to perform error detection and error correction in the means. Therefore, the time required for error detection and error correction can be apparently shortened by performing error detection and error correction on the sector data read by the host computer at the same time that the host computer reads the sector data. The memory access speed can be increased.

  Furthermore, for a memory connected to a memory bus having a bus width twice that of the system bus, 2N-1st sector data is stored on the upper side of the memory bus, and 2Nth sector data is stored on the lower side. . As a result, the 2N-1st sector data and the 2Nth sector data stored on the upper side of the memory bus can be read simultaneously, and at the same time the host computer reads the sector data, By performing error detection and error correction on the sector data read by, the time required for error detection and error correction can be apparently shortened, and the memory access speed can be increased.

The block diagram which shows the system configuration | structure of the external storage device of this invention. FIG. 3 is a block diagram showing a configuration of a system interface unit 13. 2 is a block diagram showing the configuration of data switching means 11. FIG. The chart which shows the truth table of the read data selection circuit. The truth table of the error correction means input data selection circuit 117. 6 is a flowchart showing the operation of the host computer 2. 7 is a flowchart showing the operation of the microprocessor 8; 7 is a flowchart showing the operation of the microprocessor 8; 7 is a flowchart showing the operation of the microprocessor 8; 7 is a flowchart showing the operation of the microprocessor 8; 7 is a flowchart showing the operation of the microprocessor 8; The block diagram which shows the system configuration | structure of the other Example of the external storage device of this invention. The block diagram which shows the structure of the data switching means 92. FIG. The block diagram which shows the system configuration | structure of the further another Example of the external storage device of this invention. The block diagram which shows the structure of the data switching means 93. FIG. The timing diagram which shows the operation example of the write process in an Example. Explanatory drawing of the 1st memory 4 and the 2nd memory 5. FIG. FIG. 6 is a timing diagram illustrating an operation example of read processing in the embodiment. FIG. 19 is a timing chart following the timing chart of FIG. 18. 1 is an external view of a memory card incorporating an external storage device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory control apparatus, 2 ... Host computer, 3 ... System bus, 4 ... 1st memory, 5 ... 2nd memory, 6 ... Local bus, 7 ... Write buffer, 8 ... Microprocessor, 9 ... Memory, 11 Data switching means, 12 Error correction means, 13 System interface section, 22 Control signal, 31 Host computer bus, 32 External bus, 61 Write buffer bus, 62 Microprocessor bus, 81 Write buffer address , 82 ... First memory address, 83 ... Second memory address, 84 ... Memory address, 91 ... Memory bus, 92 ... Data switching means, 93 ... Data switching means, 111 ... First memory bus, 112 ... First 2 memory buses, 113 ... ECC bus, 114 ... internal data bus, 115 ... data selection setting Register 116, Read data selection circuit, 117 ... Error correction means input data selection circuit, 131 ... Interrupt signal, 132 ... Read signal, 133 ... Write signal, 134 ... Transfer end signal, 135 ... Timing signal, 136 ... Data buffer, 137: Access setting register, 138: Control signal decoding unit, 139: Status register, 911: Upper data of the memory bus 91, 912: Lower data of the memory bus 91

Claims (13)

A system interface unit that executes an interface with a host computer via an external bus; a control unit that analyzes a command received from the host computer by the system interface unit and controls an operation performed in the storage device; In a storage device including a nonvolatile semiconductor memory that can electrically erase and rewrite data,
The nonvolatile semiconductor memory stores data received from the host computer via the system interface unit,
In response to a read command received from the host computer via the system interface unit, the control means transfers data after data processing to the host computer via the system interface unit, and the data processing A storage device for performing the transfer of the next data from the non-volatile semiconductor memory in parallel. The parallel operation of the transfer of the data after the data processing to the host computer via the system interface unit and the transfer of the next data for the data processing from the nonvolatile semiconductor memory includes two non-volatile operations. The storage device according to claim 1, wherein the storage device is executed using a volatile semiconductor memory. In response to a read command received from the host computer via the system interface unit, one of the two nonvolatile semiconductor memories generates data after the data processing, and the two nonvolatile semiconductor memories 3. The storage device according to claim 2, wherein the other generates the next data for the data processing. The storage device according to claim 2, wherein the nonvolatile semiconductor memory is a flash memory. One of the two nonvolatile semiconductor memories is connected to the control means via a first memory bus,
The other of the two nonvolatile semiconductor memories is connected to the control means via a second memory bus,
During the transfer of the data after the data processing to the host computer via the system interface unit, the data after the data processing is transferred to the host computer via the system interface unit and the data processing The next data for transfer from the other of the two non-volatile semiconductor memories via the second memory bus,
During the transfer of the next data for the data processing from the nonvolatile semiconductor memory, the next data after the data processing is transferred to the host computer through the system interface unit and the data processing 5. The storage device according to claim 2, wherein further data for transfer is transferred from one of the two nonvolatile semiconductor memories via the first memory bus. 6. A system interface unit that executes an interface with a host computer via an external bus; a control unit that analyzes a command received from the host computer by the system interface unit and controls an operation performed in the storage device; In a storage device including a nonvolatile semiconductor memory that can electrically erase and rewrite data,
The nonvolatile semiconductor memory stores data received from the host computer via the system interface unit,
In response to a read command received from the host computer via the system interface unit, the control means transfers the data after error detection / correction to the host computer via the system interface unit, and A storage device characterized in that the next data for error detection / correction is transferred in parallel from the nonvolatile semiconductor memory. The parallel operation of the transfer of the data after the error detection / correction to the host computer via the system interface unit and the transfer of the next data for the error detection / correction from the nonvolatile semiconductor memory, The storage device according to claim 6, wherein the storage device is executed by using the two nonvolatile semiconductor memories. In response to a read command received from the host computer via the system interface unit, one of the two nonvolatile semiconductor memories generates the data after the error detection / correction, and the two nonvolatile semiconductors 8. The storage device according to claim 7, wherein the other of the memories generates the next data for the error detection / correction. 9. The storage device according to claim 7, wherein the nonvolatile semiconductor memory is a flash memory. One of the two nonvolatile semiconductor memories is connected to the control means via a first memory bus,
The other of the two nonvolatile semiconductor memories is connected to the control means via a second memory bus,
During the transfer of the error-detected / corrected data to the host computer via the system interface unit, the error-detected / corrected data is transferred to the host computer via the system interface unit. The next data for error detection / correction is transferred from the other of the two nonvolatile semiconductor memories via the second memory bus,
During the transfer of the next data for error detection / correction from the nonvolatile semiconductor memory, the next data after the error detection / correction is transferred to the host computer via the system interface unit. 10. The next data for error detection / correction is transferred from one of the two nonvolatile semiconductor memories via the first memory bus. Storage device. A system interface unit that executes an interface with a host computer via an external bus, a control unit that controls a read operation and a write operation of data from the host computer, an error correction unit that performs data error detection and correction, In a storage device including a nonvolatile semiconductor memory that can electrically erase and rewrite data,
The nonvolatile semiconductor memory stores sector data received from the host computer via the system interface unit,
The control means reads out the Nth sector data from the nonvolatile semiconductor memory and performs error detection / correction by the error correction means when performing read access to a plurality of continuous sector data from the host computer, While transferring the Nth sector data after error detection / correction to the host computer, the (N + 1) th sector data is read from the nonvolatile semiconductor memory and transferred to the error correction means. A storage device that performs control. The error correction means is configured to read the (N + 1) th read from the nonvolatile semiconductor memory while transferring the Nth sector data after the error detection / correction to the host computer. 12. The storage device according to claim 11, wherein error detection / correction of sector data is performed. 13. The storage device according to claim 11, wherein the size of the sector data is 512 bytes.

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