JPH0981331A - Data processing management device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing management device of an inexpensive configuration which can fast process the data with no erasion of them even when the supply of power is cut off. SOLUTION: This management device includes a control circuit which performs the control to store the user data in the specific one of memory devices 9, 10 and 11, based on the parity data generated from the user data. When the newly produced user data are stored in the specific one of devices 9 to 11 via the buffer circuits 5, 6 and 7, the control circuit stores the corresponding parity data to other memory devices in cooperation with a stripe recognition circuit 2, a buffer control circuit 4 and a parity generation circuit 8. When the user data cannot be read out of the specific one of devices 9 to 11, the control circuit reads the parity data corresponding to the user data out of other memory devices. Then the control circuit instructs a device control circuit 3 to perform the control to restore the user data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is mainly applied to an information processing apparatus such as an office processor and a server, an array apparatus and the like, and stores parity data created from user data in a memory device.
ndant Array of Inexpensiv
e Discs) standard compliant data processing management device.

[0002]

2. Description of the Related Art Conventionally, as a technique related to this type of data processing management device, there is a disk array device disclosed in, for example, JP-A-5-324206 and JP-A-5-231155.

A data processing operation in these disk array devices will be described with reference to the RAID stripe configuration diagram shown in FIG.

In this disk array device, three memory devices 9, 10, 11 are configured in conformity with RAID5. Here, when rewriting the user data within the RAID stripe range, first, the user data of the memory devices 9 and 10 that is the current user data and the parity data of the memory device 11 that is the current parity data are first read. After that, new user data is written to the memory device 9, but at this time, the current user data is also written to the memory device 10 that has not been rewritten.

In this stripe configuration diagram, the device sector numbers 0, 1, 2, 3 correspond to 0, 1, 2, 3 in the memory device 9, and 4, 5, 6, in the memory device 10. 7 corresponds, memory device 11
In, P0, P1, P2, and P3 correspond. By the way,
In the figure, n is a sector unit of the memory devices 9, 10 and 11, and m is a stripe width in the RAID configuration.
The range of this stripe width is 4 sectors, and the RAI
It is 4 blocks for D configuration. The positive value in the figure is R
It is a block number when the AID is configured, and indicates that it is user data. Furthermore, Px (x = 0,
1, 2, 3) are parity data generated from user data for each sector number of the memory devices 9, 10, 11.

That is, in this disk array device, new parity data is generated by using the exclusive OR of new user data and the current user data, and then written to a predetermined memory device.

FIG. 4 exemplifies the contents of a data pattern relating to parity generation by the disk array device. FIG. 4A shows the data values of the current user data a1 and b1 and the current parity data c1. The figure (b) relates to the data values of the new user data a2, the current user data b1, and the new parity data c2, and the figure (c) shows the current user data a1, the current parity data c1, and the exclusive OR. Data d1 (exclusive OR regarding current user data a1 and b1),
And the data value of the new parity data c2.

That is, when the current data pattern is as shown in FIG. 4A when the parity is generated by the disk array device, conventionally, the parity of the new parity data c2 as shown in FIG. 4B is generated. After that, Fig. 4
Obtain a new data pattern corresponding to the current data pattern as shown in (c).

[0009]

In the case of the above-mentioned data processing management device (disk array device), the user creates new user data when the user data created by the user is stored in a specific memory device. When storing data in that memory device, it is necessary to update the parity data stored in another memory device.

In such a case, it is necessary to read the currently stored parity data and the currently stored user data from a specific memory device, and in order to speed up the data processing for all the memory devices used. Although a high-speed compatible memory device is used, the high-speed compatible memory device is more expensive than a normal memory device, so that the data processing management device is structurally expensive.

Further, the above-mentioned disk array apparatus discloses the case where a semiconductor device is used as a high speed memory device. However, since the semiconductor device needs to be supplied with power as needed to hold the stored data, power is supplied. If is cut off, the stored data will be lost. To prevent such data loss, it is possible to connect a battery or the like as an auxiliary power source, but such a measure also leads to high cost of the data processing management device. Incidentally, there is a similar problem when a cache memory is used as another high speed memory device.

Further, in the above-mentioned disk array device,
Data processing is being performed to read the current user data, which is required when new parity data is generated from new user data. There is a problem that the data processing requires a considerable processing time for accessing each device.

The present invention has been made to solve the above problems, and its technical problem is that data can be processed rapidly without being lost even when the power supply is cut off, and the cost is low. Another object of the present invention is to provide a data processing management device that can be configured into

[0014]

According to the present invention, a plurality of memory devices for storing user data created by a user and parity data is generated from the user data, and based on the generated parity data. In the data processing management device, the control circuit includes a control circuit that performs control for storing the user data in a specific one of the plurality of memory devices. When storing in a specific one of the memory devices, the parity data created from the user data is stored and stored in another memory device, and the user from a specific one of the plurality of memory devices is stored. Parity data corresponding to the user data from the other memory device when the data cannot be read Read data processing management apparatus including a device control circuit for performing control to recover the user data is obtained.

Further, according to the present invention, in the above-described data processing management device, the control circuit, when writing newly created user data to a specific one of the plurality of memory devices, is controlled by the control system external device. A predetermined instruction signal is output according to the result of determining whether or not the block information relating to the corresponding memory device to be transmitted is currently within the stripe range of the RAID configuration and the access state to the corresponding memory device by the device control circuit. There is obtained a data processing management device including a stripe recognition circuit and a parity generation circuit for generating parity data from user data according to a predetermined instruction signal.

Further, according to the present invention, in the above-mentioned data processing management device, the control circuit includes a plurality of buffer circuits according to the number of a plurality of memory devices for storing the user data and the parity data in a distinguishable manner. , Controlling storage of user data and parity data in a plurality of buffer circuits according to a predetermined instruction signal,
A data processing management device including a buffer control circuit for instructing the parity generation circuit to generate parity data is obtained.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The data processing management device of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of a data processing management device according to an embodiment of the present invention.

This data processing management apparatus generates a plurality of (here, three) memory devices 9, 10 and 11 for storing user data created by a user and parity data from the user data, and also creates parity data. A control circuit for controlling the storage of the user data in a specific one of the memory devices 9, 10, 11 based on the generated parity data, and a control system for transmitting block information regarding the corresponding memory device The information processing device 1 as a device.

Here, the control circuit is composed of a stripe recognition circuit 2, a buffer control circuit 4, a parity generation circuit 8, a device control circuit 3, and respective buffer circuits 5, 6, 7 and each part other than the device control circuit 3 Cooperate with each other to transfer the newly created user data to each buffer circuit 5, 6, 7
When storing in a specific one of the memory devices 9, 10, 11 via the same, the corresponding parity data is stored in another one and the user data from the specific one of the memory devices 9, 10, 11 is stored. When the data cannot be read, the device control circuit 3 performs control for reading the parity data corresponding to the other parity data and restoring the user data.

That is, in this control circuit, the stripe recognition circuit 2 is transmitted from the information processing device 1 when writing the newly created user data into a specific one of the memory devices 9, 10 and 11. A predetermined instruction signal is output according to the result of determining whether the block information about the corresponding memory device is within the stripe range of the RAID configuration at present, and the access state to the corresponding memory device by the device control circuit 3. . The parity generation circuit 8 generates parity data from user data according to a predetermined instruction signal.

Further, a plurality of buffer circuits 5, 6, 7 are provided (three in this case) according to the number of memory devices 9, 10, 11 in order to store user data and parity data in a distinguishable manner. Has been. The buffer control circuit 4 receives each of the buffer circuits 5 and 5 in response to a predetermined instruction signal.
It controls storage of user data and parity data for 6 and 7, and instructs the parity generation circuit 8 to generate parity data.

Therefore, the basic operation of the control circuit in this data processing management device (control in a single RAID stripe including parity generation) will be described below with reference to the RAID stripe configuration diagram of FIG.

In this data processing management apparatus, first, the stripe recognition circuit 2 receives from the information processing apparatus 1 head block number information and block length information as block information regarding a memory device to be newly rewritten. The stripe recognition circuit 2 determines whether or not the leading block number information and the block length information are within the stripe range of the memory device currently configured in RAID.

Therefore, assuming that the current RAID configuration is as shown in FIG. 2, where P0 is parity data of 0 block and 4 blocks, and in such a case, the stripe range is 4 blocks. The control within the stripe range when a write request with a block length of 1 and a block length of 2 is issued from the processing device 1 will be described.

The stripe recognition circuit 2 starts from the P1 block of the memory device 11 in which the parity data of the first block number is stored in the device control circuit 3 from the 2nd block.
The reading of the data for the block is activated, and the buffer circuit 6 is instructed to store the data. Further, the stripe recognition circuit 2 notifies the buffer control circuit 4 that it is within the stripe range.

When the buffer control circuit 4 receives the notification within the stripe range, the buffer control circuit 4 instructs the buffer circuit 6 to receive the data from the device control circuit 3, and then activates the data transmission to the device control circuit 3. To do. or,
The buffer control circuit 4 instructs the buffer circuit 5 to store new user data from the information processing device 1. After that, the buffer control circuit 4 starts transmission of new user data to the information processing device 1.

The information processing apparatus 1 transmits new user data to the buffer circuit 5 in order to temporarily store the new user data. When the data reception is completed, the buffer circuits 5 and 6 notify the buffer control circuit 4 of the completion of the data reception. The buffer control circuit 4 receives the notification of the end of data reception and then instructs the parity control circuit 8 to generate parity. Further, the buffer control circuit 4 instructs the buffer circuit 7 to store the generated new parity data after instructing the parity generation, and also instructs the buffer circuits 5 and 6 to store the data in the parity generation circuit 8. Instruct to send.

Upon receipt of the instruction, the parity generation circuit 8 generates new parity data using the new user data value and the current parity data value, and transmits the generated new parity data to the buffer circuit 7. When the storage of the new parity data is completed, the buffer circuit 7 notifies the buffer control circuit 4 of the end of the storage. The buffer control circuit 4 notifies the parity generation circuit 8 of the end of parity generation and then instructs the stripe recognition circuit 2 to write user data.

After receiving the notification, the stripe recognition circuit 2 receives the data from the buffer circuit 5 to the device control circuit 3 and writes the block length data to the memory device 9 corresponding to the head block. Give instructions. Further, the stripe recognition circuit 2 notifies the buffer control circuit 4 that the device control circuit 3 has been instructed.

When the device control circuit 4 receives the notification,
After instructing the buffer circuit 5 to transmit data to the device control circuit 3, the device control circuit 3 is activated to receive data. When the data transmission is completed, the buffer circuit 5 notifies the buffer control circuit 4 of the end of the data reception. The buffer control circuit 4 is
After receiving the end notification, the stripe recognition circuit 2 is instructed to write the parity data.

After receiving the notification, the stripe recognition circuit 2 receives the data from the buffer circuit 6 to the device control circuit 3, and from the P1 block to the memory device 11 in which the parity data of the head block number is stored. Instruct to write the data of the P2 block. When the data transmission is completed, the buffer circuit 6 notifies the buffer control circuit 4 of the end of the data reception.

Next, the control in the case where the information processing apparatus 1 makes a write request with the head block number 3 and the block length 2 (outside the stripe range) will be described.

The stripe recognizing circuit 2 stores the parity data of the first block number for the device control circuit 3 from the memory device 11 in the P3 block 1st block.
Reading of data for a block is activated, and thereafter, data for one block of the 0th block is read from the memory device 11 and the buffer circuit 6 is instructed to store the data. Further, the stripe recognition circuit 2 notifies the buffer control circuit 4 that it is out of the stripe range.

When the buffer control circuit 4 receives the notification outside the stripe range, the buffer control circuit 4 instructs the buffer circuit 6 to receive the data from the device control circuit 3, and then activates the data transmission to the device control circuit 3. . The buffer control circuit 4 also instructs the buffer circuit 5 to store new user data from the information processing device 1. After that, the buffer control circuit 4 starts transmission of new user data to the information processing device 1.

The information processing device 1 sends a notification to the buffer circuit 5 to temporarily store new user data. When the data reception is completed, the buffer circuits 5 and 6 notify the buffer control circuit 4 of the completion of the data reception.
The buffer control circuit 4 receives the notification of the end of data reception and then instructs the parity control circuit 8 to generate parity. Further, the buffer control circuit 4 instructs the buffer circuit 7 to store the generated new parity data after instructing the parity generation, and also instructs the buffer circuits 5 and 6 to store the data in the parity generation circuit 8. Instruct to send.

Upon receipt of the instruction, the parity generation circuit 8 generates new parity data using the new user data value and the current parity data value, and transmits the generated new parity data to the buffer circuit 7. When the storage of new parity data is completed, the buffer circuit 7 notifies the buffer control circuit 4 of the completion. The buffer control circuit 4 notifies the parity generation circuit 8 of the end of parity generation and then instructs the stripe recognition circuit 2 to write user data.

After receiving the notification, the stripe recognition circuit 2 receives the data from the buffer circuit 5 to the device control circuit 3, and transfers one block of data to the third block to the memory device 9 corresponding to the head block. writing,
After that, the memory device 10 to which the block next to the first block is assigned is instructed to write the data for one block to the fourth block. Further, the stripe recognition circuit 2 notifies the buffer control circuit 4 of the instruction to the device control circuit.

Upon receiving the notification, the device control circuit 4 instructs the buffer circuit 5 to transmit data to the device control circuit 3, and then activates the device control circuit 3 to receive data. When the data transmission is completed, the buffer circuit 5 notifies the buffer control circuit 4 of the data reception completion. The buffer control circuit 4 is
After receiving the end notification, the stripe recognition circuit 2 is instructed to write the parity data.

After receiving the notification, the stripe recognition circuit 2 receives the data from the buffer circuit 6 to the device control circuit 3, and goes to the P3 block of the memory device 11 in which the parity data of the head block number is stored. 1
It is instructed to write the data of the block and then write the data of one block to the P0th block of the memory device 11. When the data transmission is completed, the buffer circuit 6 notifies the buffer control circuit 4 of the data reception completion.

FIGS. 2A to 2C are timing charts illustrating the data processing contents corresponding to the processing time t by the data processing management device. FIG. 2A relates to the conventional device and FIG. (B) relates to the case within the stripe range of the embodiment apparatus, and (c) of the figure relates to the case outside the stripe range of the embodiment apparatus.

From FIG. 2A, in the conventional apparatus, when the user data is stored in the memory device, when the user newly creates the user data and stores it in the memory device, the user data is stored in another memory device. Since it is necessary to update the stored parity data and read the currently stored parity data and the currently stored user data, the processing time t required for data processing
You can see that is getting longer.

On the other hand, from FIG. 2B and FIG. 2C, in the apparatus of the embodiment, the user data is stored in the memory device, and when the user uses the stored user data again, the memory device is used. When the user data is read from the memory device and the user data is stored in the memory device, the parity data is created from the user data, the parity data is stored in another memory device, and the memory device storing the user data fails. If the data cannot be read due to other reasons, the parity data is read and the user data is restored. Therefore, the current user data becomes unnecessary when the new parity data c2 is generated, and the processing time t required for data processing is smaller than that in the conventional device. You can see that it is much shorter.

Control (generation of parity data) in the parity generation circuit 8 of the data processing management device will be described below with reference to FIGS. 4 (a) to 4 (c).

When rewriting the data pattern of the current user data value, first, the pattern value of the new user data a2 for rewriting and the current parity data c1.
Get the exclusive OR of with the pattern value of. Next, it is determined whether the pattern value of the new user data a2 and the current pattern value of the parity data c1 are the same from the result value of the exclusive OR. Here, if the pattern values are the same, the result of the exclusive OR is 0, and if they are different, it is 1. Therefore, when the result of the exclusive OR is 0, the pattern value of the new user data a2 is inverted. Then, the pattern value of the new parity data c2 is set, and when the result of the exclusive OR is 1, the pattern value of the new user data a2 is set as the pattern value of the new parity data c2.
As a result, the parity generation circuit 8 outputs the generated new parity data c2.

[0046]

As described above, according to the data processing management apparatus of the present invention, when the user data is stored in the memory device and the user uses the stored user data again, the user data is stored in the memory device. When reading and storing user data in the memory device, parity data is created from the user data, the parity data is stored in another memory device, and the memory device in which the user data is stored cannot be read due to a failure or the like. In this case, the parity data is read and the user data is restored.Therefore, the data in the memory device is not lost even when the power is cut off, and the current user data is not needed when new parity data is generated. The processing time required for processing is much shorter than with conventional equipment. Order to improve over data processing speed, memory device is adapted to be quickly perform data processing be connected Dejichen.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a data processing management device according to an embodiment of the present invention.

2A and 2B are timing charts exemplifying data processing contents corresponding to processing time by the data processing management device shown in FIG. 1, where FIG. 2A is related to a conventional device and FIG. Related to cases,
(C) relates to the case where the stripe is outside the stripe range of the apparatus of the embodiment.

FIG. 3 is a diagram showing a RAID stripe configuration in a disk array device which is an example of a conventional data processing management device.

4A and 4B show examples of data pattern contents relating to parity generation by the disk array device described in FIG. 3, where FIG. 4A shows data values of current user data and current parity data, and FIG. User data, current user data, and data values of new parity data. (C) relates to data values of current user data, current parity data, exclusive OR data, and new parity data.

[Explanation of symbols]

 1 Information processing device 2 Stripe recognition circuit 3 Device control circuit 4 Buffer control circuit 5, 6, 7 Buffer circuit 8 Parity generation circuit 9, 10, 11 Memory device

Claims (3)

[Claims] 1. A plurality of memory devices for storing user data created by a user, parity data generated from the user data, and the user data stored in the plurality of memories based on the generated parity data. In a data processing management device including a control circuit that performs control for storing in a specific one of the devices, the control circuit is configured to control the user data newly created by a user among the plurality of memory devices. When the parity data created from the user data cannot be stored and stored in another memory device and stored in a specific one, and the user data cannot be read from a specific one of the plurality of memory devices. Read the parity data corresponding to the user data from the other memory device, A data processing management apparatus including a device control circuit for performing control for recovering user data. 2. The data processing management device according to claim 1, wherein the control circuit writes the newly created user data to a specific one of the plurality of memory devices, and a control system external device. The block information about the corresponding memory device transmitted from the current RAID
A stripe recognition circuit that outputs a predetermined instruction signal according to the result of determining whether it is within the stripe range of the constituents and the access state to the corresponding memory device by the device control circuit, and the predetermined instruction signal And a parity generation circuit for generating parity data from the user data according to the data processing management apparatus. 3. The data processing management device according to claim 2, wherein the control circuit has a plurality of buffers according to the number of the plurality of memory devices for storing the user data and the parity data in a distinguishable manner. A circuit, and a buffer control circuit that controls storage of the user data and the parity data in the plurality of buffer circuits according to the predetermined instruction signal and that instructs the parity generation circuit to generate the parity data. A data processing management device comprising: