KR20010004536A - Auto redundancy circuit - Google Patents

Abstract

PURPOSE: An automatic redundancy circuit is provided to additionally make acceptance an information presenting whether an address is a row address when it is a row active or a column address when it is a column active except an address information inputted from the outside and to use all of a row redundancy and a column redundancy with one fuse CONSTITUTION: An automatic redundancy circuit includes first and second power supply voltage supplying portions(10,60), a result displaying portion(30), an address information comparing portion(40), and a column/row information comparing portion(50). The first and second power supply voltage suppling portions respectively supply at least first and second power supply voltage sources. The result displaying portion outputs whether there is a repair operation or not. The address information comparing portion transmits the second power supply voltage source by the result compared an address information inputted from the outside to an information programmed to a fuse into the result displaying portion. The column/row information comparing portion transmits the second power supply voltage source by the result compared a column/row information signal inputted from the outside to a column/row redundancy selection information programmed to a fuse into the result displaying portion.

Description

Auto redundancy circuit

The present invention relates to a redundancy circuit, and more particularly, to an automatic redundancy circuit that enables the use of both ROW redundancy and column redundancy with a single redundancy fuse.

In general, a low-frequency redundancy circuit replaces a word line (bit line) to which a defective cell is connected with an extra spare word line (bit line) when a defect occurs in any cell in the cell array. A device that compensates for defects. When an address for selecting a defective cell is applied to the inside of a device, a normal path for selecting a defective cell is broken, and instead, a redundancy circuit operates to connect a repaired cell to a word line (bit). By enabling the ROH (column) redundancy operation is made.

However, in the conventional redundancy fuse circuit configured as described above, it is impossible to use the redundancy fuse in a matrix form to perform repairs by performing only one of the redundancy and the column redundancy. That is, since the redundancy and the column redundancy are to operate in independent structures, it is not possible to use the row redundancy by using the column redundancy fuse or the column redundancy by using the redundancy. As a result, if all of the column redundancy fuses were used, they could not be used for column repair even though the low redundancy fuses were left unused. On the contrary, if all of the row redundancy fuses were used, they could not be used for the row repair even if the column redundancy fuses were left unused. Therefore, the conventional redundancy fuse circuit has a problem in that the redundancy circuit and the column redundancy circuit are separately configured to occupy the layout area by that amount and reduce the redundancy efficiency.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to receive information indicating whether the address is a row address at the time of a row active or a column address at the time of a column active in addition to the address information input from the outside. It is intended to provide an automatic redundancy circuit that allows the use of both fuse and column redundancy with one fuse.

1 is an automatic redundancy circuit diagram according to a first embodiment of the present invention.

2 is an operation timing diagram according to the first embodiment

3 is an automatic redundancy circuit diagram according to a second embodiment of the present invention.

4 is an operation timing diagram according to the second embodiment.

Explanation of symbols on the main parts of the drawings

10,12: first power supply

30,32: result display unit 40,42: address information comparison unit

50,52: column / row information comparison unit 60,62: second power supply unit

In order to achieve the above object, the automatic redundancy circuit according to the present invention,

In the redundancy circuit of a semiconductor memory device,

At least first and second power supply voltage source supplying means for supplying first and second power supply voltage sources, respectively;

Result display means for outputting whether or not the repair operation;

Address information comparing means for transferring the second power supply voltage source to the result display means based on a result of comparing the address information input from the outside with information programmed into the fuse;

And a column / row information comparison means for passing the second power supply voltage source to the result display means by comparing the column / row redundancy selection information programmed in the fuse with the externally input column / row information signal. It is done.

Here, the first power source voltage source is a power source voltage, and the second power source voltage source is a ground voltage.

In addition to the above configuration, the result display means is a precharge PMOS connected between the first power supply voltage and an inverter connected between one node and an output terminal which are outputs of the address information comparing means and the column / roo information comparing means. It is preferred to be configured.

And a first PMOS transistor for transmitting the first power supply voltage source to one node of the result display means by a precharge signal, and one side of the result display means for sending the first power supply voltage source by a level signal of the output terminal. It is preferable to further configure a second PMOS transistor to be delivered to the node.

The address information comparing means includes one fuse and an NMOS transistor whose source terminal is connected to the fuse and switched by an address signal applied to a gate between one node of the result display means and the second power supply voltage source. It is preferable that the number of input addresses or a double of them (when an address comes in at A // A) be connected in parallel.

The column / roo information comparison means has an NMOS type having a fuse connected in series between one node of the result display means and the second power supply voltage source, and one terminal connected to the fuse and switched by a column / row information signal. It is preferable that it is comprised with a transistor. In this case, the column / roo information signal is preferably a signal decoded from an external control signal such as RASB, CASB, and the like.

In addition, another automatic redundancy circuit according to the present invention,

In the redundancy circuit of a semiconductor memory device,

At least first and second power supply voltage source supplying means for supplying first and second power supply voltage sources, respectively;

Result display means for outputting whether or not the repair operation;

Address information comparing means for transferring the second power supply voltage source to the result display means based on a result of comparing the address information input from the outside with information programmed into the fuse;

And a column / row information comparison means for transferring the second power voltage source to the result display means by comparing the column / row redundancy selection information programmed in the fuse with the externally input column / row information. do.

Here, the first power source voltage source is a ground voltage, and the second power source voltage source is a power source voltage.

The result display means is preferably composed of an inverter connected between an output terminal and one node which is an output of the address information comparing means and the column / roo information comparing means.

And a first NMOS transistor for transmitting the second power supply voltage source to one node of the result display means by a precharge signal, and one side of the result display means for sending the second power supply voltage source by a level signal of the output terminal. It is preferable to further configure a second NMOS transistor to be delivered to the node.

The address information comparing means includes a fuse and a PMOS transistor whose source terminal is connected to the fuse and switched by an address signal applied to a gate, between the second power supply voltage source and one node of the result display means. It is preferable to connect in parallel by the number of addresses to be used or twice that (when an address is input to A and / A).

The column / row information comparing means includes a fuse connected in series between the second power supply voltage source and one node of the result display means, and a terminal connected to one side of the fuse and switched by a column / row information signal. It is preferable that it is comprised with a transistor. In this case, it is preferable that the column / roo information signal is a signal obtained by decoding an external control signal such as RASB, CASB, or the like.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

FIG. 1 is an automatic redundancy circuit diagram according to a first embodiment of the present invention, in which a redundancy determined by comparing a power supply voltage unit 10 supplying a power supply voltage Vdd with externally input address information and information programmed into a fuse. The result display unit 30 outputs out of the redundancy fuse circuit, an address information comparison unit 40 which receives a column / roo address and compares it with information programmed in the fuse, and column / roo information programmed in the fuse. Investigate the connection state of the fuse and the column / roo information comparison unit 50 which outputs a signal compared with the inputted column / roo information from the outside, and initializes the fuse circuit for the investigation of the input address and information to be input next. It is composed of a precharge unit 20 for transferring the power supply voltage to the result display unit to return to the state.

Hereinafter, the detailed configuration and operation of the automatic redundancy circuit according to the present invention will be described.

First, the precharge unit 20 includes a PMOS transistor P1 that transfers a power supply voltage Vdd to the node A when the precharge signal PCG has a low state, and a voltage of an output terminal out. It consists of a PMOS transistor P2 which transfers Vdd to the node A when the level signal has a low.

The result display unit 30 is composed of an inverter INV1 connected between the node A and the output terminal out.

In addition, the address information comparing unit 40 includes the number of addresses to which an NMOS transistor, which is switched by a fuse and an address signal connected to a source terminal connected to the fuse, is input between the node A and the ground voltage Vss. Are connected in parallel. At this time, the fuse cuts the fuse connected to the NMOS transistor in which the address for selecting the defective cell is input in advance by laser to break the path of the address where the defective cell is generated and replace the spare cell. In the figure, the fuse f2 is cut off. At this time, when the address signal A1 for selecting the defective cell is input, the potential of the output terminal out is outputted as 'low', thereby performing a repair operation.

The column / row information comparison unit 50 refers to an external input control signal such as a fuse f5 and a column / row information signal XY; CSB, RASB, CASB, and WEB connected in series between the node A and the Vss terminal. Is composed of an NMOS transistor N5 that is switched by.

The operation of the automatic redundancy circuit of the present invention having the above configuration will be described in detail with reference to the operation timing shown in Figs. 2A to 2H.

First, when the precharge signal PCG becomes 'low' level at time t1, the node A is precharged to a 'high' level. Then, at time t3, the input address and the column / row information signal XY are input. The address entered at this point is an address that does not match the address programmed into the fuse. That is, the address programmed in the fuse means A0 = 0, A1 = 1, A2 = 0, A3 = 0, and XY = 1, but the address input at the time point t3 shown in FIG. It's time. Therefore, node A falls to the 'low' level at this time t3. At this time, the output signal (out) is a 'high' level indicates that the situation does not use redundancy.

Next, when the precharge signal PCG comes in again at time t5, the node A is again precharged to the 'high' level, waiting for the next input address and column / roo information signal.

Then, at the time t7, the case where the column address 2 (A1) like the one programmed in the fuse is input to the input of the circuit will be described. in this case. The addresses A0, A2, and A3 all have a 'low' level, so the NMOS transistors N1, N3, N4 are all turned off and the address A1 becomes high, and the NMOS transistor N2 is turned on, but the fuse (f2) The node A remains in the precharged 'high' level because no path is formed to allow current to go to Vss. Therefore, the output signal out becomes the 'low' level, indicating that the situation should use redundancy.

FIG. 2 is an automatic redundancy circuit according to a second embodiment of the present invention, and a redundancy determined by comparing a power supply voltage unit 62 supplying a power supply voltage Vdd with externally input address information and information programmed into a fuse. The result display unit 32 outputs the redundancy fuse out of the redundant fuse circuit, the address information comparison unit 42 which receives the column / roo address and compares it with the information programmed in the fuse, and the column / roo information programmed in the fuse. A column / roo information comparator 52 for outputting a signal compared with externally inputted column / roo information, and after inspecting a connection state of the fuse, initializing a fuse circuit for the investigation of an input address and information to be input next. It is composed of a precharge unit 21 for transferring the power supply voltage to the result display unit to return to the state.

The precharge unit 22 includes an NMOS transistor N11 that transfers the ground voltage Vss to the node B when the precharge signal PCG has a high state, and a voltage level signal at the output terminal out. Is composed of an NMOS transistor N12 that transfers Vss to the node B when it has high.

The result display unit 32 is composed of an inverter INV2 connected between the node B and the output terminal out.

In addition, the address information comparing unit 42 includes the number of addresses into which a PMOS transistor, which is switched by a fuse and an address signal connected to a source terminal connected to the fuse, is input between the node B and the power supply voltage Vdd. Are connected in parallel. At this time, the fuse cuts the fuse connected to the PMOS transistor in which the address for selecting the defective cell is input in order to cut off the path of the address where the defective cell is generated and replace the spare cell with the laser. In the figure, the fuse f12 is cut off. At this time, when the address signal A1 for selecting the defective cell is input, the potential of the output terminal out is outputted as 'high', thereby performing a repair operation.

The column / row information comparison unit 52 refers to an external input control signal such as a fuse f15 and a column / row information signal XY; CSB, RASB, CASB, and WEB connected in series between the node B and the Vdd terminal. It is composed of a PMOS transistor P15 that is switched by.

The operation of the automatic redundancy circuit of the present invention having the above configuration will be described in detail with reference to the operation timing shown in Figs. 4A to 4H.

First, when the precharge signal PCG becomes 'high' level at time t1, the node B is precharged to a 'low' level. Then, at time t3, the input address and the column / row information signal XY are input. The address entered at this point is an address that does not match the address programmed into the fuse. That is, the address programmed in the fuse means A0 = 0, A1 = 1, A2 = 0, A3 = 0, XY = 1, and means the column (Y) address 2, but the address input at the time point t3 shown in FIG. Rho (X) address 15. Therefore, Node B goes up to the 'high' level at this time t3. At this time, the output signal (out) is a 'low' level indicates that the situation does not use redundancy.

Next, when the precharge signal PCG is input again at time t5, the node B is precharged to the 'low' level again, and waits for the next input address and column / row information signal.

Then, at the time t7, the case where the column address 2 (A1) like the one programmed in the fuse is input to the input of the circuit will be described. in this case. All of the addresses A0, A2, and A3 have a 'high' level, so the PMOS transistors P11, P13, and P14 are all turned off and the address A1 is turned low so that the PMOS transistor P12 is turned on, but the fuse (f12) is turned on. ), The node B remains at the precharged 'low' level because no path is formed to allow current to go to Vdd. Therefore, the output signal out is at the 'high' level, indicating that redundancy should be used.

The automatic redundancy circuit according to the present invention can be variously implemented by adding the column / roo information comparison means newly implemented in the present invention to the existing redundancy fuse circuit in addition to the above-described first and second embodiments.

As described above, according to the automatic redundancy circuit of the present invention, in addition to the address information input from the outside, it is possible to further receive information indicating whether the address is a row address at a row active or a row address at a column active. One fuse has a very good effect of using both redundancy and column redundancy.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (14)

In the redundancy circuit of a semiconductor memory device, At least first and second power supply voltage source supplying means for supplying first and second power supply voltage sources, respectively; Result display means for outputting whether or not the repair operation; Address information comparing means for transferring the second power supply voltage source to the result display means based on a result of comparing the address information input from the outside with information programmed into the fuse; And a column / row information comparison means for passing the second power supply voltage source to the result display means by comparing the column / row redundancy selection information programmed in the fuse with the externally input column / row information signal. Automatic redundancy circuit. The method of claim 1, The first power source voltage source is a power source voltage, And the second power supply voltage source is a ground voltage. The method of claim 1, wherein the result display means, And an inverter connected between an output terminal and one node which is an output of the precharge means, the address information comparison means, and the column / roo information comparison means. The method of claim 1, wherein the precharge means, A first PMOS transistor that transfers the first power source voltage source to one node of the result display means by a precharge signal, and the first power source voltage source to one node of the result display means by a level signal of the output terminal; An automatic redundancy circuit comprising a second PMOS transistor for transmitting. The method of claim 1, wherein the address information comparing means comprises: One fuse and an NMOS transistor in which a source terminal is connected to the fuse and switched by an address signal applied to a gate are connected in parallel by the number of addresses input between one node of the result display means and the second power supply voltage source. Automatic redundancy circuit characterized in that. The method of claim 1, wherein the column / row information comparison means, An automatic redundancy circuit comprising a fuse connected in series between one node of the result display means and the second power supply voltage source, and an NMOS transistor connected to one terminal of the fuse and switched by a column / row information signal; . The method of claim 1, wherein The column / roo information signal is an automatic redundancy circuit, characterized in that the external control signal such as CSB, RASB, CASB, WEB. In the redundancy circuit of a semiconductor memory device, At least first and second power supply voltage source supplying means for supplying first and second power supply voltage sources, respectively; Result display means for outputting whether or not the repair operation; An address information comparing means for transferring the first power source voltage source to the result display means based on a result of comparing the address information input from the outside with information programmed into the fuse; Column / roo information comparison means for transferring the first power voltage source to the result display means by comparing the column / row redundancy selection information programmed in the fuse with the externally input column / roo information; And a precharge means for transferring said second power supply voltage source to said result display portion by a precharge signal. The method of claim 8, The second power supply voltage source is a power supply voltage, And the first power source voltage source is a ground voltage. The method of claim 8, wherein the result display means, And an inverter connected between an output terminal and one node which is an output of the precharge means, the address information comparison means, and the column / roo information comparison means. The method of claim 8, wherein the precharge means, A first NMOS transistor that transfers the first power supply voltage source to one node of the result display means by a precharge signal, and the second power supply voltage source to one node of the result display means by a level signal of the output terminal; An automatic redundancy circuit comprising a second NMOS transistor for transmitting. 9. The apparatus of claim 8, wherein the address information comparing means comprises: One fuse and a PMOS transistor in which a source terminal is connected to the fuse and switched by an address signal applied to the gate are connected in parallel by the number of addresses input between the second power source voltage source and one node of the result display means. Automatic redundancy circuit, characterized in that. The method of claim 8, wherein the column / row information comparison means, An automatic redundancy circuit comprising a fuse connected in series between the second power source voltage source and one node of the result display means, and a PMOS transistor connected to one terminal of the fuse and switched by a column / row information signal. . The claim according to claim 8, wherein The column / roo information signal is an automatic redundancy circuit, characterized in that the external control signal such as RASB, CASB and the like.