KR20010003025A - method of confirming a frame synchronization, at that time correlation results being sampled is used - Google Patents

Abstract

PURPOSE: A method for confirming frame synchronization with sampled correlation is provided to perform correlation processing with the optimum pilot pattern having a length twice as long as a slot and to confirm frame synchronization after sampling the correlation at a specific delay point. CONSTITUTION: Plural pilot sequences having a length twice as long as a slot per radio frame are received through each physical channel on a communication link. The pilot sequences are correlated depending on each receiving position. The correlation results are outputted at a 2N delay point or the other delay points except the particular one wherein the N is 0, 1, 2 and so on. Each correlation result shows the maximum value at the particular delay point while having a side lobe value which includes the opposite polarity of the maximum value at the other delay points except the particular one. The correlation results are compared with predetermined critical values respectively. The compared values are sampled depending on output timing to confirm synchronization of the radio frame therefrom.

Description

Method of confirming a frame synchronization, at that time correlation results being sampled is used}

The present invention relates to a next generation mobile communication system. In particular, the pilot pattern having a length twice the number of slots is used when using a code sequence whose length is not even in an uplink or a downlink of a next-generation mobile communication system using the W-CDMA scheme. It relates to a method of checking frame synchronization using.

Recently, ARIB in Japan, ETSI in Europe, T1 in the US, TTA in Korea, and TTC in Japan are the core networks of existing mobile communication globalization systems (GSMs) that provide multimedia services such as voice, video and data. The next generation of mobile communication system based on wireless access technology was envisioned.

In order to present technical specifications for the next generation evolved mobile communication system, they agreed to joint research, and the project for this was called Third Generation Partnership Project (hereinafter abbreviated as 3GPP).

3GPP includes three major technical research areas.

The first is the 3GPP system and service sector, which is a study of the structure and service capabilities of the system based on the 3GPP specification.

Second, it is a research area for Universal Terrestrial Radio Access Network (UTRAN), where the Universal Terrestrial Radio Access Network (UTRAN) is based on W-CDMA according to Frequency Division Duplex (FDD) mode. Radio Access Network (RAN) using TD-CDMA according to Time Division Duplex (TDD) mode.

Third, it is a research section for core network that has evolved from the second generation mobile communication globalization system (GSM) and has third generation networking capability such as mobility management and global roaming.

In the above-described technical research divisions of 3GPP, a research section for a global radio access network (UTRAN) describes definitions and descriptions of a transport channel and a physical channel.

The uplink or downlink physical channels described in 3GPP generally consist of three hierarchical structures: superframes, radio frames, and timeslots.

The 3GPP radio access network (RAN) standard defines a superframe in a maximum frame unit having a 720 ms period, and in terms of the number of system frames, one superframe consists of 72 radio frames. In addition, a radio frame is composed of 16 time slots, and each time slot is defined as fields having corresponding information bits according to a physical channel.

In particular, the uplink or downlink physical channel, which is currently discussed in 3GPP, is based on a chip rate of 4.096 Mcps. This means using a 16 slot long pilot pattern for frame synchronization.

This is considered only for the case where the slot length is ^2N . However, in 3GPP, there is a movement to use a chip rate of 3.84 Mcps in an uplink or downlink physical channel. If the chip rate is changed from 4.096 Mcps to 3.84 Mcps, a radio frame consists of only 15 slots. If the pilot pattern of length is applied as it is, it is difficult to obtain an optimal effect.

Accordingly, Korean Patent Application No. 99-0133 discloses a pilot pattern of 15 slots in length, and also proposes a method of using a 15-slot pilot pattern for frame synchronization for a physical channel in an uplink or a downlink.

In the proposed scheme for frame synchronization, a correlation threshold (± V _T ) is set so that when the correlation result is above or below this threshold, it is regarded as a frame synchronization detection time.

For example, when double check is possible during frame synchronization, a maximum correlation result of different polarities is obtained when the delay is '0' and when the delay is in the middle of one period. In the sidelobe, which is the time point, the least correlation result is obtained. If no noise occurs at this time, the correlation threshold is a value between the maximum correlation result value and the minimum correlation result value.

However, if noise is inserted so that the minimum correlation result in the side lobe exceeds the correlation threshold, the point in time is also regarded as the frame synchronization detection point.

In this way, frame synchronization may be detected at a time point that is not required by the noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame synchronization checking method using a sampled correlation result suitable for reducing a frame synchronization false detection probability.

It is still another object of the present invention to perform correlation processing using an optimal pilot pattern having a length twice as large as a slot when using a chip rate of 3.84 Mcps in the uplink and downlink of a mobile communication system. The present invention provides a method of checking frame synchronization after sampling at a predetermined delay time.

A first feature of the frame synchronization confirmation method using the sampled correlation result according to the present invention for achieving the above object is that each physical on the communication link is a pilot sequence that is a multiple of the length of the slot length per radio frame according to an arbitrary chip rate Receiving through the channel, correlated according to the reception position of the multiple times length pilot sequence, and using the output sampled for each delay time of each of the processed correlation results, to confirm the synchronization for the radio frame. .

Preferably, each result of the correlation process output by the sampling is summed by the same delay time as the case may be, the result of each sum is compared with each preset threshold, and the comparison result is compared with respect to the radio frame. Used to confirm synchronization.

In addition, the sampled correlation results are compared with each preset threshold, and the synchronization with respect to the radio frame is confirmed from the comparison result.

According to a second aspect of the present invention for achieving the above object, a pilot sequence, which is twice the slot length per radio frame according to an arbitrary chip rate, is received through each physical channel on a communication link, and the double length pilot Correlate the sequence according to each reception position, and output each result of the performed correlation processing at 2N (N = 0,1,2,3 ....) delay time or delay time except this, respectively, and output the Each correlation result is compared with each preset threshold, and the comparison result is sampled according to the output timing, and the synchronization with respect to the radio frame is confirmed from the sampled comparison result.

Preferably, each result of the correlation process output by the sampling optionally sums correlation results at the 2N (N = 0,1,2,3 ....) delay points, and 2N (N = 0,1,2,3. Used for

In addition, each sampling output used for the radio frame synchronization check indicates a maximum value at a specific delay time of the correlation period, and represents a side lobe value different from the maximum value at a time except for the specific delay time.

A feature of the frame synchronization checking apparatus using the sampled correlation result according to the present invention for achieving the above object is that each physical channel on the communication link is a pilot sequence of a multiple times the slot length per radio frame according to an arbitrary chip rate. One or more matching filters received through the terminal and performing correlation processing according to a predetermined tap coefficient, a sampling unit for sampling each correlation result by the matching filter for each delay time point, and each sampling by the sampling unit And a sampling comparison unit for comparing the output with a predetermined threshold, and using the output of the sampling comparison unit to confirm synchronization with the radio frame.

Here, the matched filter uses tap coefficients of the same length as the pilot sequence that is a multiple of the slot length.

1 is a view showing a device configuration and a correlation result for explaining a method of confirming frame synchronization using a pilot pattern twice as long as a slot according to the present invention.

2 is a diagram illustrating a device configuration and a correlation result for explaining a method of confirming frame synchronization using a sampled correlation result according to a first embodiment of the present invention.

3 is a diagram illustrating a device configuration and a correlation result for explaining a method of confirming frame synchronization using a sampled correlation result according to a second embodiment of the present invention;

4 is a diagram illustrating an apparatus for explaining a method of confirming frame synchronization using a sampled correlation result according to a third exemplary embodiment of the present invention.

5 is a diagram illustrating an apparatus configuration and a correlation result for explaining a method of confirming frame synchronization using a sampled correlation result according to a fourth embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

60: first matched filter (Matched Filter1) 61: second matched filter

62: first threshold comparison unit 63: second threshold comparison unit

Hereinafter, a preferred embodiment of a frame synchronization checking method using a sampled correlation result according to the present invention will be described with reference to the accompanying drawings.

In the present invention, an optimal pilot pattern for frame synchronization is used when a chip rate of 3.84 Mcps is used instead of a chip rate of 1696 slots (16 slot length) in an uplink or downlink physical channel.

In particular, in the present invention, at a chip rate of 3.84 Mcps, the 15 slot length pilot pattern shown in Table 1 is not used as is for correlation processing for frame synchronization, and the double length (30 slot length) of the slot shown in Table 2 is used. The pilot pattern having is used for correlation processing for frame synchronization.

That is, when a sequence length used for correlation processing for frame synchronization is N, a sequence having a slot length defined as N` = `4l` + 2 is used. In the present invention, a physical channel of uplink or downlink is used. In order to use frame rate of 3.84Mcps instead of 4.096Mcps (16 slot length), we use 30 slot length (when l` = `7), which is twice the length of 15 slots.

The 30 slot long sequence used in the present invention has an autocorrelation characteristic as shown in Equation 1 below.

For this reason, the present invention uses the sampling result by delay time to improve the probability of false detection for accurate frame synchronization.

Vertical sequence (15 slots long) C1 = (a1, a3, a5, ……, a29) = (1 0 0 0 1 1 1 1 0 1 0 1 1 0 0) C2 = (a2, a4, a6, ……, a30) = (1 0 1 0 0 1 1 0 1 1 1 0 0 0 0) C3 = (b1, b3, b5, ……, b29) = (1 1 0 0 0 1 0 0 1 1 0 1 0 1 1) C4 = (b2, b4, b6, ……, b30) = (0 0 1 0 1 0 0 0 0 1 1 1 0 1 1) C5 = (c1, c3, c5, ……, c29) = (1 1 1 0 1 0 1 1 0 0 1 0 0 0 1) C6 = (c2, c4, c6, ……, c30) = (1 1 0 1 1 1 0 0 0 0 1 0 1 1 1) C7 = (d1, d3, d5, ……, d29) = (1 0 0 1 1 0 1 0 1 1 1 1 0 0 0) C8 = (d2, d4, d6, ……, d30) = (0 0 0 0 1 1 1 0 1 1 0 0 1 0 1)

30 slot length sequence A = (a1, a2, a3, ..., a30) = (110001001011111001110110100000) B = (b1, b2, b3, ..., b30) = (110001001101011001010000111011) C = (c1, c2, c3, ..., c30) = (111010110010001110111000010111) D = (d1, d2, d3, ..., d30) = (100110101111000000011101100101)

Table 3 shows the results of autocorrelation of the double length sequence (A, B, C, D) generated from each column sequence (C1, C2, C3, C4, C5, C6, C7, C8) of Table 1 described above. R (τ) is shown. The sequences A, B, C, and D all show the same correlation result by the autocorrelation characteristics as in Equation 1.

τ 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 R (τ) 30 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 τ 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 R (τ) -30 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2

As can be seen from Table 3, when the correlation processing is performed using a pilot pattern of 30 slots in length, the maximum correlation value 30 having the same polarity and the same magnitude is different at the time points 'τ = 0' and 'τ = 15'. Or -30, and in sidelobe (Sidelobe) you get a correlation of 2 or -2.

In this case, the correlation threshold (± V _T ) is used to increase the efficiency of frame synchronization detection. That is, it is regarded as a detection time point for frame synchronization only when the autocorrelation result of the 30 slot length sequence is above or below the correlation threshold.

Table 4 and Table 5 below show an example of a 30-slot pilot pattern according to the present invention. When the number of pilot bits constituting one slot is 5 bits or 6 bits, an uplink dedicated physical control channel (DPCCH) The pilot pattern is shown.

In this case, the sequence A and the sequence B shown in Table 2 are shown, and the sequence C and the sequence D can also be used.

Table 6 and Table 7 below show the remaining pilot patterns of the uplink dedicated physical control channel (DPCCH), and show the pilot bit patterns for the case where the number of pilot bits constituting one slot is 7 bits or 8 bits.

In this case, the case where sequence A and sequence B are used in Table 2 is also shown, and sequence C and sequence D can also be used.

In the above Tables 6 and 7, four parallel sequences having a length of 15 slots are called C1, C2, C3, and C4 when the pilot bits are 5 bits, 6 bits, 7 bits, or 8 bits. Table 8 shows the arrangement according to the position of each pilot bit.

N _pilot Pilot bit position number (bit #) Vertical sequence (15 slots long) 5 0 C1 One C2 3 C3 4 C4 6 One C1 2 C2 4 C3 5 C4 7 One C1 2 C2 4 C3 5 C4 8 One C1 3 C2 5 C3 7 C4

In the present invention, correlation processing for frame synchronization is performed using four parallel sequences of 15 slot lengths allocated to each pilot bit, that is, a code sequence having a total length of 60.

In Table 5 and Table 7, the shaded portion of all pilot bits is used for correlation processing for frame synchronization, and the pilot bits of the other portions except this have a value of "1", and all of the pilot bits of "1" The vertical sequence having is used for channel estimation for coherent detection.

In other words, when the pilot bit of each slot is 5 bits, bit # 0 (C1), bit # 1 (C2), bit # 3 (C3), and bit # 4 (C4) are 6 bits, and the pilot bit of each slot is 6 bits. Or bit # 1 (C1), bit # 2 (C2), bit # 4 (C3), and bit # 5 (C4) if 7 bits, and bit # 1 if the pilot bit of each slot is 8 bits. (C1), bits # 3 (C2), bits # 5 (C3), and bits # 7 (C4) are used for correlation processing for frame synchronization. Therefore, the pilot bits used for frame synchronization in one slot are all four bits as pilot bits in each slot, and the total number of pilot bits used for synchronization of radio frames is "60".

The following shows another example of a 30-slot pilot pattern according to the present invention. Table 9 shows a pattern of pilot symbols included in a downlink dedicated physical channel (DPCH). This is divided according to different symbol rates of the downlink dedicated physical channel (DPCH).

In Table 9, a pilot symbol used for downlink frame synchronization is a shaded portion of all pilot symbols at each symbol rate. The pilot symbol of the other parts except this has a value of "1".

That is, for example, in the case where the symbol rate is 16, 32, 64, 128 Ksps (N _Pilot = 8), symbol # 1 and symbol # 3 are used for frame synchronization. Therefore, since four pilot symbols are used for frame synchronization per slot, a total of 60 pilot symbols (4 x 15) are used for frame synchronization.

When the following Table 10 is that classified according to different symbol rate, the pattern of the pilot symbols included in the downlink dedicated physical channel (DPCH), the symbol rate is 8ksps (N _Pilot = 4) the first pilot symbol (symbol # In 1), the column sequence mapped to the I-channel tributary is C1, and the column sequence mapped to the Q-channel tributary is C2.

In addition, when the symbol rate is 16,32,64,128ksps (N _Pilot = 8), the column sequence mapped to the I-channel feeder in the first pilot symbol (symbol # 1) is C1, and the column sequence mapped to the Q-channel feeder is C2. In the third pilot symbol (symbol # 3), the column sequence mapped to the I-channel tributary is C3, and the column sequence mapped to the Q-channel tributary is C4.

Finally, when the symbol rate is 256,512,1024ksps (N _Pilot = 16), each I channel of the first, third, fifth, and seventh pilot symbols (symbol # 1, symbol # 3, symbol # 5, symbol # 7) The column sequence mapped to the branch or each Q-channel branch is C1, C2, C3, C4, C5, C6, C7, C8 in order.

Symbol rate Pilot symbol location number (symbol #) Channel feeder Column Sequence (15 Slots Length) 8ksps (N _Pilot = 4) One I C1 Q C2 16,32,64,128ksps (N _Pilot = 8) One I C1 Q C2 3 I C3 Q C4 256,512,1024ksps (N _Pilot = 16) One I C1 Q C2 3 I C3 Q C4 5 I C5 Q C6 7 I C7 Q C8

In addition, in order to describe the pilot symbol pattern of the downlink dedicated physical channel (DPCH), the transmit diversity of the downlink physical channel mentioned in the 3GPP radio access network (RAN) standard should be considered. Open loop transmit diversity and closed loop transmit diversity are applied on the downlink physical channel.

In this case, STTD based on spatial or temporal block coding is used for open loop transmit diversity.

The present invention also uses a 30 slot long downlink pilot pattern that takes this STTD into account.

STTD encoding principle according to the 3GPP Radio Access Network (RAN) standard is briefly described. After the symbol "S1, S2" is shifted, repaired, and converted by STTD encoding over each symbol interval, the symbol "-S2 ^* , S1 ^* " Is generated.

Table 11 below shows another pattern of pilot symbols included in the downlink dedicated physical channel (DPCH), and converts the pilot symbol patterns of Table 9 in consideration of STTD.

In Table 12, pilot symbol patterns considering STTD are classified according to different symbol rates, and the following serial sequences are obtained based on the vertical sequence defined in Table 11.

When the symbol rate is 8ksps (N _Pilot = 4), the column sequence mapped to the I-channel tributary in the first pilot symbol (symbol # 0) is -C1, which is 1's complement to C1, and the sequence sequence mapped to the Q-channel tributary is C2.

When the symbol rate is 16,32,64,128ksps (N _Pilot = 8), the column sequence mapped to the I-channel feeder in the first pilot symbol (symbol # 1) is equal to 1's complement to C3, the Q-channel feeder. The column sequence mapped is C4, the column sequence mapped to the I-channel tributary in the third pilot symbol (symbol # 3) is C1, and the column sequence mapped to the Q-channel tributary is -C2, which is 1's complement to C2.

Finally, when the symbol rate is 256,512,1024ksps (N _Pilot = 16), each I channel of the first, third, fifth, and seventh pilot symbols (symbol # 1, symbol # 3, symbol # 5, symbol # 7) The column sequence mapped to the branch or each Q-channel branch is in sequence -C3, C4, C1, -C2, -C7, C8, C5, -C6.

Symbol rate Pilot symbol location number (symbol #) Channel feeder Column Sequence (15 Slots Length) 8ksps (N _Pilot = 4) 0 I -C1 Q C2 16,32,64,128ksps (N _Pilot = 8) One I -C3 Q C4 3 I C1 Q -C2 256,512,1024ksps (N _Pilot = 16) One I -C3 Q C4 3 I C1 Q -C2 5 I -C7 Q C8 7 I C5 Q -C6

The principle of allocation and arrangement of pilot symbol patterns for a downlink physical channel in consideration of the STTD encoding shown in Table 11 is as follows.

STTD encoding is necessarily performed in groups of two symbols. For example, assuming that two symbols "S1 = A + jB" and "S2 = C + jD", STTD encoding is performed by binding S1 and S2. Where A and C are pilot bits of I channel feeder, and B and D are pilot bits of Q channel feeder.

STTD encoding of "S1 S2" at this time results in "-S2 ^* S1 ^* " (where * is a complex conjugate). In the end, the two symbols encoded STTD become "-S2 ^* = -C + jD" and "S1 ^* = A-jB".

Table 13 shows pilot symbol patterns for frame synchronization for the secondary common control physical channel (SCCPCH).

In Table 14, four column sequences of length 15 are divided according to different symbol rates, and the first pilot symbol (symbol #) when the symbol rate is 16,32,64,128ksps (N _Pilot = 8) is shown in Table 14. In 1), the column sequence mapped to the I-channel feeder is C1, and the column sequence mapped to the Q-channel feeder is C2, and the column sequence mapped to the I-channel feeder in the third pilot symbol (symbol # 3) is C3 and Q-channel feeder. The column sequence to be mapped is C4.

Also, when the symbol rate is 256,512,1024ksps (N _Pilot = 16), each I-channel feeder of the first, third, fifth, and seventh pilot symbols (symbol # 1, symbol # 3, symbol # 5, symbol # 7) Or a column sequence mapped to each Q-channel tributary is C1, C2, C3, C4, C5, C6, C7, C8 in order.

Symbol rate Pilot symbol location number (symbol #) Channel feeder Column Sequence (15 Slots Length) 16,32,64,128ksps (N _Pilot = 8) One I C1 Q C2 3 I C3 Q C4 256,512,1024ksps (N _Pilot = 16) One I C1 Q C2 3 I C3 Q C4 5 I C5 Q C6 7 I C7 Q C8

Table 15 below shows a pattern of pilot symbols for frame synchronization on a primary common control physical channel (PCCPCH).

In Table 16, four column sequences of length 15 are named C1, C2, C3, and C4 when they are mapped to the I-channel and Q-channel branches of each pilot symbol position number (symbol #). .

Pilot symbol location number (symbol #) Channel feeder Column Sequence One I C1 Q C2 3 I C3 Q C4

The 15-slot pilot pattern used in the uplink DPCH, downlink DPCH, and common control physical channel (CCPCH) described above can be used in the correlation processing for frame synchronization. Double length (30 slot length) is used.

In addition, one of the important characteristics of these pilot patterns is autocorrelation characteristics. That is, the results of autocorrelation of the pilot pattern used in the present invention are the same in all four cases.

First, when the original sequence is cyclically shifted,

Secondly, when we convert the original sequence in time and shift it again,

Thirdly, when the original sequence is conservatively transformed and cyclically shifted again,

Fourth, when the original sequence is transformed and repaired in time, and it is cyclically shifted again.

Next, the 15 slot length pilot pattern used for the uplink dedicated physical channel (Uplink DPCH), the downlink dedicated physical channel (Downlink DPCH), and the common control physical channel (CCPCH) is twice the slot length (30 slot length). The method to be applied to the frame synchronization check will be described.

1 is a view showing a device configuration and a correlation result for explaining a method of confirming frame synchronization using a pilot pattern twice the length of a slot according to the present invention. Table 17 also shows the results of autocorrelation at point A, the output of matched filter 10, when using the 30 slot length sequence shown in Table 2.

τ 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 slot# One One 2 2 3 3 4 4 5 5 6 6 7 7 8 Branch A 30 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 τ 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 0 slot# 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 One Branch A -30 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 -2 2 30

In FIG. 1B, the correlation threshold (± V _T ) has an absolute value smaller than the maximum correlation value '30' and the maximum correlation value '-30' of the other polarity, and the correlation result by the matching filter 10 is greater than or equal to the correlation threshold value. The following time is regarded as the frame synchronization detection time.

In this case, if noise of ± (V _T -2) or more occurs, frame synchronization false detection occurs. The probability of frame synchronization false detection is determined from the relationship between the correlation threshold and the side lobe correlation.

Table 18 shows the output of the threshold comparison unit 11 according to the delay variable τ in the device configuration of FIG. 1. In the present invention, the frame synchronization can be confirmed by observing the output of the threshold comparison unit 11.

Table 18 shows the result of comparing the output of the matched filter 10 with its own threshold value V _T specified in advance in the threshold comparison section 11, where the threshold value is greater than + V _T as 'H', and the threshold − V _T to '-H' the time or less, exhibited a time threshold is between ± V _T to 'L'.

τ 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 slot# One One 2 2 3 3 4 4 5 5 6 6 7 7 8 C branch H L L L L L L L L L L L L L L τ 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 0 slot# 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 One C branch -H L L L L L L L L L L L L L L H

In addition, by properly combining and summing the correlation results shown in Table 17 in the apparatus configuration of FIG. 1, optimum performance may be exhibited in confirming frame synchronization.

1 illustrates a basic apparatus configuration for confirming frame synchronization using a pilot pattern twice as long as a slot. Hereinafter, examples of using a sampled correlation result in frame synchronization confirmation will be described.

2 is a diagram illustrating an apparatus configuration and a correlation result for explaining a method of confirming frame synchronization using a sampled correlation result according to a first embodiment of the present invention.

In the apparatus configuration of FIG. 1, double check is possible for frame synchronization confirmation, but frame synchronization false detection occurs when noise of ± (V _T -2) or more occurs, resulting in poor performance of accurate frame synchronization detection.

Therefore, FIG. 2 is a device configuration for the purpose of further reducing the frame synchronization false detection probability.

In FIG. 2, the autocorrelation result at point A, which is the output of the matched filter 20, is the same as shown in Table 17. At the output of the matched filter 20, the delay variable including the time point at which the delay variable τ = 0 is Sample the correlation result when even (τ = 2k, k = 1,2,3,4, ...). (In some cases, the delay variable is odd (τ = 2k + 1, k = 0,1,2, 3, 4, ...) can be sampled correlation results.)

Table 19 shows the result of comparing the correlation result when the delay variable is an even number including τ = 0 and comparing it with the correlation threshold value V _T of the threshold comparison unit 21. That is, when the sampled correlation value is greater than or equal to the correlation threshold value V _T , it is represented as 'H', and when the correlation value is less than or equal to the correlation threshold value V _T , it is represented as 'L'.

τ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 slot# One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Correlation 30 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 C branch H L L L L L L L L L L L L L L

In the present invention, frame synchronization can be confirmed by observing the output of the threshold comparison section 21 shown in Table 19. FIG. In this case, using the device configuration of FIG. 2, as shown in FIG. 2B, a double check is not possible in frame synchronization check, but frame sync misdetection occurs only when (V _T + 2) or more noise occurs in the side lobe. Occurs. As a result, four false detection probability gains are obtained compared to the apparatus of FIG. 1.

3 is a diagram illustrating an apparatus configuration and a correlation result for explaining a method of confirming frame synchronization using a sampled correlation result according to a second embodiment of the present invention.

In FIG. 3, the autocorrelation result, which is the output of the matched filter 30, is the same as shown in Table 17. At the output of the matched filter 30, the delay variable including the time point at which the delay variable τ = 0 is an even number (τ = Sample the correlation result when 2k, k = 1,2,3,4,…, and the delay variable is odd (τ = 2k + 1, k = 0,1,2,3,4,…) Sampling results of correlation.

In FIG. 3, the result of comparing the correlation result when the delay variable is an even number including τ = 0 and comparing it with the correlation threshold value (+ V _T ) of the first threshold comparison unit 31 is the same as shown in Table 19. Sample the correlation result when the variable is odd (τ = 2k + 1, k = 0,1,2,3,4, ...) and compare it with the correlation threshold (-V _T ) of the second threshold comparison unit 32. One result is shown in Table 20. That is, when the correlation value sampled at the point B is less than or equal to the correlation threshold (-V _T ), it is represented as '-H', and when it is greater than or equal to the correlation threshold (-V _T ), it is represented as 'L'.

τ One 3 5 7 9 11 13 15 17 19 21 23 25 27 29 slot# One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Correlation 2 2 2 2 2 2 2 -30 2 2 2 2 2 2 2 C branch L L L L L L L -H L L L L L L L

In the present invention, the output of the first threshold comparator 31 or the second threshold comparator 32 is not observed without observing both the output of the first threshold comparator 31 and the output of the second threshold comparator 32. You can verify frame sync by observing only one of the outputs. In this case, the output of the matched filter 30 sampled to the point A in the device configuration of FIG. 3 is the same as that of FIG. 2B, and the output of the matched filter 30 sampled to the point B is shown in FIG. 3B.

After all, when the device shown in Fig. 3 is used for frame synchronization confirmation, as in the device configuration of Fig. 2, a double check is not possible in the frame synchronization confirmation, but noise of ± (V _T + 2) or more is detected in the side lobe. Frame synchronization false detection occurs only. This results in four false detection probability gains compared to the device of FIG.

FIG. 4 is a diagram illustrating an apparatus configuration and a correlation result for explaining a method of confirming frame synchronization using a sampled correlation result according to a third embodiment of the present invention.

In FIG. 4, all of the 30 slot length sequences (a and b = C1, C2, C3, and C4 of Table 5), which are twice the length of 15 slots, are used for frame synchronization checking. The outputs of 51 and 52 are sampled and used at the same timing as the sampling timing of the matched filter 40 and 50 outputs.

In Table 21 and Table 22, when the number of pilot bits constituting one slot in the pilot pattern of the uplink dedicated physical control channel (DPCCH) shown in Table 5 is 5 bits, each threshold comparison unit 41, 42 or 51, 52) The values of point E and point J sampled from the output are shown.

The correlation threshold + V _T set in the first threshold comparator 41 and the third threshold comparator 51 of FIG. 4 is the same, and the correlation threshold (-V _T ) having a different polarity and the same magnitude is the second. The threshold comparator 42 and the fourth threshold comparator 52 are set.

As shown in Table 21, when inputting a sequence of 30 slots length (a = C1 and C2 in Table 5), the time point at which 'H' is detected at point E is bit # 0 of slot # 1 and '-H' Is detected at bit # 1 of slot # 8.

In addition, as shown in Table 22, when inputting a sequence having a slot length of 30 (b = C3 and C4 in Table 5), the time at which 'H' is detected at point J is bit # 3 of slot # 1 and '- The time at which H 'is detected is bit # 4 of slot # 8.

After all, when the device shown in Fig. 4 is used for frame synchronization confirmation, a double check is impossible in the frame synchronization confirmation as in the device configuration of Fig. 1, but noise of ± (V _T + 2) or more in the side lobe Only when this occurs, frame synchronization false detection occurs. This results in four false detection probability gains compared to the device of FIG.

5 is a diagram illustrating an apparatus configuration and a correlation result for explaining a method of confirming frame synchronization using a sampled correlation result according to a fourth embodiment of the present invention.

In FIG. 5, the 30 slot length sequence (a and b = C1, C2, C3, and C4 in Table 5), which is twice the 15 slot length, is used for frame synchronization checking, and the threshold comparison units 62 and 63 are used. The output of is sampled at the same timing as the sampling timing of the matched filter (60, 61) output. However, in the device configuration of FIG. 5, the delay variable including the point at which the delay variable τ = 0 is output among the outputs of the first matched filter 60 and the second matched filter 61 is an even number (τ = 2k, k = 1,2, 3, 4, ...), the result of the correlation is sampled, and then the correlation values of the sampled points A and C are summed and transmitted to the first threshold comparison unit 62. Also, the correlation result when the delay variable is odd (τ = 2k + 1, k = 0,1,2,3,4, ...) among the outputs of the first matched filter 60 and the second matched filter 61. After sampling the sum of the correlation value of the sampled point B and D point it is delivered to the second threshold comparison unit (63).

Table 23 shows correlation values of points A, C and E of FIG. 5 when the number of pilot bits constituting one slot in the pilot pattern of the uplink dedicated physical control channel (DPCCH) shown in Table 5 above is 5 bits. And the output of the first threshold comparator 62 (point G) are shown in Table 24, and the correlation values of the points B, D, and F of FIG. 5 and the output of the second threshold comparator 63 (point H) are shown in FIG. ).

τ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 A, C branch 30 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 E branch 60 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 G branch H L L L L L L L L L L L L L L

τ One 3 5 7 9 11 13 15 17 19 21 23 25 27 29 B, D branch 2 2 2 2 2 2 2 -30 2 2 2 2 2 2 2 F point 4 4 4 4 4 4 4 -60 4 4 4 4 4 4 4 H branch L L L L L L L -H L L L L L L L

Table 25 below shows I point values obtained by sampling G point values and H point values of Tables 23 and 24.

A correlation threshold (+ V _T ) is set in the first threshold comparison unit 62 of FIG. 5, and a correlation threshold (-V _T ) having a different polarity and the same magnitude is set in the second threshold comparison unit 63. .

As shown in Table 25, when inputting a sequence of 30 slots in length (a = C1 and C2 in Table 5, or b = C3 and C4 in Table 5), the point where 'H' is detected at point I is slot # Bit # 0 or bit # 3 of 1 and '-H' is detected is bit # 1 or bit # 4 of slot # 8.

As shown in FIG. 5B, when the device shown in FIG. 5 is used for frame synchronization check, a double check is possible in the frame synchronization check as in the device configuration of FIG. 1, and ± (V) in the side lobe. _T + 4) error occurs only when frame synchronization false detection occurs. This is because the false detection probability gain of 8 compared with the device of Figure 1 is the best error detection probability.

1, 2, 3, 4, and 5, the matched filters 10, 20, 30, 40, and 50 use tap coefficients of the same length as the input sequence.

As described above, according to the frame synchronization checking method using the sampled correlation result according to the present invention, since the correlation processing result of the 30 slot length sequence is appropriately sampled or summed and used for frame synchronization check, the frame synchronization caused by noise is generated. The probability of false detection can be significantly improved.

In addition, when using a chip rate of 3.84 Mcps in the uplink and the downlink of the mobile communication system, correlation processing is performed using an optimal pilot pattern having a length twice the slot, and the correlation result according to a predetermined delay time point. Since sampling is used for frame synchronization confirmation, more accurate frame synchronization confirmation is possible.

Claims (3)

Receive on each physical channel on the communication link a pilot sequence of multiple times the slot length per radio frame according to an arbitrary chip rate, Correlate according to a reception position of the multiple times length pilot sequence, And checking the synchronization with respect to the radio frame by using the output of each processed correlation result for each delay time point. The wireless frame according to claim 1, wherein the results of the correlation processing output by the sampling are summed for each of the same delay points as occasion demands, the respective summation results are compared with each preset threshold, and the comparison result is compared with the radio frame. Frame synchronization confirmation method using a sampled correlation result, characterized in that for use in the synchronization confirmation. Receive on each physical channel on the communication link a pilot sequence that is twice the slot length per radio frame at an arbitrary chip rate, Correlating the double length pilot sequence according to each reception position, Output each result of the correlation processing performed at 2N (N = 0,1,2,3 ....) delay time or delay time except this, Each output correlation result is compared with each preset threshold value indicating a maximum value at a specific delay time point of the correlation period and representing a side lobe value different from the maximum value at a time except the specific delay time point, and comparing accordingly. Sample the result according to the output timing, And confirming synchronization with respect to the radio frame from the sampled comparison result.