KR0181133B1 - Frame sync. detection circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Frame synchronization detection circuit and method in a digital communication system.

2. The technical problem to be solved by the invention

In the frame sync detector, the longer the frame, the smaller the detection error. However, since the frame sync pattern is longer than the length of the frame to be transmitted, duplication increases and thus the transmission efficiency is reduced.

3. Summary of Solution to Invention

Provided are a method and an apparatus for increasing the detection probability without increasing the frame synchronization pattern by using an early-rate-functural pattern detector.

4. Important uses of the invention

Frame synchronization detection circuit in digital communication system.

Description

Frame Sync Detection Circuit and Method in Digital Communication System

1 is a block diagram of a conventional frame sync detector.

2 is a block diagram of a frame sync detector according to the present invention.

* Explanation of symbols for main parts of the drawings

101, 201: shift register 103, 205, 206, 207: adder

104, 105, 204, 205: latch 102, 202: XOR gate portion

106, 208, 209: Comparator 211: Andgate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital communication systems, and more particularly, to circuits and methods for finding and maintaining synchronization in a communication system transmitting frame by frame.

In general, when using a frame- or packet-based communication method, it is important to accurately find the start point of a frame or packet and maintain the synchronization state as well as the bit synchronization for clock recovery or data recovery. However, in recent years, data compression techniques and error correction techniques have become commonplace. Therefore, various methods have been used for accurate synchronization tracking and maintenance of the aforementioned frame or packet. One method is explained through the frame sync detector of FIG.

First, the structure of a conventional frame sync detector includes a shift register 101 for storing an input data sequence, a first latch 104 for storing a pattern to be detected, a second latch 105 for determining a pattern comparison result, And a comparator 106. The operation of the frame sync detector having the above structure receives the data pattern to be detected and the pattern discrimination value through the cpu interface circuit, and stores the data pattern stored in the shift register 101 at every input clock. The comparison is made using. The signal output determined by each of the XOR gate sections 102 performs a + operation on a signal that does not match the + operation for a signal matched by the adder 103. In this case, the calculated result is information on how much of the pattern n bits to be detected are matched. In addition, the signal output through the adder 103 is compared with the output of the latch 105 storing the minimum discrimination value in the comparator 106, which is a bit ni bits (where n is greater than or equal to i). It is determined whether or not the above conditions match, and the result of the frame synchronization detection signal is shown. However, the frame synchronization detector can reduce the detection error as the frame length is longer, but the frame synchronization pattern is longer than the length of the frame to be transmitted. Therefore, duplication increases and transmission efficiency is lowered.

Accordingly, an object of the present invention is to provide a circuit and a method for increasing the detection probability without increasing the frame sync pattern using an early-late-punctual pattern detector.

The frame synchronization detecting circuit of the present invention for achieving the above object comprises an output means for receiving serial data and outputting the parallel data, a latch unit for latching a reference pattern and a discrimination value, and inputting first bits which are part of the parallel data. A first logic part that searches for whether the first bits and the reference patterns are identical to each other by bit, and outputs the result, and adds the first logic part if the outputs of the first logic part are identical to each other; A first operation unit for outputting an operation result, a first comparison unit for comparing the output of the first operation unit with the discrimination value, and outputting the result, and receiving second bits one bit ahead of the first bits A second logic unit for searching whether the second bits and the reference patterns are the same for each bit and outputting a result; and outputting the second logic unit. A second operation unit which adds if they represent the same, otherwise subtracts and outputs the operation result, and a second output unit that compares the output value of the second operation unit with the value obtained by subtracting the discrimination value from the maximum correlation value and outputs the result. A second logic unit configured to receive a third bit after the first bit with respect to the first bit, search whether the third bit and the reference pattern are identical to each other by bit, and output the result; A third calculation unit which adds if the outputs of the third logic gate unit are equal to each other; otherwise, subtracts and outputs the operation result; and a value obtained by subtracting the discrimination value from the maximum correlation value with the output of the third operation unit. A third comparison unit for comparing and outputting the result, an output of the first operation unit is greater than the discrimination value, and an output of the second operation unit is at the maximum correlation value; Smaller than the value obtained by subtracting the value, the output from ryeogwa maximum correlation value of the third arithmetic unit characterized by comprising a fourth logic gate section for generating a frame synchronizing signal detection time is less than the value obtained by subtracting the determined value.

In order to achieve the above object, the frame synchronization detecting method of the present invention receives serial data and outputs the data as parallel data, and searches whether the first bits that are part of the parallel data are the same as the reference pattern for each bit, Outputting a first operation result that is added and otherwise subtracted; and searching whether the second bit is one bit ahead of the first bits by the bit, and if the same is the same as the reference pattern; Outputting a second operation result; searching for whether the first pattern is the same as the reference pattern bit by bit for the third bits after the first bit, adding the same, and auditing the third operation result And outputting the first operation result equal to or greater than the determination value, and the second operation result and the third operation result are determined from the maximum correlation value. Is less than the subtracted value, characterized in that it comprises the step of generating a frame synchronization detection signal.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

2 is a blur configuration diagram of a frame sync detector according to the present invention.

An n + 2 bit shift register 201 for storing input data every clock, a first latch 203 storing a reference pattern, an output of the n + 2 bit shift register 201, and Correlation values from three XOR gate portions 202 ₁ , 202 ₂ , and 202 ₃ for comparing the output patterns of the first latch 203 and the outputs of the XOR gate portions 202 ₁ , 202 ₂ , and 202 ₃ . Three comparators for comparing the outputs of the three adders 205, 206, and 207, and the outputs of the second latch 204, which store the outputs of the adders 205, 206, and 207, and the minimum discrimination values. 208, 209 and 210, and a three input end gate 211 for checking the condition of the outputs of the three comparators 208, 209 and 210 for early-rate-functural pattern discrimination.

Hereinafter, the block diagram of FIG. 2 attached to the present invention will be described in detail.

First, it is assumed that the length of the frame sync pattern to find the sync of the frame is n bits. In this case, the correlation characteristic of the code pattern used is a pattern having a maximum value only at the correct pattern detection position and having a correlation value of 0 for the same pattern that is preceded or followed by one bit interval. First, before the pattern detection starts, the latch 203 is assigned a reference pattern through the cpu interface circuit, and the latch 204 is assigned a minimum discrimination value. The two pieces of information are then maintained. Then, the pattern detection operation is performed after the initialization procedure as described above. The shift register 201 has an initial value of all zeros and one bit of data is input every clock. At this time, the shift register 201 is composed of all n + 2 bits to output the data string input in parallel every clock. The output Q ₀ ~Q _{N + 2} of Q ₀ ~Q _N of the shift register 201 are input to XOR gate portion _{(202 1), Q 1 ~Q} N + 1 is input to the XOR gate portion (202 ₂₎ and, Q ₂ ~Q _{N + 2} are input to the XOR gate portion (202 _3), the XOR gate portion (202 _1, 202 _2, 202 ₃₎ is the output of the shift register 201 receives each input bit by bit basis If the pattern is correct, 0 is output. When the outputs of the XOR gate portions 202 ₁ , 202 ₂ , and 202 ₃ are input to the adders 205, 206, and 207, respectively, the adders 205, 206, and 207 are 0 with respect to the input n-bit signal. In the case of 1, the result of performing the + operation is output. At this time, the outputs of the adders 205, 206, and 207 represent the correlation values of the input patterns computed by the early-rate-functively, respectively, which are the discriminated values stored in the latches 204 in the comparators 208 and 210. The result is compared with a value obtained by subtracting the maximum correlation value n, and the comparator 209 outputs a read result for the punctual pattern. The output of the comparators 208, 209 and 210 eventually outputs the frame synchronization detection signal by the three-input input gate 211 as to whether the pattern detection condition satisfies Equation 1 below. That is, the three input end gate 211 has a frame when the output of the comparator 209 is equal to or larger than the discrimination value, and the output of the comparators 209 and 210 is smaller than the subtracted discrimination value from the maximum correlation value n. Output the synchronous detection signal.

In the above-described circuit, when the alarm sound occurs, the probability (Equation 2a) and the probability of losing synchronization (Equation 2b) are shown in the following second equation.

As described above, the present invention provides an improved frame synchronization circuit and method for more accurate frame synchronization detection, thereby improving the probability of detecting a frame without lengthening the synchronization pattern by using the correlation characteristics of the frame synchronization pattern. There is an advantage.

Claims (3)

In a frame synchronization detecting circuit in a digital communication system, an output unit for receiving serial data and outputting the parallel data, a latch unit for latching a reference pattern and a discrimination value, and receiving first bits that are part of the parallel data A first logic gate unit for searching whether one bit and the reference patterns are identical to each other and outputting a result, and adds the first logic gate unit if the outputs of the first logic gate unit are identical to each other, and subtracts the result of the operation A first comparator to output the first comparator, a first comparator to compare the output of the first comparator with the discriminant value, and output a result thereof, a second bit one bit ahead of the first bits, and a second comparator A second logic unit for searching whether bits and the reference patterns are identical to each other and outputting a result thereof, and an output of the second logic unit A second operation unit which adds if it is equal to, and otherwise subtracts and outputs the operation result, and a second output unit that compares the output obtained by subtracting the determination value from the maximum correlation value with the output of the second operation unit and outputs the result. A third logic unit configured to receive a third bit after the first bit from the comparison unit, search whether the third bits and the reference patterns are identical to each other by bit, and output a result; If the outputs of the third logic gate portion are equal to each other, the third operation unit adds, otherwise subtracts and outputs the operation result, and the value obtained by subtracting the discrimination value from the maximum correlation value with the output of the third operation unit is compared. A third comparison unit for outputting the result and the output of the first operation unit is larger than the determination value, and the output of the second operation unit is the determination value at the maximum correlation value. In the digital communication system, characterized in that it comprises a fourth logic gate portion that generates a frame synchronization detection signal when the value is smaller than the value obtained by subtracting the value from the determined value from the maximum correlation value of the output of the third operation portion. Frame sync detection circuit. The second logic unit of claim 1, wherein the first logic gate unit is configured of a plurality of exclusive orifices respectively receiving the bits of the first bits and the bits of the reference pattern, and the second logic unit comprises a bit and a reference of the second bits. And a plurality of exclusive oragates each receiving a bit of a pattern, and the third logic gate portion is composed of a plurality of exclusive oragates respectively receiving a bit of a third bit and a bit of a reference pattern. Frame synchronization detection circuit in a digital communication system. In a frame synchronization detection method in a digital communication system, receiving serial data and outputting the same as parallel data; searching for whether the first bit, which is a part of the parallel data, is the same as a reference pattern; Outputting a first operation result, and searching whether the second bit precedes the first bit by the same bit as the reference pattern for each of the first bits, and if it is the same, adds and otherwise subtracts the second operation result. And searching whether the first bit is the same as the reference pattern for each of the third bits after the first bit, and outputting a third operation result that is added if not equal and otherwise subtracted. If the first operation result is equal to or larger than the discrimination value, and the second operation result and the third operation result are smaller than the subtracted value from the maximum correlation value Generating a frame synchronization detection signal.