KR20000073995A - function test apparatus of CES board - Google Patents

Abstract

PURPOSE: A device for testing circuit emulation service(CES) board functions is provided to transfer optional cells to a circuit corresponding to a testing cell, to transfer the cells into the device through a loop-back, and to compare the cells with an initially generated value, and to detect errors, so as to test the CES board functions. CONSTITUTION: When a status of circuit emulation service(CES) board functions is tested, a testing cell generating and comparing circuit(150) inputs arbitrary data on a payload part of an asynchronous transfer mode(ATM) cell and transfers the data to a line(110). Serial data transmitted to the line is mapped on a user data area of a frame. The transmitted data loops back the circuit to return to a CES board. A segmentation and re-assembly(SAR) & channel circuit(130) extracts user data from a frame and reassembles the extracted user data as ATM cells, to transmit the user data to a high-stream cell processor(120b). The high-stream cell processor converts a header of the cell to transmit the header to a cell bus interfacing circuit(140). A cell transferred to the cell bus interfacing circuit is delivered to a low-stream cell processor(120a). A cell transferred thereto is converted into the ATM cell through ATM cell combinations. If the ATM cell is looped back and transferred to the testing cell generating and comparing circuit, the testing cell generating and comparing circuit extracts another payload part of the cell and compares data forms of the payloads. If the data forms are not equal, the testing cell generating and comparing circuit regards the compared result as data losses, to notify a controlling circuit of a circuit interfacing failure.

Description

Function test apparatus of CES board

The present invention relates to a functional test apparatus of a CES board, and more particularly, to generate an arbitrary cell corresponding to a test cell and to send it to a line, and to enter the inside of the device through a loopback on a line, compared with a value generated first. The present invention relates to a functional test apparatus of a CES board, which enables the function of a CES board to be tested by detecting an error.

In general, the Circuit Emulation Service (hereinafter referred to as CES) is a constant bit rate (hereinafter referred to as CBR), that is, the circuit traffic and the Asynchronous Transfer Mode (ATM) network. As a service for an interface, more specifically, a function of performing an AAL (ATM adaptation layer) 1 function of converting an E1 / T1 / DS3 transport interface, which is a transport frame, into an ATM cell and an ATM cell into an E1 / T1 / DS3 interface. Say

Figure 1 is a road showing the configuration of a conventional CES board, the CES board is responsible for the interface of eight E1 / T1 subscribers and the AAL1 function for eight E1 / T1 frames. Parallel first-in first-out (FIFO) interface for sending and receiving user data. Consists of 16-bit parallel, matches the upper frame Mux Demux board assembly (FMDA) with a 56-byte cell bus, and communicates with the FMDA processor via the VME bus. .

As shown in FIG. 1, a conventional CES board includes a cell bus processor 10, a segmentation and reassembly (SAR) & channel unit 20, a synchronous chronological time stamp (SRTS) processor 30, and a controller 40. And a clock unit 50.

In the above-described configuration, the cell bus processing unit 10 FMDA receives information received from the down stream cell bus processing unit 10a and the SAR & channel unit 20 transmitted from FMDA, which is a functionally large processor. It consists of an upstream cell bus processing unit 10b for transmitting to. The downlink cell bus processing unit 10a converts a header conversion and a 16-bit cell bus into an 8-bit cell bus during downlink cell bus processing, and controls each signal necessary for storing data in the FIFO and transmitting data to the AAL1 SAR processor 20a. Used for The uplink cell bus processing unit 10b converts the header and 16-bit cell buses into 8-bit cell buses during the up-cell bus processing, stores data in the FIFO, reads the data, and controls each signal necessary for transmitting the cell bus to the FMDA. use.

The SAR & channel unit 20 includes an AAL1 SAR processor processing unit 20a and eight channel processing units 20b that are in charge of the E1 frame function. The AAL1 SAR processor 20a divides the data of the internal cell transmitted from the downlink cell bus processing unit 10a into channels and sends data and information of the corresponding channel to each corresponding channel. Each channel is responsible for delivering data and information to channel subscribers. Data and information of each channel subscriber is transmitted to the AAL1 SAR processor 20a in each corresponding channel. The AAL1 SAR processor 20a converts the received data and information into ATM internal cells (53 bytes) and transmits the data to the uplink cell bus processor 10b. The data of the AAL1 SAR processor 20a is shared with the processor through an SRAM (static RAM) 70 and a buffer 60.

The SRTS processor 30 functions to restore the clock. The SRTS function is provided because there is a need to synchronize the frequency between the other channel or the terminal linked with each channel of the CES board. The SRTS function utilizes the frequency provided in each channel or terminal, and recovers the frequency by inferring the originally required clock by adjusting the remaining time of the frequency.

The control unit 40 performs a function of generating an address decoder and a control signal of each device, communicating with an upper processor to a dual port RAM (DPRAM) using a VME bus, monitoring and controlling the state of the CES board, and CES Search each register on the board.

The clock unit 50 receives and generates a clock from the FCDA to perform cell bus matching with the outside in order to normally drive the AAL1 SAR processor 20a and the channel processing unit 20b.

As described above, when the self-test function of the conventional CES board is examined, there is a problem that the overall test function of the device is not supported because the function test related to the interface with the lower part of the SAR processor is not included.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and generates an arbitrary cell corresponding to a test cell, sends it to a line, and then enters the inside of the device through a loopback on a line to detect an error compared with the value originally generated. The purpose is to provide a functional test device for the CES board to test the function of the CES board.

1 is a view showing the configuration of a conventional CES board.

2 is a diagram showing the configuration of a functional test apparatus for a CES board of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

10, 120. Cell bus processing section 10a, 120a. Down-cell bus processor,

10b, 120b. Up-cell bus processor,

20, 130.Segmentation and Reassembly & Channel Division,

20a. AAL1 SAR processor, 20b. Channel processing unit,

30. Synchronous Residual Time Stamp (SRTS) processing unit,

40. control unit, 50. clock unit,

60.Buffer, 70. Static RAM (SRAM),

80.Dual port RAM (DPRAM), 110. circuit,

140. Cell bus interface unit 150. Test cell generation and comparison

The functional test apparatus of the CES board of the present invention for achieving the above object transfers the data of the cell received from the upper processor for each channel, SAR and channel unit for transmitting the channel data and information received from the line to the upper processor Wow; A cell bus interface unit providing protocol matching between the CES board and the upper processor; A functional test apparatus of a CES board comprising an up / down cell bus processing unit for performing ATM cell transmission / reception processing between the cell bus interface unit and the SAR and channel units, comprising: a test cell for performing an interface related function test with a circuit; And a test cell generation and comparison unit for checking an interface state with the line based on the test cell generated and looped back on the line. Further, the test cell generation and comparison unit fills and delivers any promise-type data to the payload portion of the ATM cell delivered from the cell bus processor to the SAR & channel unit, and pays back the loopback on the circuit. Extract and compare the data format of the payload portion with the first form to check the interface state with the line.

Hereinafter, with reference to the accompanying drawings will be described in detail a functional test apparatus of the CES board according to a preferred embodiment of the present invention.

2 is a diagram illustrating a configuration of a functional test apparatus of a CES board of the present invention. As shown in FIG. 2, the functional test apparatus of the CES board of the present invention includes a circuit 110, a cell bus processing unit 120, a SAR & channel unit 130, a cell bus interface unit 140, and a test cell generation and Comparing unit 150 is provided.

In the above-described configuration, the cell bus processing unit 120 transmits the cell bus received from the upper processor through the cell bus interface unit 140 to the SAR & channel unit 130. 120a and an upstream cell bus processor 120b for transmitting information received from the circuit 110 through the SAR & channel unit 130 to an upper processor. Here, the downlink cell bus processor 120a converts the header conversion and the 16-bit cell bus into an 8-bit cell bus to store data in the FIFO, and transmits the cell bus to the SAR & channel unit 130 during downlink cell bus processing. The uplink cell bus processor 120b converts the header conversion and the 16-bit cell bus into an 8-bit cell bus to store the data in the FIFO, reads the data, and transmits the data to the upper processor.

The SAR & channel unit 130 divides the data of the internal cell transmitted from the downlink cell bus processor 120a by channels to send data and information of the corresponding channel to each corresponding channel, and each channel transmits data and information to the channel subscribers. The data and information received from each channel subscriber through the circuit 110 is converted into an ATM internal cell (53 bytes) and transmitted to the uplink cell bus processor 120b.

The test cell generation and comparison unit 150 fills the data of arbitrary promise in the payload portion of the ATM cell to the SAR & channel unit 130 and sends it back on the circuit 110 when the cell is assembled. loopback) Extracts the payload of the on-cell and compares the data format in it with the data format generated when the test cell occurs.

The cell bus interface 140 provides protocol matching between the CES board and the upper processor.

Hereinafter, an operation process of the functional test apparatus of the CES board of the present invention will be described with reference to FIG. 2.

When testing the functional state of the CES board in the production of the CES board, the test cell generation and comparison unit 150 combines arbitrary data in the payload portion of the ATM cell, for example, 01, 02, 03,... , ff sequential values are written and sent to the SAR & channel unit 130, and the SAR & channel unit 130 sends the payload portion of the ATM cell to the circuit 110, and the serial data transmitted to the circuit 110. Maps to the user data area of the frame. Here, the service mode should be a function of providing a structured service.

As described above, the data transmitted to the circuit 110 returns to the CES board by looping back the circuit 110. In the SAR & channel unit 130, the user data portion in the frame returned by looping back the circuit 110 again. After extraction, the cell is reassembled into an ATM cell and transmitted to the uplink cell processor 120b, and the uplink cell processor 120b can process the cell received from the SAR & channel unit 130 by the cell bus interface 140. The header of the cell is converted and transmitted to the cell bus interface unit 140. The cell transmitted to the cell bus interface unit 140 is transferred to the downlink cell processor 120a, and the cell delivered to the downlink cell processor 120a is converted into an ATM cell through an ATM cell combination. As described above, When the ATM cell is looped back and enters the test cell generation and comparison unit 150, the test cell generation and comparison unit 150 extracts the payload unit of the cell to generate the first data format of the payload portion, that is, 01, 02, 03,... If both data formats are different from each other by comparing with ff, the controller is notified that an error has occurred in the interface with the line 110, considering data loss.

The functional test apparatus of the CES board of the present invention is not limited to the above-described embodiments, and can be variously modified and implemented within the range permitted by the technical idea of the present invention.

According to the functional test apparatus of the ces board of the present invention as described above, by generating an arbitrary cell corresponding to the test cell and sending it to the line, and then back to the inside of the device through the loopback on the line compared to the value generated first By detecting the error, the CES board has the effect of performing an interface-related functional test with the line.

Claims (2)

A SAR & channel unit for transmitting the data of the cell transmitted from the upper processor for each channel, and for transmitting the channel data and information received from the circuit to the upper processor; A cell bus interface unit providing protocol matching between the CES board and the upper processor; In the functional test apparatus of the CES board comprising an up / down cell bus processing unit for performing ATM cell transmission and reception between the cell bus interface unit and the SAR and channel unit, And a test cell generation and comparison unit for generating a test cell for performing an interface-related function test with the circuit and checking the interface state with the circuit based on the test cell which is looped back on the circuit. Functional test device of the board. The method of claim 1, wherein the test cell generation and comparison unit The cell bus processing unit fills and delivers the data of any promised form to the payload portion of the ATM cell delivered from the SAR & channel portion, extracts the payload of the ATM cell returned by loopback on the circuit and returns the data format of the payload portion. A functional test device for a CES board, which checks the state of an interface with the line by comparing the same with the first occurrence.