KR100369792B1 - Apparatus and method for processing cell of atm system - Google Patents

Abstract

The present invention relates to a cell processing apparatus and method of an asynchronous transmission mode system, and more particularly, to a cell processing apparatus and method of an asynchronous transmission mode system using AAL2. The present invention is connected to the E1 link, and has an asynchronous transmission mode cell multiplexing / demultiplexing unit, and receives the AEL 5 and the AEL 0 for transmitting the real-time packet and the AEL 5 for transmitting the inter-processor communication packet. In the asynchronous transmission mode system, a controller for analyzing the ADL 5 and updating a connection table for the ADL 2 to be input, and mutually converting the AEL 2 and the AEL 0 with reference to the updated connection table. When the ADL 5 is input to the digital signal processor and the controller, the controller switches to the controller. When the AEL 2 and the ARL 0 are input, the digital signal processor switches to the digital signal processor. A2 2 and A0 are input and A2 2 is E1. Black and switching the aal2 0 is characterized by the parts yirueojim Utopia switch for switching parts of the asynchronous transfer mode cell multiplexer / demultiplexer.

Description

Cell processing apparatus and method of asynchronous transmission mode system {APPARATUS AND METHOD FOR PROCESSING CELL OF ATM SYSTEM}

The present invention relates to a cell processing apparatus and method of an asynchronous transmission mode system, and more particularly, to a cell processing apparatus and method of an asynchronous transmission mode system using AAL2 (ATM Adaptation Layer 2).

In the IMT-2000 system, an Asynchronous Transfer Mode (ATM) method is preferable to the circuit switching method used in the cellular PCS. The ATM method enables the provision of high quality voice, video and video services, and Internet access. In general, however, mobile phone services require the transmission of data from a large number of subscribers within extremely limited bandwidth. Although ATM can provide high-speed, high-capacity bandwidth, efficient utilization of data within the limited bandwidth is necessary because the existing low-speed transmission facilities must be considered. In other words, the market principle that generational replacement of network equipment, which requires enormous investment costs, is almost impossible to realize, no matter how advanced the technology, requires a realistic implementation plan to improve performance and quality while maximizing existing equipment. .

In the prior art, AAL processing between E1 links between a base transmission system (BTS) and a base station controller (BSC) is performed in a batch of AAL5 including both a voice packet and an interprocessor cell (IPC). Treated with. This constrained the efficiency of E1 link data transmission and required investment for network facilities. In order to overcome this problem and efficiently use the existing network facilities, AAL2 packet has appeared and will be applied.

Specifically, when AAL5 is used for data that does not require real-time processing, information can be transmitted in all 48 bytes of payload of AAL5. However, when the AAL5 is used in the mobile communication system, since the mobile communication system mainly processes 5ms or 20ms of voice data requiring real time, the AAL5 is transmitted using only a part of the payload of the AAL5. If the 48-byte payload is transmitted, the quality of service will be degraded due to delay in cell assembly. In order to apply ATM system to mobile communication system, ITU-T adopts AAL2 and configured in the format described below to avoid waste of bandwidth.

FIG. 1 is a diagram showing the format of AAL2 applied to the present invention. Hereinafter, AAL2 will be described with reference to FIG.

The AAL2 packet generated in the base transmission system (BTS) is transmitted through an ATM connection, and the AAL2 packet may be transmitted through one ATM connection. The channel identifier used for the AAL2 packet (hereinafter referred to as "CID") is set and released through signaling between the base station controller (hereinafter referred to as "BSC") and the BTS. The AAL2 packet is standardized for short-length data transmission that is frequently generated, which is advantageous for voice data transmission.

FIG. 1A shows the format of a typical ATM cell, which is composed of a header of 5 bytes and a payload of 48 bytes.

FIG. 1B is a format of an AAL2 packet and includes a CID, a length indicator (hereinafter referred to as "LI"), and an user-to-user indicator (hereinafter referred to as "UUI") in the payload of FIG. 1A. Header error control (hereinafter referred to as "HEC") and AAL2 payload (CPS-Information) for user traffic.

The CID uses a value from 1 to 255 as an AAL2 packet identifier. CID = 0 is not used to avoid confusion with “all 0” used for unused payloads, and 2-7 are assigned for layer management peer-to-peer procedures. have. Therefore, CID for transmitting AAL2 user traffic can be used from 8 to 255. The CID value for the AAL2 user is set by AAL2 signaling when setting up the AAL2 channel.

LI represents the length of the AAL2 packet payload. The default value is 45 EH, which is maximum 64 bytes, but is defined as 45 bytes in CS-1 (Capability Set-1) to avoid implementation complexity.

UUI is used to transfer information between AAL2 users, that is, between Service Specific Convergence Sublayer (SSCS) entities or between AAL2 layer managers. Codes 0 through 31 are used, with 0 through 27 allocated for SSCS entities, 28 through 29 for future use, and 30 through 31 for hierarchy management.

HEC is used to protect AAL2 packet headers and a polynomial of X5 + X2 + 1 is used.

CPS-Information is a payload that carries actual information and is variable within a maximum of 45 bytes.

The AAL2 packet assembled in the above format is transmitted multiplexed in a CPS-PDU form to be described below. The smaller the size of AAL2, the more AAL2 packets are multiplexed into one ATM cell. The configuration of the CPS-PDU will be described with reference to FIG. 1C below.

First, an ATM cell to which an AAL2 packet is applied consists of 5 bytes of ATM cell header and 48 bytes of CPS-PDU. The CPS-PDU consists of a Start Field (hereinafter referred to as "STF") and 47 bytes of the CPS-PDU payload. The STF consists of an offset field (hereinafter referred to as "OSF") 6 bits, a sequence number (hereinafter referred to as "SN") 1 bit and parity (hereinafter referred to as "P"). The OSF indicates at what byte from the STF the AAL2 packet starts. If the size of the AAL2 packet exceeds 47 bytes and there is no starting point of the AAL2 packet in the CPS-PDU payload, it is indicated as 47.

SN is used to count CPS-PDU streams modulo-2. That is, 0 and 1 are repeatedly assigned to each CPS-PDU.

P is used to detect the occurrence of an error in STF Filed. The parity is odd parity.

The CPS-PDU payload is composed of information and fading, and the information is a portion into which an AAL2 packet is inserted, and fading may not be used depending on the length of the AAL2 packet. Therefore, the maximum length of the AAL2 packet is 47 bytes.

The voice is coded at a predetermined compression rate in the terminal according to the change of voice spurt and silence and transmitted to the AAL2 processor. The AAL2 processing unit adds 5 bytes of control information to each voice packet, assembles them into AAL2 packets by attaching 3 bytes of AAL2 packet headers, and then adds 1 byte of CPS-PDU header to generate a CPS-PDU. The CPS-PDUs thus generated are multiplexed with the other CPS-PDUs and transmitted to the ATM cell according to their size. The ATM cell generation process in the above-described AAL2 application is shown in FIG.

3 is a diagram illustrating a connection diagram between a BTS and a BSC applying a general ATM system. A description with reference to FIG. 3 is as follows.

Reference numerals 101 and 103 in the drawings denote a base station transmission system (BTS), and 105 denotes a base station controller (BSC) to which an ATM system is applied. The interface standard between the BTSs 101 and 103 and the BSC 105 supports the CEPT (E1) scheme. In the ATM system, the BTSs 101 and 103 convert the data received from the terminal into an ATM cell and transmit the data to the BSC 105 through the non-channelized E1 ATM interface. The ATM system 107 of the BSC 105 sorts the non-channelized and received data into ATM cells, converts the sorted ATM cells into AAL0 packets, and outputs them by outputting the ATM cell processing unit 109 and ACMA 111 (ATM Cell). Mux / Demux Board Assembly).

4 is a diagram illustrating a cell processor of a general ATM system. A description with reference to FIG. 4 is as follows.

The line interface 113 performs line interfacing with the asynchronous transmission system on the non-channelized data received in analog form from the BTSs 101 and 103 through the E1 link. That is, the line interface unit 113 converts the data input in the analog form into digital data and outputs the converted data. The framer 115 checks various CRC errors and frame errors for frame allocation and outputs them in the E1 format. In addition, the framer 115 receives a predetermined clock to find the start position of the cell, and the start of cell (SOC) ATM indicating the start of the cell and the data output from the line interface unit 113. Output to the interface unit 117. The ATM interface unit 117 receives the data of the E1 format, sorts them into ATM cells according to the SOC, and outputs the same. The switching unit 119 is a muxing / demuxing unit, and has a connection table. The switching unit 119 demuxes an ATM cell input from the ATM interface unit 117 or demuxes a cell input from an ACMA. In addition, the switching unit 119 outputs to the controller if the input cell is an InterProcessor Cell (IPC) cell. If the input IPC cell is transmitted to the controller 129 of FIG. 4, the IPC cell is input to the dual synchronous memory 121. The dual synchronous memory 121 has a transmission memory and a reception memory, and stores an IPC cell input to or output from the switching unit 119. The controller 129 is connected to the dual synchronous memory 121 through a utopia Tx / Rx bus, and is connected to the framer 115 through a flash ROM, a DRAM, an EPLD, and an address / data bus (not shown). The controller 129 reads an AAL5 packet from the dual synchronous memory 121, converts connection information such as VCI, and transmits it to the ACMA through the dual synchronous memory 121 and the switching unit 119. In addition, the controller 129 receives the IPC cell received from the ACMA through the switching unit 119 and the dual synchronous memory 121, converts the connection information such as the VCI, and then converts the dual synchronous memory 121 and the switching unit ( Output to the ATM interface unit 117 through 119. A MMC (Man Machine Interface) 131 is connected to the controller 129 and is in charge of an interface with a universal asynchronous receiver and transmitter (UART) or Ethernet.

The above configuration describes a conventional ATM system applying only AAL5. However, when AAL2 is applied to a voice packet requiring real time in a configuration such as a conventional ATM system, a controller in charge of AAL5 processing must process both AAL2 and AAL5. However, since the controller of the conventional ATM system, which was in charge of the conventional AAL5 processing, cannot process both AAL2 and AAL5, the quality of service is deteriorated if the existing ATM system is used. Therefore, a device that can handle both AAL2 and AAL5 is required in an ATM system.

Accordingly, an object of the present invention is to provide an asynchronous transmission mode cell processing apparatus and method for processing AAL2 in a digital signal processor using a digital signal processor (DSP) to process both AAL2 and AAL5.

In order to achieve the above object, the present invention is connected to the E1 link, and includes an asynchronous transmission mode cell multiplexing / demultiplexing unit, AEL 5 for transmitting inter-processor communication packets, and AEL for transmitting real-time voice information packets. In the asynchronous transmission mode system receiving 2 and 0, the controller for updating the connection table for the A2 to be input by analyzing the A5, and the A2 with reference to the updated connection table And a digital signal processor for mutually converting between and 0A, and switching to the controller when AEL 5 is input to the controller, and switching to the digital signal processor when AEL 2 and AEL 0 are input. Input AEL 2 and AEL 0 which are mutually converted by the digital signal processor. The A 2 is configured to switch to the E1 link, and the A 0 is a Utopia switch unit configured to switch to the asynchronous transmission mode cell multiplexing / demultiplexing unit.

In order to achieve the above object, the present invention provides a dual port memory having a connection table, a utopia switch unit, a controller and a digital signal processor, and transmits an ALS 5 and a real time packet for transmitting a communication packet between processors. In the cell processing method of the asynchronous transmission mode system for receiving the A to 2,

The Utopia switch unit receives the switching to the AI 5 and the AEL 2 and the AEL 0, the process of updating the connection table by receiving the AEL 5 switched by the controller in the utopia switch unit, and the digital When the signal processing processor inputs the 2A or 0A of the switching switch in the utopia switch unit, the process of mutually converting the 2A and 2A with reference to the updated connection table; It is characterized by consisting of the process of outputting the AEL 0 to the utopia switch unit.

Figure 1a is a diagram showing the configuration of a general AAL5 asynchronous transmission mode cell.

1B illustrates a typical AAL2 packet format.

Figure 1c is a diagram showing the configuration of a general AAL2 asynchronous transmission mode cell.

2 is a diagram illustrating a process of converting general voice packet data into an AAL2 asynchronous transmission mode cell.

3 is a diagram illustrating a configuration of a general base station transmission subsystem and a base station controller to which an asynchronous transmission mode system is applied.

4 is a diagram illustrating a configuration of a general asynchronous transmission mode system.

5 is a diagram illustrating a configuration of a cell processing apparatus of an asynchronous transmission mode system according to an embodiment of the present invention.

6 illustrates an interface structure between the digital signal processor and the FIFO of FIG. 5;

7 is a flowchart illustrating a cell switching method in a cell processing apparatus of an asynchronous transmission mode system according to an embodiment of the present invention.

8 is a flowchart illustrating a method for a digital signal processor to process AAL2 and AAL0 in a cell processing apparatus of an asynchronous transmission mode system according to an embodiment of the present invention.

9 is a flowchart of the AAL2 service routine of FIG.

10 is a flowchart of the AAL0 service routine of FIG.

11 is a flowchart illustrating a cell storing method by an interrupt in a cell processing apparatus of an asynchronous transfer mode system according to an exemplary embodiment of the present invention.

12 is a flowchart illustrating a cell transfer method by an interrupt in a cell processing apparatus of an asynchronous transfer mode system according to an exemplary embodiment of the present invention.

13 is a flowchart illustrating a cell storing method according to an exemplary embodiment of the present invention.

14 is a FIFO cell transfer timing diagram of a digital signal processor.

15 is an EPLD FIFO cell transmission timing diagram.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same reference numerals as much as possible even if they are displayed on different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

5 is a diagram illustrating an ATM cell processor according to an exemplary embodiment of the present invention. Hereinafter, a configuration and an operation according to the present invention will be described with reference to FIG. 5.

First, as shown in FIG. 5, the CEPT (E1) method, which is an interface standard between the BSC 105 and the BTSs 101 and 103, is supported. The transmission of data is in the Unchannelized E1 format. The framer 133 receives the non-channelized data, finds a cell start point of the received non-channelized data, generates and outputs the received data and the SOC. In addition, the framer 133 checks various CRC errors and frame errors for frame alignment. Data arranged in the E1 format in the framer 133 is input to the mapper 135. The mapper 135 receives the data arranged in the E1 format in 30 channels except for the synchronization channel TS0 and the signaling channel TS16, and maps the data of the E1 format received by the SOC to a 53-byte ATM cell. To print. The dual port memory 151 stores a connection table for configuring AAL5 and AAL2 of manganese, that is, a VCI, a virtual path identifier (VPI), and a CID table. The digital signal processor 139 receives an AAL2 packet and an AAL0 packet as inputs, and converts the AAL2 packet and the AAL0 packet into AAL0 if the input packet is AAL2 by referring to the connection table of the dual port memory 151, that is, the CID table. To print. The controller 149 receives an AAL5 packet, which is an IPC cell, as an input and performs a corresponding function. In addition, the controller 149 converts the VCI of the AAL5 packet, which is an IPC cell input thereto, by referring to the dual port memory 151 and then transmits the VCI to the ACMA 111.

The dual port memory 151 is a common memory shared by the controller 149 and the digital signal processor 139. The utopia switch unit 137 determines whether the input ATM cell is a voice packet or an IPC packet, and if the voice packet is a voice packet, outputs the switching to the digital signal processing unit 139, and outputs to the controller 149 when the IPC packet is an IPC packet or the controller. If it is not the IPC for 149, the IPC cell changes only the connection information such as VCI and transmits it to the ACMA for transmission to the controller. Whether the cell input from the mapper 135 is AAL5 or AAL2 can be determined by examining the virtual channel identifier (VCI) of the ATM cell header. In addition, the utopia switch unit 137 receives the AAL0 input from the controller 149 and the digital signal processor 139 and the AAL5 input from the controller 145 to be described later, and outputs it to the ACMA 111.

The digital signal processor 139 includes a digital signal processor 143 and a first-in first-out memory (hereinafter referred to as "FIFO": 141). The FIFO 141 buffers an AAL2 or AAL0 packet input from the utopia switch unit 137, buffers one cell, generates an interrupt, and outputs the interrupt to the digital signal processor 143. At this time, the digital signal processor 143 receives the interrupt and buffers the cell from the FIFO 141 to the memory 142. The buffered AAL2 cell is converted to AAL0, and the AAL0 cell is converted to AAL2 and then buffered back to the FIFO 141. In addition, the FIFO 141 buffers AAL0 or AAL2 input from the digital signal processor 143 and generates an interrupt when one cell is buffered and outputs the interrupt to the digital signal processor 143. The digital signal processor 143 receives the interrupt and outputs the buffered AAL0 packet to the utopia switch unit 137 in one cell or when a 1.25 msec interrupt is generated from the 1.25 msce interrupt generator. All cells including the cell are output to the utopia switch unit 137.

The controller 149 receives the AAL5 from the utopia switch unit 137 and buffers it in the memory 150. When the AAL5 cell is buffered, the controller 149 refers to the dual port memory 151 and converts the connection information such as the VCI and the VPI and outputs the converted information to the utopia switch unit 137.

The FIFO 141 consists of a receiving FIFO 155 and a transmitting FIFO 157. 6 is a diagram showing the detailed configuration of the digital signal processing unit 139 according to the reception FIFO 155 and the transmission FIFO 157. FIG. The configuration and operation of the FIFO 141 and the digital signal processor 143 according to the present invention will be described with reference to this.

The receiving FIFO 155 receives EPLD_WCLK, EPLD_WE, and SOC from the utopia switch unit 137 and buffers the ATM cell input from the utopia switch unit 137. A timing diagram for this is shown in FIG. 15. The reception FIFO 155 outputs an interrupt to the digital signal processor 143 through the HF terminal when one cell is full. The digital signal processor 143 then drives a direct memory access (DMA) to read the cell from the receiving FIFO 155 into the internal memory 142 in units of one cell. The digital signal processor 143 analyzes the header and the VCI of the cell stored in the internal memory 142 to analyze whether it is AAL2 or AAL0 data. At this time, the controller 149 preallocates the VCI and CID connection table through the dual port memory 151 before call setup. For this translation, the dual port memory 151 is configured as a dual port so that both the controller 149 and the digital signal processor 143 can use it. When the VCI and CID are set by the controller 149, the digital signal processor 143 cleans up AAL0 or AAL2 and buffers them in the transmission FIFO 157. A waveform diagram for this is shown in FIG. At this time, if the ATM cell is more than one cell to the transmission FIFO 157, and outputs to the utopia switch unit 137, or if a 1.25msec interrupt occurs, all cells buffered in the transmission FIFO 157 is output to the utopia switch unit.

7 is a flowchart illustrating a switching method of a utopia switch unit according to an exemplary embodiment of the present invention. FIG. 7A illustrates a switching method for transmitting an ATM cell input from a link or ATM cell mux / demux unit to the controller 149 and the digital signal processor 143. FIG. 7B illustrates a digital signal with the controller 149. FIG. A diagram illustrating a method for switching an ATM cell input from the processor 143 to a link or ATM cell mux / demux unit.

First, referring to FIG. 7A, the utopia switch unit 137 checks whether an ATM cell is input from the mapper 135 or the ATM cell mux / demux unit in step 601. When the ATM cell inputs in step 601, the utopia switch unit 137 proceeds to step 603 to check whether the ATM cell is AAL2 or AAL0 by checking the header of the received ATM cell. If the cell is AAL2 or AAL0, the utopia switch unit 137 switches the cell to the digital signal processor 143 through the FIFO 141 in step 607 and outputs the cell to the digital signal processor 143. However, if the input ATM cell is not AAL2 or AAL0, the utopia switch unit 137 proceeds to step 605 to check whether the ATM cell is AAL5. If the ATM cell is an AAL5 cell, the utopia switch unit 137 switches to the controller 609 in step 609 and outputs the cell to the controller 609.

7B, the utopia switch unit 137 checks whether an ATM cell is input from the digital signal processor 143 or the controller 149 in step 611. In this case, when the ATM cell is input from the digital signal processor 143 or the controller 149, the utopia switch unit 137 proceeds to step 613 to check whether the input ATM cell is an AAL2 cell. As a result of the check, if the input ATM cell is an AAL2 cell, the utopia switch unit 137 proceeds to step 617 and outputs by switching to the E1 link through the mapper 135 and the framer 133. However, if it is not the AAL2 cell, the utopia switch unit 143 proceeds to step 615 and checks whether it is AAL5 or AAL0. If the input ATM cell is AAL5 or AAL0, the utopia switch unit 137 switches and outputs the input cell to the ATM cell mux / demux unit of the ACMA 111 in step 619.

8 is a flowchart illustrating a method for the digital signal processor 143 to process AAL2 and AAL0 according to an embodiment of the present invention. A description with reference to FIG. 8 is as follows.

In operation 701, the digital signal processor 143 initializes the internal memory 142 and the FIFO 141 when the power is applied. The digital signal processor 143 checks whether a cell is input from the utopia switch unit 137 in step 703 after the initialization process. In this case, when the utopia switch unit 137 transmits the AAL2 or AAL0 ATM cell by the method of FIG. 7, the digital signal processor 143 analyzes the virtual channel identifier (VCI) of the ATM cell in step 705, and in step 707. Determines whether the cell is an AAL2 cell or an AAL0 cell from the analyzed information. If the input cell is an AAL2 cell, the digital signal processor 143 proceeds to step 709 to perform an AAL2 service routine, and if it is an AAL0 cell, proceeds to step 711 to execute and terminate the AAL0 service routine.

9 is a flowchart illustrating the AAL2 service routine of FIG. Hereinafter, the AAL2 service method will be described in detail with reference to FIG. 9.

The utopia switch unit 137 checks the virtual channel identifiers of the cells inputted, and provides the AAL0 and AAL2 cells to the digital signal processor 139. At this time, if the input cell is AAL2, the digital signal processor 143 of the digital signal processor 139 receives the AAL2 cell through the FIFO 141 and performs an AAL2 service routine.

In step 801, the digital signal processor 143 receives the SOC and the AAL2 cells from the utopia switch unit 137 through the reception FIFO 155 and stores them in the internal memory 142. When the SOC and the AAL2 cells are stored in the internal memory 142, the digital signal processor 143 performs synchronization by the SOC. The AAL2 synchronization is a synchronization with respect to a start point of an AAL2 cell.

When the AAL2 synchronization is performed, the digital signal processor 143 converts the AAL2 cell into an AAL0 cell by referring to the connection table of the dual port memory 151 in step 803. The converted cell is copied in units of bytes to the destination address of the internal memory 142 in step 805. The digital signal processor 143 checks whether the AAL2 has been converted to AAL0 while copying the converted cell to the destination address in step 807. When the conversion to AAL0 is completed, the digital signal processor 143 copies the AAL0 cell stored in the internal memory 142 to the transmission FIFO 157 in step 809.

10 is a flowchart illustrating the AAL0 service routine of FIG. Hereinafter, the AAL0 service method will be described with reference to FIG. 10.

First, the digital signal processor 143 receives AAL0 and SOC from the utopia switch unit 137 through the reception FIFO 155 and stores the AAL0 and SOC in the internal memory 142. When the AAL0 and the SOC are stored in the internal memory 142, the digital signal processor 143 performs AAL0 synchronization in step 901. The AAL0 synchronization is a synchronization with respect to a start point of an AAL2 cell, similarly to the AAL2 synchronization. When the AAL0 synchronization is performed in step 901, the digital signal processor 143 converts to AAL2 by referring to the connection table of the dual port memory 151 in step 903. The converted AAL2 is copied to the destination address of the internal memory 142 in units of bytes in step 905. The digital signal processor 143 checks whether the conversion of AAL0 is completed in step 907. When the conversion of AAL0 of AAL2 is completed, the digital signal processor 143 proceeds to step 909 to copy the AAL2 cell copied to the internal memory 142 to the transmission FIFO 157.

8 and 10, an operation for receiving a cell from the reception FIFO 155 and a method for outputting the cell to the transmission FIFO 157 will be described with reference to FIGS. 11 and 12.

11 is a flowchart illustrating a method for a digital signal processor to receive a cell from a receive FIFO according to an embodiment of the present invention. A description with reference to FIG. 11 is as follows.

First, the receiving FIFO 155 receives and buffers the AAL0 and AAL2 cells from the utopia switch unit 137, and generates and outputs an interrupt when all of the cells are buffered. This interrupt is hereinafter referred to as a first interrupt. In operation 921, the digital signal processor 143 checks that the first interrupt is generated from the reception FIFO 155. At this time, if the one-cell buffer is filled with AAL0 or AAL2 cells in the reception FIFO 155 and an interrupt occurs, the digital signal processor 143 receives the interrupt and stores the corresponding cell buffered in the reception FIFO 155 in the internal memory 142. Set the address to save. When the address is set, the digital signal processor 143 drives the DMA in step 925 to read the corresponding cell from the receiving FIFO 155 and copy it to the set address of the internal memory 142. When the cell is stored in the internal memory 142, the digital signal processor 143 increments the memory pointer and terminates in step 927.

12 illustrates a method of outputting cells which are converted to AAL0 or AAL2 in the digital signal processor and stored in the transmission FIFO 157.

Hereinafter, referring to FIG. 12, the digital signal processor 143 checks whether the second interrupt is input from the interrupt generator 144 in step 931. The interrupt generator generates an interrupt at a 1.25 msec period. When the second interrupt is input from the interrupt generator in step 931, the digital signal processor 143 is copied to the transmit FIFO 157 in step 933, so that all cells, whether the cell is full or unfilled, are switched to the utopia switch. Output to section 137. This is to prevent too much time delay since data applying the AAL2 packet is data requiring real time.

In addition, the present invention proposes a method for performing synchronization without generating SOC by setting a start address to store an input cell when the cell is stored in the FIFO 151. The method is illustrated in FIG. 13 and will now be described with reference to FIG.

FIG. 13 is a flowchart illustrating an addressing method when a cell is copied to an internal memory of the digital signal processor 143 according to an exemplary embodiment of the present invention. FIG. 14 is a timing diagram illustrating a cell transfer of a FIFO of the digital signal processor. 15 illustrates a cell transmission timing diagram associated with an EPLD FIFO.

The digital signal processor 143 checks whether there is an ATM cell to convert in step 941. This can be seen by checking whether the first interrupt is generated from the reception FIFO 155 and the digital signal processor 143 has copied the ATM cells of the cell unit from the reception FIFO 155 to the internal memory 142. At this time, if the ATM cell to be converted is copied to the internal memory 142 on a cell basis, the digital signal processor 143 performs the conversion. The ATM cell to be converted is copied to a predetermined address in step 943. For example, as shown in FIG. 14, when the conversion of the cell starts in the initial state, the digital signal processor 143 copies the converted ATM cell to the start address of 0x800 preset in the internal memory 142. During the conversion of the converted ATM cell, the digital signal processor 143 proceeds to step 945 to check whether the conversion of the next ATM cell starts. In this case, if the ATM cell to be converted into the internal memory is copied in units of cells, the digital signal processor proceeds to step 947 to perform the conversion, and copies the converted ATM cell to the next start address 0x7FF of the 0x800 address as shown in FIG. The ATM cell to be input is copied by designating the starting address as 0x7FE, 0x7FD .... Each start address may have a difference of 53 bytes, and may have a difference greater than the extra bits. Here, only the case where the digital signal processor 143 copies the ATM cell to the internal memory 142 is described. However, when the utopia switch unit 137 copies the ATM cell to the FIFO 151 or the digital signal processor 143 makes the FIFO. The same may be applied to the case of storing in 151. The SOC is automatically generated as shown in Fig. 15 by assigning the ATM cell converted as described above to a pre-assigned start address. That is, in the cell processing apparatus of the present invention, the SOC can be generated without a separate device for generating the SOC.

As described above, the present invention can maximize the band utilization of the E1 link by implementing AAL2 and control message AAL5 for the voice packet in order to effectively use the E1 link of the mobile communication system. There is an advantage of easy expansion.

Another advantage of the present invention is that AAL2 transmission efficiency and network equipment cost are reduced while processing high speeds requires processing power. The AAL5 processor-to-processor communication channel is configured to be processed by the controller, and the switching of the AAL2 voice packet is configured to be performed by a high-speed digital signal processor and thus can be processed in real time, thereby improving the performance of the system.

Claims (26)

An asynchronous transmission mode system connected to an E1 link and receiving AEL 5 for transmitting inter-processor communication packets and AEL 2 and AEL 0 for transmitting real-time packets and having an asynchronous transmission mode cell multiplexing / demultiplexing unit. In A controller for analyzing the ADL 5 and updating a connection table for the ADL2 to be input; A digital signal processor for mutually converting the AEL 2 and the AEL 0 with reference to the updated connection table; The switch is switched to the controller when the AEL 5 is input to the controller, and the ALA 2 is input from the E1 link or the AEL 0 is input from the asynchronous transmission mode cell multiplexer / demultiplexer. Switching to the digital signal processor and receiving the mutually converted AEL 2 and AEL 0, the AEL 2 switches to the E1 link, and the AEL 0 switches to the asynchronous transmission mode cell multiplexing / demultiplexing unit. A cell processing apparatus comprising a utopia switch unit. 2. The cell processing apparatus of claim 1, further comprising a dual port memory having the connection table and commonly connected to the controller and a digital signal processor. The method of claim 1, wherein the digital signal processing unit, A first-in, first-out memory for receiving and buffering the AEL 2 and the AEL 0; And a digital signal processor which reads the AEL 2 and the AEL 0 in the unit of cells from the first-in first-out memory, converts them to the first-in-first-out memory by mutually converting them by referring to the connection table. 4. The cell processing apparatus of claim 3, wherein the digital signal processor further comprises an internal memory for copying the AEL 2 and the AEL 0 read from or interconverted from the first-in, first-out memory. The method of claim 4, wherein the first-in, first-out memory, A first-in, first-out memory for buffering AEL 2 and AEL 0 inputted from the utopia switch unit; And a transmission first-in, first-out memory for buffering the converted AEL 2 and AEL 0 in the digital signal processor. The method of claim 5, wherein the first-in, first-out memory, And outputting a first interrupt to the digital signal processor when the AEL 2 or the AEL 0 is buffered in units of cells. 7. The cell processing apparatus of claim 6, wherein the digital signal processor receives the first interrupt, reads the cell, and stores the cell in the internal memory. The method of claim 5, wherein the first-in, first-out memory, And outputting to the utopia switch unit when the AEL 2 or the AEL 0 is buffered in units of cells. 6. The cell processing apparatus of claim 5, further comprising a second interrupt generator for generating a second interrupt at a predetermined time period and outputting the second interrupt to the digital signal processor. 10. The cell processing apparatus of claim 9, wherein the digital signal processor outputs the AEL 2 and the AEL 0 copied to the first-in, first-out memory to the utopia switch unit when the second interrupt is input. 11. The cell processing apparatus of claim 10, wherein the second interrupt is an interrupt occurring at a 1.25 msec period. 6. The cell processing apparatus of claim 5, wherein the utopia switch unit stores the AEL 2 or the AEL 0 in the first-in, first-out memory. 6. The cell processing apparatus of claim 5, wherein the digital signal processor stores the AEL 2 or the AEL 0 in the first-in, first-out memory. An asynchronous transmission mode having dual port memory having a connection table, a utopia switch unit, a controller and a digital signal processor, and receiving AEL 5 for transmitting inter-processor communication packets and AEL 2 for transmitting real-time packets. In the cell processing method of the system, The utopia switch unit is configured to switch between receiving the 5A, 5A, 2A and 0A, and Updating, by the controller, the connection table by receiving the AL 5 switched in the utopia switch unit; Receiving, by the digital signal processor, the AI 2 or the AI 0 switched by the utopia switch unit and mutually converting the AI 2 and the AI 0 with reference to the updated connection table; And outputting the converted AEL 2 or AEL 0 to a utopia switch unit. The method of claim 14, wherein the switching process, Switching a transmission asynchronous transmission mode cell for transmission to the controller or digital signal processor; Receiving switching for receiving at the controller or digital signal processor. The method of claim 15, wherein the transmission switching process, Determining a service type of an asynchronous transmission mode cell by examining a header of the received asynchronous transmission mode cell; And if the received asynchronous transmission mode cell is the ADL 5, switching to the controller, and if the AEL 2 or AEL 0, switching to a digital signal processor. The method of claim 15, wherein the receiving switching process, Determining a service type of an asynchronous transmission mode cell by examining a header of the received asynchronous transmission mode cell; And if the asynchronous transmission mode cell is an ADL, switching to an asynchronous transmission mode mux / demux section, an A2 switching to a link, and an ADL 0 switching to a mux / demux section. The method of claim 14, wherein the AEL 2 and AEL 0 interconversion process, Initializing memory at power-up, Checking whether the asynchronous transmission mode cell is input; When the asynchronous transmission mode cell is input, analyzing the virtual channel identifier of the cell and checking whether the A / L 2; If the input asynchronous transmission mode cell is AEL 2, executing an AEL 2 service routine; And if the input asynchronous transmission mode cell is AEL 0, executing the AEL 0 service routine. 19. The method of claim 18, wherein the A2 service routine execution process, Synchronizing the starting point of the ALA 2, Converting the AEL 2 into AEL 0 and copying it to internal memory; And converting the converted AEL 0 into a first-in, first-out memory when the AEL 0 of one cell is converted into the internal memory. 19. The method of claim 18, wherein the A 0 service routine execution process, Synchronizing the starting point of the AEL 0; Converting the A 0 to A 2 and copying it to internal memory; And converting the converted AEL 2 into a first-in, first-out memory when the AEL 2 of one cell is converted into the internal memory. 21. The method of claim 19 or 20, wherein the asynchronous transmission mode cell stored in the first-in, first-out memory further comprises receiving and outputting a second interrupt from the digital signal processor. 21. The method of claim 19 or 20, wherein the asynchronous transmission mode cell stored in the transmission first-in, first-out memory further comprises outputting when the length of one asynchronous transmission mode cell is filled. The method of claim 20, wherein the first-in, first-out copying process, Copying the converted asynchronous transfer mode cell to a start address of a predetermined first-in first-out memory when the predetermined asynchronous transfer mode cell is converted by the digital signal processor; Copying the asynchronous transmission mode cell to an address reduced by a predetermined area interval when the asynchronous transmission mode cell is input after the conversion is completed. 24. The method of claim 23, wherein the transmission is repeated until the first-in, first-out memory is initialized. 24. The method of claim 23, wherein the predetermined region interval is an interval capable of storing one asynchronous transmission mode length. 19. The method of claim 18, wherein the step of reading an asynchronous transmission mode cell from the received first-in, first-out memory, A step in which the reception first-in-first-out memory outputs a first interrupt to a digital signal processor when one asynchronous transmission mode cell is filled from the utopia switch; And receiving the first interrupt by the digital signal processor to read an asynchronous transfer mode cell of the corresponding memory.