KR100195068B1 - AAL1 Processing Unit at User-Network Interface of Broadband Telecommunication Networks - Google Patents

Abstract

The apparatus of the present invention relates to an AAL1 processing apparatus in the user-network interface of a broadband integrated information network. The apparatus of the present invention uses 47 A payload of payload of 47 bytes by using the AAL1 protocol. A transmitter 10 for generating a 53-byte ATM cell and transmitting it to the ATM link by attaching an ALL1 header of 5 bytes and an ATM cell header of 5 bytes after creating a Playload; Input ATM cell from ATM link to perform 5 byte ATM cell header processing, extract 1 byte of AAL 1 header using AAL1 protocol, generate DS1E bit stream from 47 bytes of payload and transmit to DS1E link Receiving unit 20, which matches user service information and ATM cell format at ATM User-Network Interface (UNI) according to AAL1 protocol proposed by International Organization for Standardization, handles transmission errors, lost or inserted cells This has the effect of performing processing of, error cell processing, and the like.

Description

An apparatus for proccessing a AAL1 in a BISDN UNI

The present invention relates to a user-network interface (UNI) of a broadband integrated telecommunication network (B-ISDN), and in particular, a user of a broadband integrated telecommunication network (BISDN) adapted to interface a DS1E class emulation of an equal bit rate to the broadband integrated telecommunication network. It relates to an AAL1 processing apparatus at a network interface.

With the rapid development of the information society, users' communication service demands have increased, and the Broadband Integrated Services Digital Network (hereinafter referred to as B-ISDN) has emerged as the next generation communication network. The ATM method, which is an asynchronous delivery mode, is the basic means of transport for accommodating a variety of services regardless of band and speed. Signaling AAL and Q.2931, B- Drafts such as ISUP and the like have been proposed.

That is, in the conventional ISDN (also referred to as narrowband (N) -ISDN), the transmission rate of a channel carrying user information was about 64 Kbps to 2 Mbps, so it was difficult to satisfy broadband services such as moving pictures.

On the other hand, B-ISDN can transmit data at high speed of 100 Mbps or more, and can process various information sources such as voice, data, document, and video by using ATM technology.

1 is a conceptual diagram illustrating an ATM protocol reference model, which is composed of a management plane, a control plane, and a user plane, and the management plane is further divided into plane management and hierarchy management.

Here, the plan management refers to the overall management of the system, and the hierarchical management refers to management of resource and use variables and operation and operation maintenance (OAM) information management.

In addition, the control plane manages call control and connection control information, and the user plane manages the transfer of user information.

Protocols of the control plane and user plane are divided into a higher layer, an ATM adaptation layer (AAL), an ATM layer, and a physical layer. The functions of each layer are shown in Table 1 below.

Function of each layer in the protocol reference model Hierarchy Tier function Upper hierarchy - Top-tier features ATM Adaptation Layer (AAL) Convergence (CS) Convergence function Cut and Rejoin (SAR) -Cutting function and recombination function ATM layer - -General flow control function-Cell header generation and extraction function-Cell virtual path identification number (VPI) / virtual channel identification number (VCI) translation-Cell multiplexing and demultiplexing function Physical layer Transmission Convergence (TC) -Cell rate separation function-Header error control (HEC) signal generation and confirmation function-Cell boundary identification function-Transmission frame generation and restoration function Physical medium (PM) -Bit time information function-Physical media related function

As shown in Table 1, the ATM scheme is divided into vertical structures, such as a physical layer, an ATM layer, an ATM adaptation layer (AAL), and a higher protocol layer, and the ATM adaptation layer is a partitioning and recombination sublayer (SAR). Segmentation And Reassembly sublayer) and Convergence Sublayer (CS) are divided into physical media (PM) and Transmission Convergence (TC) sublayers.

In addition, the ATM adaptation layer may be classified into AAL1, AAL2, AAL3, and AAL4 according to whether or not the bit rate is constant, real-time, or connectivity, and each of these types of functions is shown in Table 2 below.

Typical functions of AAL 1 to 5 Kinds function AAL 1 -Passing user data of equal bit rate at same bit rate-Passing time information between information source and destination-Error recovery and unrecovered error indication AAL 2 -Pass user data at variable bit rate-Pass time information between information source and destination-Error recovery and unrecovered error indication AAL 3/4 -Deliver user data at variable bit rates-Deliver in a connected or disconnected manner-Non-real time AAL 5 -Simplify AAL 3/4 functionality-High speed data transfer

As shown in Table 2 above, according to the AAL 1 protocol proposed by the International Organization for Standardization, AAL1 delivers services, such as delivering user data of equal bit rate at the same bit rate together with related time information, and indicating an unrecovered error to a higher layer. to provide.

In addition, AAL1 performs a function of dividing and reassembling user information, as well as providing a function of processing cell delay variation and processing lost or inserted cells. In addition, the clock information of the information source can be extracted at the receiving side, the user information section is monitored, and if a bit error occurs, correction processing is performed.

According to the AAL1 protocol proposed by the International Organization for Standardization, the present invention matches user service information with ATM cell format at an ATM user-network interface (UN) and handles transmission errors, loss or insertion of cells. It is an object of the present invention to provide an AAL1 processing apparatus in a user-network interface of a BISDN, which is configured to perform processing, processing of an error cell, and the like.

In the user-network interface of the broadband general information communication network according to the present invention for achieving the above object, the AAL1 processing apparatus, at the user-network interface of the broadband general information communication network, has an identity ratio of user data input from the DS1E link. A transmission unit for generating a payload of 47 bytes using the AAL1 protocol, attaching a 1-byte ALL1 header and a 5-byte ATM cell header, and generating a 53-byte ATM cell to transmit to the ATM link; Input ATM cell from ATM link to perform 5 byte ATM cell header processing, extract 1 byte of AAL 1 header using AAL1 protocol, generate DS1E bit stream from 47 bytes of payload and transmit to DS1E link Characterized in that it comprises a receiving unit.

That is, the apparatus of the present invention converts DS1E-class user data having a constant bit rate of 2.048 Kbps received from the subscriber side to the ATM cell and transmits it to the broadband integrated information network side, while the receiver receives the ATM transmitted from the broadband integrated information network side. The cell is converted into a general data stream and transmitted to the subscriber side.

1 is a conceptual diagram illustrating an ATM protocol reference model;

FIG. 2 is a block diagram showing an AAL1 processing apparatus in a user-network interface of a broadband general information network according to the present invention; FIG.

3 is a format diagram showing the structure of an ATM cell to which the present invention is applied.

* Names of symbols according to the main parts of the drawings

10: transmitter 20: receiver

11: CPU interface 12: cell header storage

13: output selector 14: serial / parallel converter

15: Transmission buffer 16: AAL1 header generation unit

17: multiplexer 18: transmission control unit

21: error detection unit 22: reception control unit

23: clock recovery unit 24: receiving buffer

25: bottle / serial converter 26: alarm signal generator

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating an AAL1 processing apparatus in a user-network interface of a broadband general information communication network according to the present invention.

The apparatus of the present invention is composed of a transmitter 10 and a receiver 20, as shown in FIG.

Here, the transmitting unit 10 includes a CPU interface 11 which is in charge of interfacing with an external CPU; A cell header storage unit 12 for storing an ATM cell header received from an external CPU through the CPU interface 12; An output selector 13 for selecting and outputting one of user data input from the DS1E link and test data input from the ATM link to realize local loopback; A serial / parallel converter 14 for converting serial data input from the output selector 13 into parallel data for internal processing; A transmission buffer 15 for buffering data input from the serial / parallel conversion unit 14; Synchronous Residual Time Stamp (SRTS) signal for transmitting the information of the service clock of the transmitting side to the receiving side, Sequence Number (SN) signal for checking cell loss or insertion, and presence of errors An AAL1 header generator 16 generating a cycle redundancy check (CRC) signal and a parity (P) signal to generate an AAL1 header of 1 byte; A multiplexer (17) for receiving an ATM cell header from the cell header storage unit (12), receiving data from the transmission buffer (15), and receiving an AAL1 header from the AAL1 header generator (16); And a transmission control unit 18 that controls the multiplexer 17 to control the ATM cell header of 5 bytes, the AAL1 header of 1 byte, and the payload of 47 bytes to be sequentially output to the ATM link.

In addition, the receiver 20 extracts a cyclic redundancy check (CRC) signal and a parity (P) signal from an ATM cell inputted from an ATM link, and determines whether an error has occurred in an ATM cell header and an AAL1 header. )Wow ; A clock generator 22 for extracting a synchronous residual time stamp (SRTS) signal from an ATM cell input from an ATM link and generating a clock based on a clock input from an external phase locked loop (PLL) element; A reception control section 23 which checks the sequence number SN of the ATM cell input from the ATM link to check cell loss and outputs a payload of 47 bytes; A reception buffer 24 for temporarily storing data input from the reception control unit 23; A parallel / serial conversion unit 25 for converting parallel data output from the reception buffer 24 into serial data and outputting the serial data through a DS1E link; And an alarm signal generator 26 for inspecting data output from the parallel / serial converter 25 and generating an alarm signal (AIS) when a series of data values is '1'.

Next, the operation and effects of the apparatus according to the present invention configured as described above will be described.

FIG. 3 is a format diagram showing the structure of an ATM cell, that is, a structure of an ATM cell. As shown in FIG. 1, a cell consists of 53 bytes.

The 53-byte ATM cell is divided into a 5-byte header, a 1-byte AAL1 header, and a 47-byte payload. First, the 5-byte header structure shows that the first byte is 4 It consists of a general flow control (GFC) of bits and a virtual path identifier (VPI) of 4 bits, and the second byte is a 4-bit virtual path identifier (VPI) and a 4-bit virtual channel identifier. (VCI: Virtual Channel Identifier), the third byte is composed of an 8-bit virtual channel identifier (VCI), and the fourth byte is a 4-bit virtual channel identifier (VCI) and a 3-bit effective load type identifier ( PTI: Payload Type Identifier) and 1-bit Cell Loss Priority (CLP), and the fifth byte is composed of 8-bit header error control (HEC).

In the AAL1 header, the eighth bit is a synchronous residual time stamp (SRTS) signal, the seventh, sixth, and fifth bits are a sequence number (SN) signal, and the fourth, third, and second bits are cyclic redundancy check (CRC). Signal, the first bit consists of a parity (P) signal.

In this case, the synchronous residual time stamp method is for transmitting the information of the service clock of the transmitting side to the receiving side, and the transmitting side transmits the synchronous residual time stamp (SRTS) signal to the receiving side in the AAL1 header.

In addition, the sequence number SN is a signal for checking cell loss or insertion, and the cyclic redundancy check (CRC) signal and the parity (P) signal are for detecting the presence or absence of an error.

With reference to Figures 2 and 3 to look at the operation of the embodiment according to the present invention divided into a transmitter 10 and a receiver 20.

First, referring to the operation of the transmitter 10, 2.048 Mbps of user data is input from the subscriber terminal to the output selector 13 through the DS1E link, and at the same time, the user data input to the output selector 13 is inputted. ATM header information is input from an external CPU through the CPU interface 11 and input into the cell header storage unit 12.

The serial data of 2.048 Mbps inputted to the output selector 13 is converted into parallel data by the serial / parallel converter 14 to be easily processed internally, then buffered by the transmission buffer 15, and then multiplexed by the multiplexer ( 17) is entered.

Meanwhile, an ATM cell header input to the cell header storage unit 12 is also input to the multiplexer 17.

In addition, the AAL1 header generator 16 receives a clock of 2.048 Mbps input to the synchronizer clock (usually 2.43 MHz) and the output selector 13, and receives a synchronous residual time stamp (SRTS) signal and a sequence. A number (SN) signal, a cyclic margin check (CRC) signal, and a parity (P) signal are generated to generate an AAL1 header of 1 byte, and then input to the multiplexer 17.

Accordingly, the transmission controller 18 controls the output of the signal input to the multiplexer 17. First, the 5-byte ATM cell header is output through the ATM link, and then 1-byte AAL1 header is output. Subsequently, by paying 47 bytes of payload, 53 bytes of ATM cells are generated and controlled to be output to the ATM link.

Meanwhile, referring to the operation of the receiver 20, the error detector 21 checks a cyclic redundancy check (CRC) signal and a parity (P) signal among 53-byte ATM cells inputted from the ATM link, and checks the ATM cell header and It is determined whether an error occurs in the AAL1 header.

The reception control unit 23 checks the sequence number SN in the received ATM cell to determine whether there is a lost or inserted cell.

In addition, the clock recovery unit 22 detects a synchronous residual time stamp (SRTS) signal in a received ATM cell, and controls an external phase locked loop (PLL) device to restore an output clock.

Meanwhile, the payload of 47 bytes output from the reception control unit 23 is buffered in the reception buffer 24, and then input to the parallel / serial conversion unit 25 to be converted into serial data.

By the restored clock, serial data output from the parallel / serial converter 25 is transmitted to the subscriber station through the DS1E link.

At this time, the alarm signal generator 26 checks the data output from the parallel / serial converter 25 and generates an alarm signal AIS when all data (usually 2048 bits) are '1'. .

In order to connect subscribers to the subscriber matching module, connection devices such as SAD3, SAE1, CAE1, and FRIA are required. In particular, these boards are mounted as one module in a distributed switching node of ATM-MSS, and thus, 2.048 Kbps / s It is connected to a user device with a transmission rate or an exchange that provides a dedicated line.

That is, the apparatus of the present invention converts the DS1E-class user data having a constant bit rate of 2.048 Kbps / s received from the subscriber station to the ATM cell to transmit to the broadband integrated information network side, while transmitting the ATM cell received from the network side to the general data stream Is converted to the subscriber and transmitted to the subscriber.

As described above, the device of the present invention matches user service information and ATM cell format at ATM user-network interface (UNI) according to the AAL1 protocol proposed by the International Organization for Standardization, and handles, loses, or inserts transmission errors. This has the effect of performing cell processing, error cell processing, and the like.

Claims (3)

At the user-network interface of the broadband integrated information network, one-byte ALL1 header and five-byte ATM cell are generated after 47% of payload is generated by using the AAL1 protocol with user data of the identity ratio input from the DS1E link. A transmitter 10 for attaching a header to generate an 53-byte ATM cell and transmit the same to an ATM link; Input ATM cell from ATM link to perform 5 byte ATM cell header processing, extract 1 byte of AAL 1 header using AAL1 protocol, generate DS1E bit stream from 47 bytes of payload and transmit to DS1E link AAL1 processing apparatus in the user-network interface of the broadband integrated information communication network, characterized in that it comprises a receiving unit (20). The transmission unit (10) according to claim 1, further comprising: a CPU interface (11) in charge of interfacing with an external CPU; A cell header storage unit 12 for storing an ATM cell header received from an external CPU through the CPU interface 12; An output selector 13 for selecting and outputting one of user data input from the DS1E link and test data input from the ATM link to realize local loopback; A serial / parallel converter 14 for converting serial data input from the output selector 13 into parallel data for internal processing; A transmission buffer 15 for buffering data input from the serial / parallel conversion unit 14; Synchronous Residual Time Stamp (SRTS) signal for transmitting the information of the service clock of the transmitting side to the receiving side, Sequence Number (SN) signal for detecting cell loss or insertion, and presence of errors An AAL1 header generator 16 generating a cycle redundancy check (CRC) signal and a parity (P) signal to generate an AAL1 header of 1 byte; A multiplexer (17) for receiving an ATM cell header from the cell header storage unit (12), receiving data from the transmission buffer (15), and receiving an AAL1 header from the AAL1 header generator (16); And a transmission control unit 18 that controls the multiplexer 17 to control the ATM cell header of 5 bytes, the AAL1 header of 1 byte, and the payload of 47 bytes to be sequentially output to the ATM link. The AAL1 processing apparatus in the user-network interface of the broadband integrated information network. 3. The receiver of claim 2, wherein the receiver 20 extracts a cyclic redundancy check (CRC) signal and a parity (P) signal from an ATM cell inputted from an ATM link to determine whether an error occurs in an ATM cell header and an AAL1 header. An error detection unit 21 for judging; A clock generator 22 for extracting a synchronous residual time stamp (SRTS) signal from an ATM cell input from an ATM link and generating a clock based on a clock input from an external phase locked loop (PLL) element; A reception control section 23 which checks the sequence number SN of the ATM cell input from the ATM link to check cell loss and outputs a payload of 47 bytes; A reception buffer 24 for temporarily storing data input from the reception control unit 23; A parallel / serial conversion unit 25 for converting parallel data output from the reception buffer 24 into serial data and outputting the serial data through a DS1E link; And an alarm signal generator 26 for inspecting data output from the parallel / serial converter 25 and generating an alarm signal (AIS) when a series of data values is '1'. AAL1 processing apparatus at the user-network interface of a broadband integrated information network.