KR20000066696A - Method of forming a bipolar transistor in a semiconductor device - Google Patents

Abstract

PURPOSE: A bipolar transistor forming method is provided to reduce a base narrow effect owing to a lightly doped n-well and a collector resistance owing to a triple n-well, by forming a collector region with an n-well and a triple n-well. CONSTITUTION: A bipolar transistor forming method comprises implanting impurities in a semiconductor substrate(10) by using a first photoresist pattern as a mask, so as to form a triple n-well(11) in the semiconductor substrate(10). Impurities are implanted in the semiconductor substrate(10) by using a second photoresistor pattern as a mask, so as to form n-wells(13A,13B) in the substrate(10) and at both sides of the triple n-well(11). A p-well(12) is formed in the semiconductor substrate(10) between the n-wells(13A,13B).

Description

Method of forming a bipolar transistor in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a bipolar transistor in a flash memory device capable of improving the characteristics of a bipolar transistor while applying a conventional CMOS process.

In general, a flash memory cell performs a program and erase operation using a high voltage, and a write operation is performed by an internal algorithm that verifies the cell. Is done. As described above, the bias voltage states during the program / erase operation are as follows.

Bias voltage state during program operation: Vpp = 10V, Vd = 5V, Vs = Vsub = 0V

Bias Voltage State During Erase Operation: Vee = -10V, Vs = 5V, Vd = Floating, Vsub = 0V

Bias voltage state during read operation: Vcg = 5V, Vd = 1V, Vs = Vsub = 0V

In order to implement such a bias voltage state, a separate self biasing circuit is required. In a recent CMOS process, a band gap reference circuit (B gap) is used to obtain a stable output at main power (Vcc) and temperature. band gap reference circuits) are widely used.

1 shows an example of a band gap reference circuit diagram in a CMOS device.

As shown in FIG. 1, a cascode current source, an NMOS feed-back circuit, and an output voltage feed back block constituted by a CMOS device are included. .

In this circuit, a stable self-bias voltage can be obtained by the voltage feed-back circuit in the output block, and if an appropriate k value (Boltzmann's constant) is found, the output voltage is approximately band gap energy. It will have a voltage of about.

FIG. 2 shows a cross-sectional view of an NPN bipolar transistor in a conventional CMOS device, wherein p wells 2 are formed in selected regions of n-type semiconductor substrate 1, and n + in selected regions of p wells 2; The emitter junction 4 is formed, and the n + collector junctions 3 and 5 are formed in the selected region of the adjacent semiconductor substrate 1 with the p well 2 interposed therebetween. An emitter electrode E is formed at the n + emitter junction 4, a base electrode B is formed at the p well 2, and a collector electrode (3) is formed at the n + collector junctions 3 and 5. C) is formed.

When the bipolar transistor is formed by a conventional process, the emitter junction 4, the p well 2 and the collector junction 3 and 5 have an emitter electrode E and a base electrode. B) and a collector electrode C are formed, respectively. The bipolar transistor thus formed has a collector junction (3 and 5) formed of an abrupt junction (abrupt junction) to achieve a high performance (base width: from one collector junction (3) to another collector junction ( 5) If the length of the gap is reduced, there is a possibility of a base narrowing effect in the operation of the bipolar transistor, which is operated by the surface channel and a high current is applied to the drain junction edge. Flows through and has the potential to cause junction damage by current crowing. Accordingly, in the conventional bipolar transistor formation process, since a peripheral circuit is formed of an n + junction or the like, difficulty in improving performance is generated by optimization of the CMOS transistor.

Accordingly, an object of the present invention is to implement a bipolar transistor of a self bias circuit in a flash memory in order to solve the above-mentioned problems. The present invention provides a method for forming a bipolar transistor of a semiconductor device capable of reducing a base narrowing effect by lightly doped n wells and reducing resistance of a collector electrode by a high concentration of triple n wells.

A bipolar transistor forming method of a semiconductor device of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a triple well on a semiconductor substrate; Forming n wells on semiconductor substrates on both sides of the triple well; Forming a p well on the triple well but in a semiconductor substrate between the n wells; And forming a collector junction in the n well and a base junction and an emitter junction in the p well, respectively.

1 is an example of a band gap reference circuit diagram in a CMOS device.

2 is a cross-sectional view of an NPN bipolar transistor in a conventional CMOS device.

3 is a cross-sectional view illustrating a bipolar transistor of a semiconductor device according to the present invention.

4 (a) to 4 (d) are cross-sectional views sequentially illustrating a bipolar transistor forming method according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a bipolar transistor according to another embodiment of the present invention.

<Description of Signs of Major Parts of Drawings>

1 and 10: semiconductor substrates 2, 12, 32A and 32B: p well

3, 5, 16A, 16B, 36A and 36B: collector junction

4, 14, and 34 emitter junction 11 triple n well

13A, 13B, 13C and 33: n wells 15A and 15B: base junction

21, 22, and 23: photoresist pattern

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a cross-sectional view illustrating a bipolar transistor of a semiconductor device according to the present invention.

The triple n well 11 is formed in the selected region of the semiconductor substrate 10, and the n wells 13A and 13B are formed in the semiconductor substrate 10 in the edge region above the triple n well 11. The p well 12 is formed on the triple n well 11 and is formed on the semiconductor substrate 10 between the n wells 13A and 13B. N + collector junctions 16A and 16B are formed in selected regions of the n wells 13A and 13B, p + base junctions 15A and 15B are formed in the selected regions of the p wells 12, and p An n + emitter junction 14 is formed in a selected region of the well 12. The emitter junction 14 is formed with an emitter electrode E, the base junctions 15A and 15B are connected to each other to form a base electrode B, and the collector junctions 16A and 16B are connected to each other. The collector electrode C is formed.

The bipolar transistor in the present invention operates as a vertical bipolar transistor, and emitter injection effects on electrons are formed because the emitter electrode formed by the rightly doped n + junction and the relatively low concentration p well are formed as the base electrode. Emitter injection efficiency can be increased. In addition, in the collector electrode consisting of n wells and triple n wells, the right narrow dopant n well is used as a high concentration minority carrier in base narrowing effect and high level injection. This results in base widening, which can relatively stabilize the bipolar transistor operation.

When implementing a bipolar transistor of a self-biased circuit in a flash memory device using the present invention, since the collector region is composed of n wells and triple n wells, the collector resistance can be reduced by the relatively right-doped n wells. As described above, the present invention uses the basic technology of the flash memory device as it is to form a peripheral bipolar transistor of the peripheral device, but unlike the conventional technology, the bulk junction during the negative erase operation and the channel erase operation of the cell. Triple n wells, which are used for device isolation, can be used to implement bipolar collector structures to facilitate transistor, cell, and bipolar optimization of peripheral devices. That is, when the bipolar transistor formation in the flash memory forming process is based on the present invention, it is possible to improve the early effect of the bipolar transistor and the kick's effect in the high current injection. A performance bipolar transistor can be realized.

4A to 4D are cross-sectional views sequentially illustrating a method of forming a bipolar transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, after forming the first photoresist on the semiconductor substrate 10, the selected region of the first photoresist is etched through a photolithography and an exposure process to form a first photoresist pattern ( 21). Phosphorous ions are implanted into the selected region of the semiconductor substrate 10 through an impurity ion implantation process using the first photoresist pattern 21.

Referring to FIG. 4B, after the triple n well 11 is formed in the semiconductor substrate 10 through the impurity ion implantation process, the first photoresist pattern 21 is removed. After forming the second photoresist on the semiconductor substrate 10, the selected region of the second photoresist is etched through the photolithography and exposure process to form the second photoresist pattern 22. Phosphorous ions are implanted into the selected region of the semiconductor substrate 10 through an impurity ion implantation process using the second photoresist pattern 22.

Referring to FIG. 4C, n wells 13A and 13B are formed on the semiconductor substrate 10 at both sides of the triple n well 11 through the impurity ion implantation process, and the semiconductor substrate 10 is formed. In another selected region of the n well 13C for forming the PMOS is formed. After removing the second photoresist pattern 22, a third photoresist is formed on the semiconductor substrate 10. The selected region of the third photoresist is etched through the photolithography and etching process to form the third photoresist pattern 23. Boron ions are implanted through an impurity ion implantation process using the third photoresist pattern 23.

Referring to FIG. 4 (d), the p well 12 is formed in the semiconductor substrate 10 between the n wells 13A and 13B on the triple n well 11 through the impurity ion implantation process. The third photoresist pattern 23 is removed.

3, an n + collector junction is formed in the selected region of the n wells 13A and 13B, a p + base junction is formed in the selected region of the p well 12, and the p well ( An n + emitter junction is formed in the selected region of 12). An emitter electrode E is formed at the emitter junction, the base junction is connected to each other to form a base electrode B, and the collector junction is connected to each other to form a collector electrode C.

5 is a cross-sectional view illustrating a bipolar transistor according to another embodiment of the present invention.

The n well 33 is formed in the selected region of the semiconductor substrate 10, and the p wells 32A and 32B are formed in the semiconductor substrate 10 at the edge region of the n well 33. P + collector junctions 36A and 36B are formed in selected regions of the p wells 32A and 32B, and p + emitter junctions 34 are formed in selected regions of the n wells 33. An emitter electrode E is formed at the emitter junction 34, a base electrode B is formed at the n well 33, and the collector junctions 36A and 36B are connected to each other so that the collector electrode C is formed. ) Is formed.

As described above, in the manufacture of a PNP bipolar transistor having an n well as a base, the n well is used as a base terminal to stabilize the characteristics of the bipolar transistor by improving the base width narrowing effect of the base length of the bipolar transistor. This increases the depletion width width of the collector during device operation.

As described above, according to the present invention, when implementing a bipolar transistor of a self-biased circuit in a flash memory, the collector region is composed of n wells and triple n wells, thereby reducing the base-narrowing effect by the relatively lightly doped n wells. It is possible to reduce the collector resistance by the triple n well of high concentration.

Claims (1)

Forming a triple n well in the semiconductor substrate; Forming an n well on a semiconductor substrate on both sides of the triple n well to form a collector including the triple n well and the n well; Forming a p well on the triple n well, wherein the p well is formed in a semiconductor substrate between the n wells; And forming a collector junction in the n well and a base junction and an emitter junction in the p well, respectively.