KR20000066540A - Method of forming dissymmetric salicide layer in Semiconductor device - Google Patents
Method of forming dissymmetric salicide layer in Semiconductor device Download PDFInfo
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- KR20000066540A KR20000066540A KR1019990013740A KR19990013740A KR20000066540A KR 20000066540 A KR20000066540 A KR 20000066540A KR 1019990013740 A KR1019990013740 A KR 1019990013740A KR 19990013740 A KR19990013740 A KR 19990013740A KR 20000066540 A KR20000066540 A KR 20000066540A
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- layer
- metal layer
- gate electrode
- silicide
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 239000011810 insulating material Substances 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- 238000007669 thermal treatment Methods 0.000 abstract 3
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 29
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조방법에 관한 것으로서, 특히 소스/드레인 영역과 게이트 전극에 동시에 실리사이드막을 형성하기 위한 살리사이드 공정시 소자의 열적안정성과 누설전류특성을 동시에 높일 수 있는 반도체 장치의 비대칭 살리사이드막 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an asymmetrical salicide of a semiconductor device capable of simultaneously enhancing thermal stability and leakage current characteristics of a device during a salicide process for simultaneously forming a silicide film in a source / drain region and a gate electrode. It relates to a film production method.
일반적으로 반도체 장치의 집적도가 증가함에 따라 확산층인 소스/드레인 영역 깊이가 감소하면서 게이트 전극의 선폭과 그 높이가 줄어들게 된다. 이에 따라 표면저항이 증가하고, 금속배선의 면저항이 증가함으로써, 직접회로 내에서는 신호 의 전송 시간이 지연된다.In general, as the degree of integration of a semiconductor device increases, the line width and height of the gate electrode decrease as the depth of the source / drain region, which is a diffusion layer, decreases. As a result, the surface resistance increases and the sheet resistance of the metal wiring increases, thereby delaying the transmission time of the signal in the integrated circuit.
이러한 표면저항 문제점을 개선시키기 위해서 반도체소자는 게이트 전극과 소스/드레인 영역 상부에 동시에 금속층의 실리사이드막을 형성하는 자기정렬방식의 실리사이드(Self-aligned silicide:이하 살리사이드라고 함)기술을 사용하게 되었다.In order to improve the surface resistance problem, a semiconductor device uses a self-aligned silicide (hereinafter referred to as salicide) technology that simultaneously forms a silicide layer of a metal layer on the gate electrode and the source / drain region.
그러나, 반도체 소자가 고집적화됨에 따라 이 살리사이드 공정을 이용한 금속 실리사이드막이 얇고 불균일해져서 국부적으로 미형성되는 부분이 발생하거나 후속 열공정시 확산 현상에 의해 입자가 성장하면서 실리사이드막이 단락되는 경우가 발생하여 이로 인해 표면 저항이 급격하게 증가하게 되는 문제점이 발생하게 되었다.However, as semiconductor devices become highly integrated, the metal silicide film using this salicide process becomes thin and uneven, so that a locally unformed portion may occur, or the silicide film may be short-circuited due to the growth of particles during the subsequent thermal process. There is a problem that the surface resistance is sharply increased.
더욱이, 상대적으로 불순물 도핑 농도가 높은 게이트 전극 위에서는 균일하고 두꺼운 실리사이드막이 형성되기 어렵기 때문에 게이트 전극의 열적 안정성을 높이는데 문제가 있었다. 이를 위해 게이트 전극의 전기적 특성을 높이고자 금속층의 두께를 높이면 소스/드레인 영역 상부의 실리사이드막의 두께 또한 두꺼워져서 이 부분에 누설 전류 특성이 높아지게 되는 문제점이 있으므로 통상의 살리사이드 공정을 이용하여 소자의 전기적 특성을 만족시키는 실리사이드막을 확보하는데에는 한계가 있었다.Furthermore, since it is difficult to form a uniform and thick silicide film on the gate electrode having a relatively high impurity doping concentration, there is a problem in improving the thermal stability of the gate electrode. For this purpose, if the thickness of the metal layer is increased to increase the electrical characteristics of the gate electrode, the thickness of the silicide layer on the source / drain region also becomes thick, so that the leakage current characteristic is increased in this portion. There was a limit in securing a silicide film satisfying the characteristics.
따라서, 본 발명은 이와 같은 문제점을 해결하기 위해 안출한 것으로서, 통상의 살리사이드 공정을 이용하되 게이트 전극 상부면에는 실리사이드층의 두께를 두껍게 하여 전극의 열적안정성을 높이고, 소스/드레인 영역에는 얇은 실리사이드를 형성하여 누설전류의 특성을 높이도록 하는 반도체 장치의 비대칭 살리사이드막 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve such a problem, using a conventional salicide process, but the thickness of the silicide layer on the upper surface of the gate electrode to increase the thermal stability of the electrode, thin silicide in the source / drain region It is an object of the present invention to provide a method for producing an asymmetric salicide film of a semiconductor device to form a to improve the characteristics of the leakage current.
도 1 내지 도 4는 본 발명에 따른 반도체 장치의 비대칭 살리사이드막 형성 과정을 나타낸 공정 순서도이다.1 to 4 are process flowcharts illustrating a process of forming an asymmetric salicide layer of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
2 : 반도체 기판 4 : 필드 산화막2: semiconductor substrate 4: field oxide film
6 : 게이트 산화막 8 : 게이트 전극6 gate oxide film 8 gate electrode
10 : LDD영역 12: 스페이서 절연막10: LDD region 12: spacer insulating film
14: 소스/드레인 영역 16: 제 1금속층14: source / drain region 16: first metal layer
16a: 실리사이드막 16b: 비대칭 실리사이드막16a: silicide film 16b: asymmetric silicide film
18: 절연막 20: 제 2금속층18: insulating film 20: second metal layer
이와 같은 목적을 달성하기 위한 본 발명은 반도체 장치의 살리사이드 제조 방법에 있어서, 필드 산화막이 형성된 반도체 기판의 활성 영역위에 순차 적층된 게이트 산화막과 폴리실리콘층을 패터닝하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 측벽에 절연물질로 이루어진 스페이서 절연막을 형성하는 단계와, 상기 필드 산화막과 스페이서 절연막에 의해 노출된 기판 내부에 불순물을 이온주입하여 소스/드레인 영역을 형성하는 단계와, 상기 구조물 상부에 제 1금속층을 증착하고 제 1차 열처리 공정을 실시한 후에 습식 식각 공정으로 실리콘과 반응되지 않는 금속층을 선택적으로 제거하여 상기 게이트 전극 및 소스/드레인 상부면에 모두 실리사이드막을 형성하는 단계와, 상기 실리사이드막이 형성된 구조물 상부에 절연막을 증착하고 상기 게이트 전극의 상부면이 노출되도록 상기 절연막을 평탄화하는 단계와, 상기 구조물 상부에 제 1금속층과 동일한 제 2금속층을 증착한 후에 제 2차 열처리 공정을 실시하고 습식 식각 공정으로 상기 제 2금속층을 선택식각한 후에 다시 제 3차 열처리 공정을 실시하여 상기 게이트 전극의 상부면에 상기 소스/드레인 상부면의 살리사이드막보다 두껍게 실리사이드막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing a salicide of a semiconductor device, the method comprising: forming a gate electrode by patterning a gate oxide film and a polysilicon layer sequentially stacked on an active region of a semiconductor substrate on which a field oxide film is formed; Forming a spacer insulating film made of an insulating material on the sidewall of the gate electrode, implanting impurities into the substrate exposed by the field oxide film and the spacer insulating film, and forming a source / drain region on the structure; After depositing the first metal layer and performing the first heat treatment process, selectively removing the metal layer that does not react with silicon by a wet etching process to form a silicide layer on both the gate electrode and the source / drain top surface; Deposit an insulating film on top of the formed structure Planarizing the insulating layer to expose the top surface of the gate electrode, depositing a second metal layer identical to the first metal layer on the structure, and then performing a second heat treatment process and wet etching the second metal layer. And performing a third heat treatment process after the selective etching to form a silicide film on the upper surface of the gate electrode to be thicker than the salicide film on the upper surface of the source / drain.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 반도체 장치의 비대칭 살리사이드막 형성 과정을 나타낸 공정 순서도이다.1 to 4 are process flowcharts illustrating a process of forming an asymmetric salicide layer of a semiconductor device according to the present invention.
먼저, 도 1에 도시된 바와 같이 반도체 기판(2)에 소자의 활성 영역과 소자 분리영역을 정의하는 필드산화막(4)을 형성하고, 그 활성 영역 상부에 게이트 산화막(6)을 형성하고, 그 위에 폴리실리콘을 증착한 후 포토레지스트(도시하지 않음)를 도포하고 사진 및 식각 공정을 이용하여 이를 패터닝하여 게이트 전극(8)을 형성한다.First, as shown in FIG. 1, a field oxide film 4 defining an active region and a device isolation region of a device is formed on a semiconductor substrate 2, and a gate oxide film 6 is formed over the active region. After depositing polysilicon on it, a photoresist (not shown) is applied and patterned using a photolithography and etching process to form a gate electrode 8.
그리고, 저농도의 불순물 이온 주입공정을 실시하여 게이트 전극(8)과 필드 산화막(4) 사이에 드러난 기판 내에 LDD영역(10)을 형성하고, 그 결과물에 절연막으로서 실리콘질화물질을 증착하고 이를 전면식각하여 게이트 전극(8) 측벽에 스페이서 절연막(12)을 형성한다. 계속해서, 고농도의 불순물 이온 주입 공정을 실시하여 스페이서 절연막(12) 에지와 필드 산화막(4) 사이의 기판 내에 소스/드레인 영역을 형성한다. 그 다음, 상기와 같은 구조물 전면에 제 1금속층(16)으로서 텅스텐을 증착한다.Then, a low concentration impurity ion implantation process is performed to form the LDD region 10 in the substrate exposed between the gate electrode 8 and the field oxide film 4, and to deposit a silicon nitride material as an insulating film on the resultant, which is then etched entirely. Thus, the spacer insulating film 12 is formed on the sidewall of the gate electrode 8. Subsequently, a high concentration impurity ion implantation process is performed to form a source / drain region in the substrate between the edge of the spacer insulating film 12 and the field oxide film 4. Then, tungsten is deposited as the first metal layer 16 on the front of the structure as described above.
이어서, 도 2에 도시된 바와 같이 제 1차 열처리 공정을 실시하여 게이트 전극(8)과 소스/드레인 영역 상부면에 실리콘과 반응된 텅스텐 실리사이드막(16a)을 형성하고, 습식 식각 공정으로 실리콘과 반응되지 않는 텅스텐(16)을 제거한다. 그리고, 그 구조물 상부에 절연막(18)으로서 실리콘산화막을 두껍게 증착한다.Subsequently, as shown in FIG. 2, a first heat treatment process is performed to form a tungsten silicide layer 16a reacted with silicon on the gate electrode 8 and an upper surface of the source / drain region. The unreacted tungsten 16 is removed. Then, a thick silicon oxide film is deposited as the insulating film 18 on the structure.
그리고, 도 3에 도시된 바와 같이 상기 절연막(18)을 화학적 기계적 평탄화 공정(Chemical mechanical ploishing)을 통해 게이트 전극 상부면이 노출될때까지 평탄화하고, 그 평탄화된 절연막(18) 상부에 제 1금속층과 동일한 텅스텐을 증착하여 제 2금속층(20)을 형성한다.As shown in FIG. 3, the insulating film 18 is planarized until the upper surface of the gate electrode is exposed through a chemical mechanical planarization process, and the first metal layer is formed on the planarized insulating film 18. The same tungsten is deposited to form the second metal layer 20.
이어서, 도 4에 도시된 바와 같이, 제 2차 열처리 공정을 실시하고 습식 식각 공정으로 상기 제 2금속층(20)을 선택식각한 후에 다시 제 3차 열처리 공정을 실시하여 상기 게이트 전극(8)의 상부면에만 상기 소스/드레인(14) 상부면의 살리사이드막(16a)보다 두꺼운 비대칭의 실리사이드막(16b)을 형성한다. 이후, 상기와 같은 실리사이드막(16b)이 형성된 구조물에 층간 절연막(22)을 형성한 후에 통상의 배선공정을 실시한다.Subsequently, as shown in FIG. 4, the second heat treatment process is performed, the second metal layer 20 is selectively etched by the wet etching process, and the third heat treatment process is performed again to perform the third heat treatment process. The asymmetric silicide film 16b thicker than the salicide film 16a on the top surface of the source / drain 14 is formed only on the top surface. Subsequently, after the interlayer insulating film 22 is formed on the structure in which the silicide film 16b is formed, a normal wiring process is performed.
본 발명은 상기 제 1열처리와 제 2열처리 공정에서 급속열처리(rapid thermal process) 장비를 사용하며 500∼750℃의 온도에서 수십초간 진행되도록 한다.The present invention uses rapid thermal process equipment in the first and second heat treatment processes and allows for several tens of seconds at a temperature of 500 to 750 ° C.
그리고, 상기 제 1, 2차 습식 식각 공정은 제 1 및 제 2금속층을 티타늄으로 사용하면 NH4OH:H2:H2O=1:1:5 혼합액에서 식각되도록 하고, 제 1 및 제 2금속층코발트으로 사용하면 H2OSO4:H2O2=4:1 혼합액에서 식각되도록 한다.The first and second wet etching processes may be etched in a mixture of NH 4 OH: H 2 : H 2 O = 1: 1: 5 when the first and second metal layers are used as titanium, and the first and second wet etching processes may be used. When used as a metal layer cobalt, it is etched in H 2 OSO 4 : H 2 O 2 = 4: 1 mixture.
또한, 제 3차 열처리 공정은 소스/드레인 영역과 게이트 전극의 실리사이드막(16a)이 동시에 상태변화가 일어나도록 800∼900℃에서 수십초간 진행되도록 한다.In addition, the third heat treatment process allows the source / drain region and the silicide layer 16a of the gate electrode to proceed for several tens of seconds at 800 ° C to 900 ° C so that a state change occurs simultaneously.
본 발명의 제조 방법은 제 2금속층(20)을 증착하기 전에 선 세정 공정을 실시할 수 있는데 이때, 제 2금속층(20)이 티타늄이면 NH4OH:H2O2:H2O=1:1:5의 혼합 세정액을 사용하고, 제 2금속층(20)이 코발트이면 H2SO4:H2O2=4:1의 혼합 세정액을 사용하는 것이 바람직하다.In the manufacturing method of the present invention, a pre-cleaning process may be performed before the deposition of the second metal layer 20. In this case, if the second metal layer 20 is titanium, NH 4 OH: H 2 O 2 : H 2 O = 1: It is preferable to use a mixed washing liquid of 1: 5 and a mixed washing liquid of H 2 SO 4 : H 2 O 2 = 4: 1 when the second metal layer 20 is cobalt.
이상에서 살펴 본 바와 같이, 본 발명에 의하면 소스/ 드레인의 영역에는 얇은 실리사이드막을 형성하여 소자의 누설전류 특성을 개선시키고, 아울러 게이트 전극 상부에는 상대적으로 두꺼운 실리사이드막을 형성함으로써 소자의 열적 안정성을 개선시킬 수 있도록 하는 이점이 있다.As described above, according to the present invention, a thin silicide film is formed in the source / drain region to improve leakage current characteristics of the device, and a relatively thick silicide film is formed on the gate electrode to improve thermal stability of the device. There is an advantage to this.
Claims (5)
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| KR1019990013740A KR20000066540A (en) | 1999-04-19 | 1999-04-19 | Method of forming dissymmetric salicide layer in Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100400784B1 (en) * | 2001-12-28 | 2003-10-08 | 주식회사 하이닉스반도체 | Method for forming salicide of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100400784B1 (en) * | 2001-12-28 | 2003-10-08 | 주식회사 하이닉스반도체 | Method for forming salicide of semiconductor device |
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