KR20000066433A - Device for administrating board state in digital subscriber line-access multiplexer system - Google Patents

Abstract

PURPOSE: An apparatus for managing a board state in a digital subscriber line-access multiplexer(DSLAM) system is provided to improve a reliability of a management function of the board state by checking a hardware state and a software state of a CPU, checking a state of an other module through a process for identifying as to whether a data transmission with a management board is normally performed, and displaying checked states. CONSTITUTION: A CPU(110) periodically transmits its board state information to a management board(200) and judges as to whether a response signal outputted from the management board(200) is received, The CPU(110) outputs an error state display signal to a first display unit(140) and outputs a periodic reset signal to a first fault monitoring unit when the response signal outputted from the management board(200) is not received. A first bus interface unit(120) receives board state information outputted from the first CPU(110) to transmit received board state information to the management board(200). The first bus interface unit(120) receives the response signal transmitted from the management board(200) through a data bus and transmits the received response signal to the first CPU(110). The first fault monitoring unit(130) performs an interface function between the first CPU(110) and the first display unit(140) and continuously checks a hardware state and a software state of the first CPU(110).

Description

Board Status Management Device in Digital Subscriber Line-Access Multiplexer System {DEVICE FOR ADMINISTRATING BOARD STATE IN DIGITAL SUBSCRIBER LINE-ACCESS MULTIPLEXER SYSTEM}

The present invention relates to a board state management apparatus in a digital subscriber line-access multiplexer system (DSLAM), and more particularly, to the state of each board mounted in the digital subscriber line-access multiplexer system. The board state management device in a digital subscriber line-access multiplexer system that allows the operator to display the device after accurate inspection.

In the conventional digital subscriber line-access multiplexer system, as shown in FIG. 1, a board state management apparatus includes a central process unit (hereinafter referred to as a CPU) 11 and a bus interface unit 12. A plurality of interface boards 10 including a failure monitoring unit 13 and a light emitting diode (LED) 14; It consisted of the management board 20 provided with the CPU 21, the bus interface part 22, the fault monitoring part 23, and LED24.

Meanwhile, referring to the operation of the board state management apparatus in the conventional digital subscriber line-access multiplexer system, each of the failure monitoring units 13 and 23 mounted in the plurality of interface boards 10 and the management board 20 are described. After checking only the hardware state of each CPU (11, 21) mounted in its board, if the abnormality occurs, the LED (14, 24) lights up in red.

In addition, the CPU 21 in the management board 20 outputs the status information request signals to the plurality of interface boards 10, and after receiving the status information from the plurality of interface boards 10, each of them receives an input, After checking the state of the interface board 10, the information is transmitted to the upper processor.

However, in the board state management apparatus of the conventional digital subscriber line-access multiplexer system, when each board checks its own state, it checks only the hardware state of the CPU and displays whether or not an error has occurred to the operator. The hardware status of the system is normal, but if an error occurs due to a failure of another module in the board, it could not be displayed to the operator after checking it, which causes the operator to not check the exact board status because the reliability of the board status display function is low. There was a problem.

In addition, as a board state management apparatus in a conventional digital subscriber line-access multiplexer system, the management board checks the overall state of a plurality of interface boards and then transmits the state information of the interface boards to a higher processor. Since there was no function of displaying the overall state of the interface boards, the operator could not check the overall state of the plurality of interface boards at a glance, and there was a problem that more efficient board management was difficult.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to improve the reliability of the board state management function, thereby enabling a digital subscriber line-access multiplexer to display a more accurate board state to an operator. To provide a board state management device in the system.

Another object is to provide a board status management apparatus in a digital subscriber line-access multiplexer system that allows the management board to directly display the overall status of a plurality of interface boards to the operator.

In order to achieve the above object, the board state management apparatus in the digital subscriber line-access multiplexer system of the present invention comprises: a plurality of interface boards; In the digital subscriber line-access multiplexer system comprising a management board for managing the state of the plurality of interface boards,

The plurality of interface boards periodically transmit their board status information to the management board, and then determine whether a response signal output from the management board has been received, and if not, output an error status display signal. A first CPU for outputting a periodic reset signal; A first bus interface unit transmitting board state information output from the first CPU to the management board through a data bus in a backboard, and transmitting a response signal transmitted from the management board to the first CPU; The first CPU receives and transmits an error state display signal, and continuously monitors the hardware operating state of the first CPU to output an error state display signal when an abnormality occurs, and periodically resets the reset signal from the first CPU. A first failure monitoring unit for outputting an error state display signal even when the signal is not outputted to the mobile terminal; A first display unit configured to receive an error state display signal from the first fault monitoring unit and display its board state to an operator;

When the management board periodically transmits board status information from the plurality of interface boards, the management board transmits a response signal to each interface board after receiving it, while not receiving all board status information from the plurality of interface boards. A second CPU for outputting an interface board error status display signal and outputting a software periodic reset signal; A second bus interface unit transmitting a response signal output from the second CPU to a plurality of the interface boards through a data bus in a backboard, and transmitting board state information transmitted from the plurality of interface boards to the second CPU; Wow; The second CPU receives and transmits an interface board error / normal state display signal, while continuously monitoring the hardware operation state of the second CPU, and outputs an error state display signal when an error occurs. A second failure monitoring unit for outputting an error state display signal even when the reset signal is not output periodically; A second display unit configured to receive an interface board error status display signal from the second fault monitor and display a plurality of interface board states to an operator; When receiving the error status display signal from the second failure monitoring unit, it is characterized in that the third display unit for displaying its own board status to the operator.

1 is a functional block diagram showing the configuration of a board state management apparatus in a conventional digital subscriber line-access multiplexer system;

2 is a functional block diagram showing the configuration of a board state management apparatus in a digital subscriber line-access multiplexer system according to an embodiment of the present invention;

3 is a functional block diagram showing a detailed configuration of the first failure monitoring unit in the board state management apparatus in the digital subscriber line-access multiplexer system according to FIG.

4 is a functional block diagram illustrating a detailed configuration of a second failure monitoring unit in the board state management apparatus of the digital subscriber line-access multiplexer system according to FIG. 2.

<Description of the code | symbol about the principal part of drawing>

100: interface board 110: the first CPU

120: first bus interface unit 130: first fault monitoring unit

131: first CPU interface unit 132: first hardware state monitoring unit

133: first software status monitoring unit 140: first display unit

200: management board 210: second CPU

220: second bus interface unit 230: second fault monitoring unit

231: second CPU interface unit 232: second hardware state monitoring unit

233: second software status monitoring unit 240: second display unit

250: third display unit

Hereinafter, an apparatus for managing a board state in a digital subscriber line-access multiplexer system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a functional block diagram of a board state management apparatus in a digital subscriber line-access multiplexer system according to an embodiment of the present invention, and FIG. 3 is a digital subscriber line-access multiplexer system according to an embodiment of the present invention. 4 is a functional block diagram illustrating a detailed configuration of the first failure monitoring unit in the board state management apparatus, and FIG. 4 is a view of the second failure monitoring unit in the board state management apparatus in the digital subscriber line-access multiplexer system according to an embodiment of the present invention. As a functional block diagram showing a detailed configuration, the board state management apparatus in the digital subscriber line-access multiplexer system according to an embodiment of the present invention is composed of a plurality of interface board 100 and the management board 200.

The plurality of interface boards 100 are boards in charge of the interface between the boards, and include a first CPU 110, a first bus interface unit 120, a first failure monitoring unit 130, and a first display unit 140. It consists of).

In this case, the first CPU 110 mounted in the plurality of interface boards 100 periodically transmits its own board state information to the management board 200, and then the response signal output from the management board 200 is received. If it is determined that the received signal is not received, an error state display signal is output to the first display unit 140, and a periodic reset signal is output to the first fault monitor.

In addition, the first bus interface unit 120 mounted in the interface board 100 receives board state information output from the first CPU 110 and transmits the board state information to the management board 200. The response signal transmitted from the management board 200 is received through the data bus in the back board, and serves to transmit the first CPU 110.

In addition, the first failure monitoring unit 130 mounted in the interface board 100 performs an interface function between the first CPU 110 and the first display unit 140 and the first CPU 110. The hardware status and the software status of the () continue to check and manage, the first CPU interface unit 131, the first hardware (Hardware) state monitoring unit 132 and the first software (Software) state monitoring unit ( 133).

In this case, when the first CPU interface unit 131 mounted in the first failure monitoring unit 130 receives the error state display signal output from the first CPU 110, the first CPU interface unit 131 transmits the error state display signal to the first display unit 140. When the first CPU 110 outputs a reset signal, the reset signal is transmitted to the first software state monitoring unit 133 after receiving the reset signal.

On the other hand, the first hardware state monitoring unit 132 mounted in the first failure monitoring unit 130 continuously monitors the hardware operating state of the first CPU 110 (Monitering) when an error occurs, if an error occurs Outputs a display signal to the first display unit 140.

In addition, the first software status monitoring unit 133 mounted in the first failure monitoring unit 130 has a timer mounted therein, and automatically displays the error status display signal when a periodic time is reached. A device for outputting to the first display unit 140. When a reset signal is periodically input from the first CPU interface unit 131, an internal timer is reset to output an error state display signal to the first display unit 140. If the reset signal is not periodically input from the first CPU interface unit 131, the internal timer is not reset, thereby outputting an error state display signal to the first display unit 140. .

In addition, when the first display unit 140 mounted in the plurality of interface boards 100 outputs an error state display signal from the first failure monitoring unit 130, the first display unit 140 receives an input thereof and indicates that its own board state is an error state. It serves to display to the operator.

On the other hand, the management board 200 is a board that manages the state of the plurality of interface board 100, the second CPU 210, the second bus interface unit 220, the second failure monitoring unit 230, The second display unit 240 and the third display unit 250 are configured.

In this case, when the second CPU 210 mounted in the management board 200 periodically transmits board state information from the plurality of interface boards 100, the second CPU interface 220 receives the second bus interface unit 220 after receiving the board state information. If a response signal is transmitted to each of the interface boards 100 and no board status information is received from the plurality of interface boards 100, an interface board error status display signal is sent to the second display unit 240. And outputs a reset signal periodically to the second failure monitoring unit 230.

In addition, the second bus interface unit 220 mounted in the management board 200 receives a response signal output from the second CPU 210 and transmits the received response signal to the plurality of interface boards 100. The board state information transmitted from the two interface boards 100 is received through the data bus in the back board, and serves to transmit to the second CPU 210.

Meanwhile, the second failure monitoring unit 230 mounted in the management board 200 performs an interface function between the second CPU 210 and the second and third display units 240 and 250, and the second CPU It serves to continuously check and manage the hardware state and software state of the 210, and comprises a second CPU interface unit 231, a second hardware state monitoring unit 232 and a second software state monitoring unit 233. It is.

In this case, when the second CPU interface unit 231 mounted in the second failure monitoring unit 230 receives the interface board error status display signal output from the second CPU unit 210, the second display unit ( 240, and when receiving the reset signal output from the second CPU 210, transmits the signal to the second software state monitoring unit 233.

In addition, the second hardware state monitoring unit 232 mounted in the second failure monitoring unit 230 continuously monitors the hardware operating state of the second CPU 210, and if an error occurs, an error state display signal is output. It serves to output to the third display unit 250.

On the other hand, the second software state monitoring unit 233 mounted in the second failure monitoring unit 230 is equipped with a timer therein, the third display unit 250 automatically outputs an error state display signal when a periodic time is reached. And a reset signal is periodically input from the second CPU interface unit 231, and an internal timer is reset to output the error state display signal to the third display unit 250. If the reset signal is not periodically input from the second CPU interface unit 231, the internal timer is not reset, thereby outputting an error state display signal to the third display unit 250.

In addition, when the second display unit 240 mounted in the management board 200 outputs an interface board error status display signal from the second fault monitoring unit 230, the second display unit 240 receives the input of the interface board 100. It plays a role to display to the operator that the state of all is error state.

On the other hand, when the third display unit 250 mounted in the management board 200 outputs an error state display signal from the second fault monitoring unit 230, the third display unit 250 receives the input signal to the operator that the board state is an error state. It serves to display.

Next, an operation process of the board state management apparatus in the digital subscriber line-access multiplexer system having the above configuration will be described with reference to FIGS. 2, 3, and 4.

First, a process of checking the state of the plurality of interface boards 100 in the management board 200 and displaying the result to the operator will be described below.

First, the first CPU 110 mounted in the plurality of interface boards 100 periodically outputs its board state information to the first bus interface unit 120. Then, the first bus interface unit 120 receives the board state information output from the first CPU 110 and transmits it to the management board 200 through the data bus of the back board.

Then, the second bus interface unit 220 mounted in the management board 200 receives board state information transmitted from the plurality of interface boards 100 and transmits the received board state information to the second CPU 210. In addition, the second CPU 210 mounted in the management board 200 periodically receives state information about the plurality of interface boards 100 output from the second bus interface unit 220, and then, The response signal is transmitted to each interface board 100 through the second bus interface unit 220.

However, at this time, if the second CPU 210 mounted in the management board 200 does not transmit all the board status information from the plurality of interface boards 100, the second failure monitoring unit outputs an interface board error status display signal. Outputs to the second display unit 240 through the second CPU interface unit 231 mounted in 230. Then, the second display unit 240 receives an error state display signal output from the second CPU interface unit 231 and displays to the operator that the states of the plurality of interface boards 100 are all in error state. .

In addition, after the management board 200 checks its status, it will be described a process of displaying to the operator.

First, the second hardware state monitoring unit 232 mounted in the second failure monitoring unit 230 continuously monitors the hardware operating state of the second CPU 210, and if an error occurs, the error state display signal is output. Output to the third display unit 250. Then, the third display unit 250 mounted in the management board 200 receives an error state display signal output from the second hardware state monitoring unit 232 and informs the operator that his board state is an error state. Display.

In addition, the second software state monitoring unit 233 mounted in the second failure monitoring unit 230 has a timer mounted therein, and automatically outputs the error state display signal to the third display unit 250 when a periodic time is reached. ) Is implemented.

However, the second CPU 210 outputs a reset signal to the second CPU interface unit 231 at regular intervals, and the second CPU interface unit 231 outputs the reset signal from the second CPU 210. After receiving the signal and outputs to the second software state monitoring unit 233, wherein the second software state monitoring unit 233 receives the reset signal, and resets the timer mounted therein an error state display signal. Is not output to the third display unit 250.

However, when the second CPU 210 fails to output the periodic software reset signal, the second software state monitoring unit 233 does not reset its timer. 3 is output to the display unit 250. Then, the third display unit 250 receives an error state display signal output from the second software state monitoring unit 233 and displays to the operator that his board state is an error state. Therefore, the second software state monitoring unit 233 is a system for checking software of the second CPU 210.

On the other hand, in the following it will be described a process of displaying a plurality of the interface board 100 to the operator after checking their respective status.

First, the first CPU 110 mounted in the plurality of interface boards 100 periodically outputs its board state information to the first bus interface unit 120. Then, the first bus interface unit 120 receives the board state information output from the first CPU 110 and transmits it to the management board 200 through the data bus of the back board.

Then, the second bus interface unit 220 mounted in the management board 200 receives board state information transmitted from the plurality of interface boards 100 and transmits the received board state information to the second CPU 210. In addition, the second CPU 210 mounted in the management board 200 periodically receives state information about the plurality of interface boards 100 output from the second bus interface unit 220, and then, The response signal is transmitted to each interface board 100 through the second bus interface unit 220.

In this case, the first CPU 110 mounted in the interface board 100 determines whether a response signal output from the management board 200 is received. If not, the first CPU 110 outputs an error status display signal to the first failure monitoring unit. Output to the first CPU interface unit 131 mounted in 130. Then, the first CPU interface unit 131 receives the error state display signal output from the first CPU 110 and outputs the error state display signal to the first display unit 140 again. In addition, the first display unit 140 receives an error state display signal output from the first CPU interface unit 131 and displays to the operator that its board state is an error state. However, the error content of the interface board 100 described above is not an error of the first CPU 110, but corresponds to an error of another module in the board.

On the other hand, the first hardware state monitoring unit 132 mounted in the first failure monitoring unit 130 continuously monitors the hardware operating state of the first CPU 110, and if an error occurs, the error state display signal Output to the first display unit 140. Then, the first display unit 140 mounted in the interface board 100 receives an error state display signal output from the first hardware state monitoring unit 132 to inform the operator that his board state is an error state. Display. Therefore, the error content of the interface board 100 described above corresponds to a hardware error of the first CPU 110.

In addition, the first software state monitoring unit 133 mounted in the first failure monitoring unit 130 has a timer mounted therein, and automatically displays the error state display signal when the periodic time is reached. ) Is implemented. However, the first CPU 110 outputs a reset signal to the first CPU interface unit 131 at predetermined intervals, and the first CPU interface unit 131 outputs the reset signal from the first CPU 110. After receiving the signal is output to the first software state monitoring unit 133, the first software state monitoring unit 133 receives the reset signal, and resets the timer mounted therein an error state display signal Is not output to the first display unit 140.

However, when the first CPU 110 fails to output the software periodically reset signal, the first software state monitoring unit 133 does not reset its timer, so that the error state display signal is generated by the first CPU 110. 1 is output to the display unit 140. Then, the first display unit 140 receives an error state display signal output from the first software state monitoring unit 133 and displays to the operator that his board state is an error state. Therefore, the error contents of the interface board 100 described above correspond to a software error of the first CPU 110.

According to the board state management apparatus in the digital subscriber line-access multiplexer system according to the present invention as described above, when each board checks its own board state, it checks the hardware state and software state of the CPU, and manages it. It checks and displays the status of other modules in the board through the procedure to check if the data transfer with the board is normal, thereby increasing the reliability of the board status management function, allowing the operator to check the board status more accurately. Has an excellent effect.

Another effect is that the management board checks the status of multiple interface boards and then displays the overall status of the interface boards directly to the operator, thereby allowing the operator to check the overall interface board status at once.

Claims (3)

A plurality of interface boards; In the digital subscriber line-access multiplexer system comprising a management board for managing the state of the plurality of interface boards, The plurality of interface boards periodically transmit their board status information to the management board, and then determine whether a response signal output from the management board has been received, and if not, output an error status display signal. A first CPU for outputting a periodic reset signal; A first bus interface unit transmitting board state information output from the first CPU to the management board through a data bus in a backboard, and transmitting a response signal transmitted from the management board to the first CPU; The first CPU receives and transmits an error state display signal, and continuously monitors the hardware operating state of the first CPU to output an error state display signal when an abnormality occurs, and periodically resets the reset signal from the first CPU. A first failure monitoring unit for outputting an error state display signal even when the signal is not outputted to the mobile terminal; A first display unit configured to receive an error state display signal from the first fault monitoring unit and display its board state to an operator; When the management board periodically transmits board status information from the plurality of interface boards, the management board transmits a response signal to each interface board after receiving it, while not receiving all board status information from the plurality of interface boards. A second CPU for outputting an interface board error status display signal and outputting a software periodic reset signal; A second bus interface unit transmitting a response signal output from the second CPU to a plurality of the interface boards through a data bus in a backboard, and transmitting board state information transmitted from the plurality of interface boards to the second CPU; Wow; The second CPU receives and transmits an interface board error / normal state display signal, while continuously monitoring the hardware operation state of the second CPU, and outputs an error state display signal when an error occurs. A second failure monitoring unit for outputting an error state display signal even when the reset signal is not output periodically; A second display unit configured to receive an interface board error status display signal from the second fault monitor and display a plurality of interface board states to an operator; And a third display unit configured to display its own board state to an operator when the second fault monitoring unit receives an error state display signal. The method of claim 1, The first failure monitoring unit may include: a first CPU interface unit receiving an error state display signal from the first CPU and transmitting the received error state display signal to the first display unit, and receiving and transmitting a reset signal from the first CPU; A first hardware state monitoring unit continuously monitoring a hardware operating state of the first CPU and outputting an error state display signal to the first display unit when an error occurs; When the reset signal is periodically input from the first CPU interface unit, an internal timer is reset to output the error state display signal to the first display unit, while the reset signal is not periodically input from the first CPU interface unit. Otherwise, the internal timer is not reset so that the first software state monitoring unit outputs an error state display signal to the first display unit. The method of claim 1, The second failure monitoring unit receives an interface board error / normal state display signal from the second CPU and transmits it to the second display unit, and receives and transmits a reset signal when the second CPU outputs a reset signal. An interface unit; A second hardware state monitoring unit for continuously monitoring a hardware operating state of the second CPU and outputting an error state display signal to the third display unit when an error occurs; When the reset signal is periodically input from the second CPU interface unit, an internal timer is reset to output the error status display signal to the third display unit, while the reset signal is not periodically input from the second CPU interface unit. Or a second software state monitor for outputting an error state display signal to the third display unit because the internal timer is not reset.