GB2085205A - Apparatus for monitoring auxiliary information and for fault diagnosis - Google Patents

Abstract

A central control comprises two identical processors A, B, each of which includes a central memory unit 1, a central processing unit 2, and an input- output unit 3 which is connected to peripheral users 5. Each central processing unit 2 comprises a plurality of functional units mutually connected to each other and including a central control unit 6, a watching unit 8, an updating and synchronization unit 9 and a console unit 10. The apparatus further comprises a support processor 15 which is connected to each central- control processor A, B by way of a duplicated electrical structure 16, 16A, 16B, 20A, 20B and 116, 116A, 116B, 120A, 120B. The support processor monitors the auxiliary information affecting the central control, when the two processors A, B operate in synchronism. In the absence of synchronism, caused by a fault in processor A or B, the central control monitors the auxiliary information of the processor operating while proceeding to diagnose the faulty processor by replacing its respective console unit 10 while taking advantage of possible information obtained as a result of a first diagnosis effected by the latter processor. <IMAGE>

Description

SPECIFICATION Improvements in or relating to apparatuses for monitoring auxiliary information about central controls of peripheral users and for fault diagnosis thereof The present invention relates to an apparatus for monitoring auxiliary information about and for fault diagnosis of a central control of a plurality of peripheral users. Such an apparatus may be used with the control logic for controlling peripheral users of P.C.M. type (e.g. terminal telephone exchanges) by means of a buffer exchange comprising a buffer network and the said central control.

According to the invention, there is provided an apparatus for monitoring auxiliary information about and for performing fault diagnosis of a central control of a plurality of peripheral users and comprising two identical processors, each of which includes a central memory unit, a central processing unit, and an input-output unit which is connectable to the input-output unit in the other processor and to the peripheral users, the said units being mutually connectable to each other, each central processing unit comprising a central control unit, a time-base generating unit, a watching and alarm receiving unit, an updating and synchronization unit, and a console unit, the time generating unit, the watching unit, the updating unit and the console unit being connected to the central control unit by way of two channels respectively arranged to convey input and output information of the central control unit, the apparatus comprising at least one processor connected through at least two bidirectional channels to two sections, respectively, arranged to control messages to and from, the at least one processor and to address and withdraw the messages under control of the at least one processor towards and from further bidirectional channels for connecting the two sections to the input-output units of the identical processors, there being provided connecting means for connecting the at least one processor to the console units of the identicle processors of the central control.

It is thus possible to provide an apparatus which is associated with a central control comprising two identical processors which can operate in parallel and in synchronism or independently of one another, and which monitors the auxiliary information affecting the central control (user's charging, statistics, traffic alterations, etc.) and dialogues with the central-control processor, when the latter is malfunctioning, so as to intervene by means of a succession of diagnosis programmes arranged according to predetermined hierarchic scales so as to identify the malfunction, while normal monitoring or control "dialogue" or exchange of auxiliary information with the correctly operating processor goes on.

The "support" processor in a preferred embodiment can be used to replace the console unit of the faulty processor in the central control, which makes it possible to cause the latter processor to become a slave of the support processor with all of the advantages of remote control and use in sequence of specific programmes hierarchically arranged in the support processor registers.

The present invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a block diagram of an apparatus constituting a preferred embodiment of the invention and a central control associated them with; and Figure 2 shows a further block diagram of a modified apparatus and the central control associated therewith.

With reference to the drawings, a central control unit is indicated at 100 and comprises two processors A and B identical to one another. Each proces sor has a central memory unit la acentral processing unit 2 and an input-output unit 3. These units are mutually conectable through a channel 4.

The central processing unit 2, in turn, comprises a central control unit 6, a time-base generating unit 7, a watching and alarm-receiving unit 8, an updating and synchronization unit 9, and a console unit 10.

The units 7, 8, 9 and 10 are connected to the central control unit 6 by way of two channels 11 and 12 designed to respectively convey output and input information of the control unit 6. The console unit 6.

The console unit 10 can directly intervene on the "heart" of the processor, i.e. on the central control unit 6 by way of a suitable channel 14. It should be noted that in Figure 1 the units 7, 8 and 9 of one processor are connected to corresponding units in the other or adjacent processor by way of connection channels generally indicated by 13.

Afurther processor 15 (usually termed a support processor in the art) is associated with a dialogue unit 15a (a teletypewriter, visual display unit, or the like means). The processor 15 can be connected by way of a bidirectional channel 19 to a control section 16 further described hereinafter. Similarly, the processor 15 can be connected by way of a further bidirectional channel 119 to a further control section 116 similar to the section 16. The control section 16 can be connected to the input-output units 3 in the procesors A and B by way of respective bidirectional channels 16A and 1 6B. Similarly, the control section 116 can be connected to the input-output units 3 in the processors A and B by way of respective bidirectional channels 116A and 1168.

Moreover, the control section 16 can be connected to the console units 10 in the processors A and B by way of respective bidirectional channels 20A and 20s Similarly, the control section 116 can be connected to the console units 10 in the processors A and B by way of respective bidirectional channels 1 20A and l20#.

The support processor 15 is thus connected to the processors A and B by way of a duplicated electrical structure (two channels 19 and 119, two control sections 16 and 116, etc.). This results in the connection being maintained even in the case of malfunctioning of one of the channels of each pair, or of one of the two control sections.

The input-output units 3 are connected to respective peripheral users 5 by way of a pair of bidirection al channels 5a and 5b. As a specific peripheral user a control unit 15 of a teletypewriter (or visual display unit) 215 has been shown in the drawings. The unit 115 is connected for the above mentioned reasons to the input-output units 3 by way of a pair of bidirectional channels 115A and 1158.

As is known, the processors A and B can operate either independently of, or in parallel with, one another. Standard operation takes place in parallel, in which case instruction synchronization is ensured.

In other words, both processors A and B carry out the same instruction in the same time interval and, should the time taken by the two processes differ, the begining of execution of a new instruction is made synchronous because the faster processor waits for the slower one. The units used for fulfilling this function are the two twin updating and synchronization units 9.

In the synchronized condition, the input-output units 3 in the two processors are active, even if only one of the two processors is the master, i.e. controls message exchange operations, with respect to the peripheral users 5.

In the synchronized condition, the support proces sor 15 monitors so-called auxiliary information, i.e.

information about charging, peripheral user operation, telephone traffic modifications, statistics, etc.

To this end, the processor 15 uses the channel 19 (or alternately the channel 119) and the control section 16 (or alternately the section 116) which dialogues with the input-output units 3 of the two processors A and B by way of the bidirectional channels 1 6A and 16B, whereas the bidirectional channels 20A and 20s are deactivated. Of course, corresponding considerations apply to the case where the control section 116 is used.

As mentioned above, the standard operational mode of the two processors A and B is the one in parallel, but the two processors A and B can also operate independently of each other, in which case only one of them (the master) monitors the peripheral users 5, whereas the other usually executes diagnosis programmes as a result of its previous malfunctioning. In otherwords, the two processors A Aand B are isolated from one another (i.e. they go out of synchronization) when logic or electrical or functional anomalies are detected in one of them.

The watching and alarm receiving unit 8 of each processor is connected to the electric terminals of a plurality of controllers (software controllers arranged to detect non-observance of the processing limits and the maximum processing time, and hardware controllers in the processor). The controllers are arranged in predetermined groups and their activation is stored in state registers provided in the central control.

An interrupt level is associated with each register and the various levels differ from each other and are arranged in a hierarchic scale. Thus, an internal alarm starts the software procedure associated with the state register in which the internal alarm is stored.

In the case of a plurality of simultaneous internal alarms which are not stored in the same register, a priority hardware mechanism gives precedence to the highest hierarchic level interrupt. Other possible interrupts having lower priority remain stored and can activate the software procedures associated therewith at the end of the highest priority interrupt procedure, unless such a procedure decides to stop the prosecution as it has reached sufficient information to identify the faulty functional block. The software procedures concerning the first level diagnosis are all stored in the central memory unit of each processor and terminate by making the support processor ready for receiving all information about the faulty functional block and all further useful information about both the further second level diagnosis as is described hereinafter, and their possible storing.

If, for instance, the processor A is the faulty one, the above-mentioned information is supplied to the support processor 15 by way of the channel 1 6A, the control section 16, and the channel 19 or, alternately, by way of channel 11 6A the control section being 116 and the channel 119.

Incidentally, it should be noted that the said controllers cover about 18 to 19 per cent of the possible failures affecting the processor. If a failure occurs which is not sensed by the controllers, a so-called mismatch alarm is triggered upon an erroneous comparison detected by the two updating and synchronization sections 9. In this case, the two processors A and B are isolated from one another and an interrupt request (having a higher hierarchic level than the other interrupt request) is produced in the two processors, which results in the processing being interrupted to call a suitable specific diagnosis programme. Should such a specific programme spot the faulty processor, the latter is isolated, while the other processor acts as a master.If no failure is detected in any one of the two processors A and B, the latter start again to operate in synchronism, which results (in most cases) in one of the controllers then being activated with the above-mentioned consequences. All the first level diagnosis can be executed automatically only in the case where the failure is not fatal, i.e. it is not so severe as to make the processor affected by the failure completely useless. In this situation, the support processor 15 does not obviously receive any information about the nature and the location of the failure in question.

The support processor has at its disposal information about the nature of the failure (in the case where the first level diagnosis has taken place), or has no information, or has incongruent information. In this latter case, the processor must start a general diagnosis procedure.

At this point, the support processor 15, still supposing the processor A to be faulty, initially uses the channel 16A (or alternately the channel 11 6A) to check whether the main components of the processorA are surviving (hardcore procedure) without which no further software programmes regarding the second level diagnosis can be called.

Subsequently (supposing that the control section 16 is used) the channel 20A is activated (so as to directly intervene, by taking its place, on the console unit 10 in the processor A), whereas the channel 1 6B is used to control the auxiliary information for the master processor B.

The so-called second level diagnosis of the central control (e.g. of the processor A) is effected with the aid of the support processor 15 by using the control sections and the bidirectional channels already described above. Such a diagnosis is started by the support processor itself upon receiving a message from the faulty processor informing about the situation which has occured. The support processor then obtains information on the first level diagnosis and worn the operator through suitable display means.Subsequently a procedure is started in the support processor to check whether in the faulty processor (e.g. the processor A) under diagnosis the minimum function survived which permits the second level automatic procedure to be started (by using the channel 16A or, alternately, the channel 1 16A). The channel 20A (as already mentioned above) is then activated and connects the processor 15 to the control unit 10 of the processor A, and the second level diagnosis procedures are carried out either autonomously by the support processor under the operator's direction by using the channel 20A and the console unit 10 (which intervenes on its respective central control unit 6 through the channel 14 and makes the processorAfullybecome a slave of the support processor 15).

On the ground of the information, if available (otherwise one procedes with a general diagnosis) obtained by the first level diagnosis, programmes which permit to stress the functional block under examination and to obtain malfunctioning symptoms, are successively loaded on the processor under diagnosis (i.e. the processor A). However, such programmes which reside in the support processor, are executed on the central control processor under diagnosis.

Each of such second level diagnosis programmes terminates either with spotting the failure or with a proceed request to the support processor by sending a further programme by descending along a tree programme chain.

The second level diagnosis operation normally terminates with the indication of a circuit board to be replaced. During the second level diagnosis simple manual connecting or disconnecting operations for the connectors or boards can be required. These manual operation requests may be made in conjunction with well specified video signals.

From the above the functions fulfilled by the control sections 16 and 116 should be clear. Considering for instance the section 16, the latter, when the processors A and B are in a synchronized condition, permits connection of the support processor 15 to the input-output units of 3 of both processors through the channels 16A and 1 6B. During the second level diagnosis (supposing that the processor A is malfunctioning), the section 16 permits connection of the input-output unit 3 in the processor B to the support processor 15 through the channel 1 6B to control the auxiliary information.Also during the diagnosis procedure, the section 16 first uses the channel 1 6A to check the survival of the vital functions in the processor A and then permits connection of the console unit 10 in the processor A to the support processor 15 through the channel 20A Another important function fulfilled by the control sections 16 and 116 is to ensure repeatability of the messages passing through them. Moreover, in the case of errors along the channels leading to them, it is possible to instantaneously isolate the control section in question from a faulty channel, which is particularly important since, as already mentioned above, it is possible to have direct access by way of the control sections to the console units of both processors A and B.

An embodiment of the sections 16 and 116 fulfilling the above functions is disclosed in the Italiam Patent Application No. 24284 A/80 filed on the 26 August 1980 in the name of the Applicants of the present application.

The embodiment of the above-described apparatus in accordance with the present invention is practical and advantageous in that it permits connections between the support processor 15 and the two control sections 16 and 116 through two bidirectional channels 19 and 119 only. This permits the support processor to be placed at large distances from the central control without calling for a considerable number of cables.

In the case where the processor 15 is sufficiently close to the central control, it is possible to use two channels 200A and 200B only (indicated by a broken line in Figure 2) to directly connect the console units to the support processor 15 instead of employing the channels 20A, 120A; 20s and 120B to gain access to the console units 10 of the processor A the processor B. The control section 16 and 116 are then clearly less "intelligent" as they are designed to operate a smaller number of channels then in the previous cases.

Claims (5)

1. An apparatus for monitoring auxiliaryinfor- mation about and for performing fault diagnosis of a central control of a plurality of peripheral users and comprising two identical processors, each of which includes a central memory unit, a central processing unit, and an input-output unit which, is connectable, and to the input-output unit in the other processor and to the peripheral users, the said units being mutually connectable to each other, each central processing unit comprising a central control unit, a time-base generating unit, a watching and alarm receiving unit, an updating and synchronization unit, and a console unit, the time generating unit, the watching unit, the updating unit and the console unit being connected to the central control unit by way of two channels respectively arranged to convey input and output information of the central control unit, the apparatus comprising at least one processor connected through at least two bidirectional channels to two sections, respectively, arranged to control messages to and from, the at least one processor and to address and withdraw the messages under control of the at least one processor towards and from further bidirectional channels for connecting the two sections to the input-output units of the identical processors, there being provided connecting means for connecting the at least one processor to the console units of the identicle processors of the central control.

2. An apparatus as claimed in the preceding claim, in which the connecting means comprises the two bidirectional channels and the two sections, at least two pairs of additional bidirectional channels respectively connecting the two sections 16 and 116 to the console units of the processors of the central control.

3. An apparatus as claimed in claim 1, in which the connecting means comprises at least two additional bidirectional channels respectively connecting the processor to the console units of the processors of the central control.

4. An apparatus substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

5. A central control including an apparatus as claimed in any one of the preceding claims.