KR20000066095A - Method for forming gate electrode in semiconductor device - Google Patents
Method for forming gate electrode in semiconductor device Download PDFInfo
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- KR20000066095A KR20000066095A KR1019990012945A KR19990012945A KR20000066095A KR 20000066095 A KR20000066095 A KR 20000066095A KR 1019990012945 A KR1019990012945 A KR 1019990012945A KR 19990012945 A KR19990012945 A KR 19990012945A KR 20000066095 A KR20000066095 A KR 20000066095A
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- titanium silicide
- film
- gate electrode
- layer
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 52
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 29
- 230000003647 oxidation Effects 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000010405 reoxidation reaction Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 13
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000002425 crystallisation Methods 0.000 claims 1
- 230000008025 crystallization Effects 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000003685 thermal hair damage Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 238000009279 wet oxidation reaction Methods 0.000 description 3
- 229910008486 TiSix Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로, 보다 구체적으로는 폴리실리콘막과 티타늄 실리사이드막의 적층구조로 이루어진 게이트 전극의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly, to a method of forming a gate electrode having a laminated structure of a polysilicon film and a titanium silicide film.
일반적으로, 게이트 전극은 모스 트랜지스터를 셀렉팅하는 전극으로서, 주로 불순물이 도핑된 폴리실리콘막으로 형성되거나 또는 불순물이 도핑된 폴리실리콘막과 텅스텐 실리사이드막(WSi2)의 적층막으로 형성된다.In general, the gate electrode is an electrode for selecting a MOS transistor, and is mainly formed of a polysilicon film doped with impurities or a laminated film of a polysilicon film and a tungsten silicide film WSi 2 doped with impurities.
그러나, 상기한 불순물이 도핑된 폴리실리콘막과 불순물이 도핑된 폴리실리콘막/텅스텐 실리사이드막은 낮은 집적도를 갖는 반도체 소자에는 용이하게 사용되나, 현재의 고집적 반도체 소자의 미세 게이트 전극으로는 낮은 저항값 특성을 만족시키지 못하여, 이를 사용하는데 어려움이 있다.However, the above-described impurity doped polysilicon film and impurity-doped polysilicon film / tungsten silicide film are easily used in semiconductor devices having low integration, but have low resistance value characteristics as the fine gate electrodes of the current highly integrated semiconductor devices. There is a difficulty in using it because it is not satisfied.
이에 종래에는 텅스텐 실리사이드막보다 전도 특성이 우수한 티타늄 실리사이드막(TiSi2)을 폴리실리콘막 상부에 적층하여 게이트 전극을 형성하는 방법이 제안되었는데, 이에 대하여 첨부도면 도 1a 내지 도 1e를 참조하여 설명한다.Accordingly, a method of forming a gate electrode by stacking a titanium silicide layer (TiSi 2 ) having superior conductivity than a tungsten silicide layer on a polysilicon layer has been proposed, which will be described with reference to FIGS. 1A to 1E. .
도 1a를 참조하여, 반도체 기판(1) 상부에 게이트 산화막(2)을 열성장 또는 증착 방식에 의하여 형성한다음, 게이트 산화막(2) 상부에 불순물이 도핑된 폴리실리콘막(3)을 소정두께로 증착한다.Referring to FIG. 1A, a gate oxide film 2 is formed on the semiconductor substrate 1 by thermal growth or vapor deposition, and then a polysilicon film 3 doped with impurities on the gate oxide film 2 is formed to a predetermined thickness. To be deposited.
그후, 도 1b에 도시된 바와 같이, 폴리실리콘막(3) 상부에 물리적 증착 방식으로 티타늄 실리사이드막(4)을 증착한다. 이때, 증착시 티타늄 실리사이드막(4)은 비정질 상태이다.Thereafter, as illustrated in FIG. 1B, the titanium silicide film 4 is deposited on the polysilicon film 3 by physical vapor deposition. At this time, the titanium silicide film 4 is in an amorphous state during deposition.
그다음, 도 1c에 도시된 바와 같이, 기판 결과물을 소정 온도에서 수초동안 급속 열처리 공정(rapid thermal process)을 실시하여, 비정질 상태의 티타늄 실리사이드막(4)을 결정질 상태의 티타늄 실리사이드막(5)으로 상변화시킨다.Subsequently, as shown in FIG. 1C, the substrate resultant is subjected to a rapid thermal process at a predetermined temperature for several seconds to convert the titanium silicide film 4 in the amorphous state into the titanium silicide film 5 in the crystalline state. Phase change
이어서, 도 1d에 도시된 바와 같이, 티타늄 실리사이드막(5) 상부에 고집적 소자에서 자기 정합 콘택 형성을 목적으로 사용되는 마스크 산화막(6)으로 산화막 또는 질화막을 증착한다. 이어, 공지의 포토리소그라피 방식을 이용하여 마스크 산화막(6)과 티타늄 실리사이드막(5), 도핑된 폴리실리콘막(3) 및 게이트 절연막(2)을 식각하여, 게이트 전극을 형성한다.Next, as shown in FIG. 1D, an oxide film or a nitride film is deposited on the titanium silicide film 5 with a mask oxide film 6 used for forming a self-matching contact in the highly integrated device. Subsequently, the mask oxide film 6, the titanium silicide film 5, the doped polysilicon film 3, and the gate insulating film 2 are etched using a known photolithography method to form a gate electrode.
다음으로, 도 1e에 도시된 바와 같이, 게이트 전극 형성을위한 식각 공정시, 반도체 기판(1) 표면에 발생된 데미지(damage) 및 식각 잔재물을 제거하고, 게이트 산화막(2)의 신뢰성을 회복하기 위하여, 반도체 기판(1) 결과물을 재산화(re-oxidation)한다. 이러한 재산화 공정은 로(furnace)내에서 소정의 온도 예를들어 800℃ 이상의 온도로 진행되는 것으로, 이 재산화 공정에 의하여 노출된 기판(1) 표면, 게이트 산화막(2), 폴리실리콘막(3) 및 티타늄 실리사이드막(5) 측벽 부분에 산화막(7)이 형성된다.Next, as illustrated in FIG. 1E, during the etching process for forming the gate electrode, to remove damage and etching residues generated on the surface of the semiconductor substrate 1, and to restore the reliability of the gate oxide film 2. In order to do this, the semiconductor substrate 1 is re-oxidized. This reoxidation process is carried out in a furnace at a predetermined temperature, for example, 800 ° C. or higher, and the substrate 1 surface, the gate oxide film 2, and the polysilicon film ( 3) and an oxide film 7 is formed on the sidewall portion of the titanium silicide film 5.
일반적으로 재산화 공정을 로 내부에서 진행할때, 50 내지 100Å 두께의 열산화막을 성장시키는데 거의 50 분에서 165분 정도가 소요된다.In general, when the reoxidation process is carried out in the furnace, it takes about 50 to 165 minutes to grow a thermal oxide film having a thickness of 50 to 100 kPa.
그러나, 상기 티타늄 실리사이드막(5)은 열에 매우 약하여, 상기 정도의 고온 열공정을 장시간 동안 실시하게 되면, 열적 부담(thermal budget)이 커져서, 그 전도 특성을 확보하는데 어려움이 따른다.However, the titanium silicide film 5 is very weak to heat, and when the high temperature thermal process of the above degree is performed for a long time, the thermal budget becomes large, which makes it difficult to secure the conductive property.
또한, 폴리실리콘막이 산화되는 속도와, 티타늄 실리사이드막이 산화되는 속도가 서로 현저하게 다름으로 인하여, 도 1e에 도시된 바와 같이, 폴리실리콘막(3) 측벽에 형성된 산화막(7)의 두께와 티타늄 실리사이드막(5) 측벽에 형성된 산화막(7)의 두께가 서로 상이하다.In addition, since the rate at which the polysilicon film is oxidized and the rate at which the titanium silicide film is significantly different from each other, as illustrated in FIG. 1E, the thickness of the oxide film 7 formed on the sidewall of the polysilicon film 3 and the titanium silicide The thicknesses of the oxide films 7 formed on the sidewalls of the film 5 are different from each other.
특히, 게이트 전극의 전도성을 결정하는 티타늄 실리사이드막(5)은 폴리실리콘막(3) 보다 산화 속도가 매우 빨라서, 도 1e와 같이, 폴리실리콘막보더 다량의 실리콘이 반응에 참여하게 된다. 이로 인하여, 게이트 전극을 구성하는 티타늄 실리사이드막의 선폭이 상당히 감소하여, 게이트 전극의 전도 특성을 확보하기 어렵다.In particular, the titanium silicide film 5 that determines the conductivity of the gate electrode has a much faster oxidation rate than the polysilicon film 3, so that a larger amount of silicon participates in the reaction as shown in FIG. 1E. For this reason, the line width of the titanium silicide film constituting the gate electrode is considerably reduced, and it is difficult to secure the conductive characteristics of the gate electrode.
따라서, 본 발명의 목적은 도핑된 폴리실리콘막과 티타늄 실리사이드막으로 된 게이트 전극 표면을 재산화 할 때, 티타늄 실리사이드막의 전도성을 확보할 수 있는 반도체 소자의 게이트 전극 형성방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of ensuring conductivity of a titanium silicide film when reoxidizing a gate electrode surface made of a doped polysilicon film and a titanium silicide film.
도 1a 내지 도 1e는 종래의 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 각 공정별 단면도.1A to 1E are cross-sectional views of respective processes for explaining a gate electrode forming method of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 각 공정별 단면도.2A to 2D are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 불순물이 도핑된 폴리실리콘막13: polysilicon film doped with impurities
14 : 비정질 상태의 티타늄 실리사이드막(TiSix)14: Titanium silicide film (TiSix) in the amorphous state
15 : 결정질 상태의 티타늄 실리사이드막(TiSi2)15: titanium silicide film (TiSi 2 ) in the crystalline state
16 : 마스크 산화막 17 : 재산화 공정으로 형성되는 산화막16: mask oxide film 17: oxide film formed by reoxidation process
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 실시예에 따르면, 반도체 기판상에 게이트 산화막, 폴리실리콘막 및 티타늄 실리사이드막을 순차적으로 적층하고, 상기 티타늄 실리사이드막 상부에 마스크 산화막을 증착한다. 이어, 마스크 산화막과 티타늄 실리사이드막, 폴리실리콘막 및 게이트 산화막을 소정 형태로 패터닝하여, 게이트 전극을 형성한다음, 상기 게이트 전극이 형성된 기판 결과물을 재산화한다. 이때, 상기 재산화 단계는 상기 재산화 단계는 900 내지 1000℃의 온도에서 습식 급속 열산화 방식으로 진행된다.In order to achieve the above object of the present invention, according to an embodiment of the present invention, a gate oxide film, a polysilicon film and a titanium silicide film are sequentially stacked on a semiconductor substrate, and a mask oxide film is deposited on the titanium silicide film. . Subsequently, the mask oxide film, the titanium silicide film, the polysilicon film, and the gate oxide film are patterned in a predetermined form to form a gate electrode, and then the substrate product on which the gate electrode is formed is reoxidized. At this time, the reoxidation step is the reoxidation step is carried out in a wet rapid thermal oxidation method at a temperature of 900 to 1000 ℃.
또한, 상기 티타늄 실리사이드막은 물리적 증착 방식으로 형성되고, 상기 티타늄 실리사이드막을 증착하는 단계와 상기 마스크 산화막을 증착하는 단계 사이에 상기 티타늄 실리사이드막을 결정화시키는 단계를 추가로 실시한다. 또한, 상기 마스크 산화막은 산화막 또는 질화막을 사용한다.In addition, the titanium silicide film is formed by a physical vapor deposition method, and further performing the step of crystallizing the titanium silicide film between the step of depositing the titanium silicide film and the deposition of the mask oxide film. In addition, an oxide film or a nitride film is used for the said mask oxide film.
본 발명에 의하면, 폴리실리콘막과 티타늄 실리사이드막의 적층막으로 게이트 전극을 형성한다음, 습식 급속 열산화 공정을 진행하여 재산화를 수행한다. 이에따라, 종래의 로에 의한 열산화 공정보다 짧은 시간동안 재산화 공정을 진행할 수 있어, 티타늄 실리사이드막에 인가되는 열적 부담을 최소화할 수 있다. 또한, 습식 방식을 채용함으로써 균일하게 재산화막을 얻을 수 있다. 따라서, 게이트 전극의 전도 특성을 개선할 수 있다.According to the present invention, a gate electrode is formed of a laminated film of a polysilicon film and a titanium silicide film, followed by a wet rapid thermal oxidation process to perform reoxidation. Accordingly, the reoxidation process can be performed for a shorter time than the thermal oxidation process by the conventional furnace, thereby minimizing the thermal burden applied to the titanium silicide film. In addition, by adopting the wet method, it is possible to obtain a reoxidized film uniformly. Therefore, the conduction characteristics of the gate electrode can be improved.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 각 공정별 단면도이다.2A through 2D are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
먼저, 도 2a를 참조하여, 반도체 기판(11) 상부에 게이트 산화막(12)을 공지의 열성장 또는 증착 방식에 의하여 형성한다음, 게이트 산화막(12) 상부에 불순물이 도핑된 폴리실리콘막(13)을 소정 두께로 증착한다. 그후, 도핑된 폴리실리콘막(13) 상부에 티타늄 실리사이드 타겟을 이용한 물리적 증착 방식(physical vapor deposition)으로 티타늄 실리사이드막(14:TiSix,x=2.0∼2.4)을 증착한다. 이때, 증착시 티타늄 실리사이드막(14)은 비정질 상태이다.First, referring to FIG. 2A, a gate oxide film 12 is formed on a semiconductor substrate 11 by a known thermal growth or deposition method, and then a polysilicon film 13 doped with impurities on the gate oxide film 12. ) Is deposited to a predetermined thickness. Thereafter, a titanium silicide film 14 (TiSix, x = 2.0 to 2.4) is deposited on the doped polysilicon film 13 by physical vapor deposition using a titanium silicide target. At this time, the titanium silicide film 14 is in an amorphous state during deposition.
그런다음, 도 2b에 도시된 바와 같이, 기판(11) 결과물을 700 내지 900℃에서 10 내지 60초 동안 급속 열처리 공정(RTA:Rapid Thermal Anneal)을 실시하여, 비정질 상태의 티타늄 실리사이드막(14)을 결정질 상태의 티타늄 실리사이드막(15:TiSi2)으로 상변화시킨다. 이때, 티타늄 실리사이드막(14)은 상기와 같은 증착 방식 대신에 선택적 증착 방식, 즉 티타늄막을 증착하고 열반응에 의하여 실리사이드화하는 방식으로 형성될 수 있다.Then, as shown in FIG. 2B, the resultant substrate 11 is subjected to a rapid thermal annealing (RTA: Rapid Thermal Anneal) at 700 to 900 ° C. for 10 to 60 seconds to form an amorphous titanium silicide layer 14. Phase changes to a titanium silicide film (15: TiSi 2 ) in a crystalline state. In this case, the titanium silicide film 14 may be formed by a selective deposition method instead of the deposition method as described above, that is, by depositing a titanium film and silicided by thermal reaction.
이어서, 도 2c에서와 같이, 티타늄 실리사이드막(15) 상부에 마스크 산화막(16)으로 산화막 또는 질화막을 증착한다. 이어, 공지의 포토리소그라피 방식을 이용하여 마스크 산화막(16)과 티타늄 실리사이드막(15), 도핑된 폴리실리콘막(13) 및 게이트 절연막(12)을 식각하여, 게이트 전극(100)을 형성한다. 이때, 상기 마스크 산화막(16)은 고집적 소자에서 자기 정합 콘택을 형성하기 위하여 형성되는 막이다.Next, as shown in FIG. 2C, an oxide film or a nitride film is deposited on the titanium silicide film 15 with the mask oxide film 16. Subsequently, the mask oxide layer 16, the titanium silicide layer 15, the doped polysilicon layer 13, and the gate insulating layer 12 are etched using a known photolithography method to form the gate electrode 100. In this case, the mask oxide film 16 is a film formed to form a self-aligned contact in a highly integrated device.
다음으로, 상기 게이트 전극(100)을 형성하기 위한 식각 공정시, 게이트 전극(100) 측면 또는 기판(11) 표면에 발생된 데미지 및 식각 잔재물을 제거하고, 게이트 산화막(12)의 신뢰성을 회복하기 위하여, 게이트 전극(100)이 형성된 기판(1) 결과물을 재산화한다. 이때, 본 실시예에서는 게이트 전극(100)의 티타늄 실리사이드막(13)에 가해지는 열적 부담을 최소화하여 전도 특성을 확보하면서 균일하게 재산화막이 형성되도록, 급속 열산화(RTO:Rapid thermal oxidation) 방식으로 재산화한다. 급속 열산화는 900 내지 1000℃에서 수십초 동안, 바람직하게는 재산화막(17)이 20 내지 100Å 정도만큼 성장할때까지 진행되며, 보다 티타늄 실리사이드막에 열적 부담을 덜하기 위하여 습식으로 진행된다. 상기 습식 급속 열산화 공정은 H2O와 O2(또는 H2) 분위기에 진행된다.Next, during the etching process for forming the gate electrode 100, to remove damage and etching residues generated on the side of the gate electrode 100 or the surface of the substrate 11, to restore the reliability of the gate oxide film 12 In order to do this, the substrate 1 on which the gate electrode 100 is formed is recalculated. In this embodiment, a rapid thermal oxidation (RTO) method is used to minimize the thermal burden applied to the titanium silicide layer 13 of the gate electrode 100 so that a reoxidation layer is formed uniformly while ensuring conductive properties. To property. Rapid thermal oxidation proceeds for several tens of seconds at 900 to 1000 DEG C, preferably until the reoxidation film 17 is grown by about 20 to 100 kPa, and is wetted to reduce the thermal burden on the titanium silicide film. The wet rapid thermal oxidation process is carried out in H 2 O and O 2 (or H 2 ) atmosphere.
이때, 일반적으로 건식 산화 공정은 습식 산화보다 상대적으로 속도가 느리므로, 속도를 비슷하게 유지하려면, 습식 산화 공정 보다는 고온(1100℃ 정도)이 요구된다. 그러나, 상기 1100℃ 정도의 고온에서 공정을 진행하게 되면, 아무리 단시간 동안 공정을 진행한다하여도 티타늄 실리사이드막에 열적 부담을 주기 때문에 습식으로 진행하는 편이 열적 부담을 줄이게 된다. 또한, 습식 급속 열산화의 속도는 H2O의 농도와 비례하는데, 어느 정도의 속도를 확보하면서 균일한 재산화막을 형성하기 위하여는 H2O의 농도가 전체 농도의 10 내지 50% 정도가 되도록 함이 바람직하다.At this time, in general, the dry oxidation process is relatively slower than the wet oxidation, so to maintain a similar rate, a higher temperature (about 1100 ℃) than the wet oxidation process is required. However, when the process is carried out at a high temperature of about 1100 ° C., even if the process is carried out for a short time, the heat is applied to the titanium silicide layer to reduce the thermal burden. In addition, the wet rates of the rapid thermal oxidation, the concentration of the H 2 O to form a homogeneous material oxide and, to secure a certain rate of proportional to the concentration of H 2 O about 10 to 50% of the concentration It is preferable to.
이와같이 급속 열산화 방식으로 재산화 공정을 진행하면, 동일한 두께의 재산화막을 형성하는데 매우 짧은 시간이 소요되며, 다음의 표 1에서 이를 자세히 설명하였다. 표 1은 재산화막 두께 및 형성 온도에 따른 소요 시간을 나타낸 표이다.As such, when the reoxidation process is performed in a rapid thermal oxidation method, it takes a very short time to form the reoxidation film of the same thickness, which is described in detail in Table 1 below. Table 1 is a table showing the time required according to the film thickness and the formation temperature.
(표 1)Table 1
상기 표 1에 의하면, 본 발명의 습식 급속 열산화 방식을 채용하는 편이 종래의 건식로 산화 방식을 채용하는 편 보다 약 2 내지 3시간 정도를 단축시키게 된다.According to Table 1, the method of employing the wet rapid thermal oxidation method of the present invention shortens about 2 to 3 hours than the conventional dry method of the oxidation method.
더욱이, 본 발명에 따르면, 짧은 시간동안 열이 가해지는 것이므로, 티타늄 실리사이드막에 열적 부담이 크게 작아진다. 또한, 습식 산화 방식으로 진행되므로, 티타늄 실리사이드막의 측벽에만 비정상적으로 산화되는 현상을 방지할 수 있다.Furthermore, according to the present invention, since heat is applied for a short time, the thermal burden on the titanium silicide film is greatly reduced. In addition, since the oxidation proceeds in a wet oxidation manner, abnormal oxidization of only the sidewall of the titanium silicide layer can be prevented.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 폴리실리콘막과 티타늄 실리사이드막의 적층막으로 게이트 전극을 형성한다음, 습식 급속 열산화 공정을 진행하여 재산화를 수행한다. 이에따라, 종래의 로에 의한 열산화 공정보다 짧은 시간동안 재산화 공정을 진행할 수 있어, 티타늄 실리사이드막에 인가되는 열적 부담을 최소화할 수 있다. 또한, 습식 방식을 채용함으로써 균일하게 재산화막을 얻을 수 있다. 따라서, 게이트 전극의 전도 특성을 개선할 수 있다.As described in detail above, according to the present invention, a gate electrode is formed of a laminated film of a polysilicon film and a titanium silicide film, and then subjected to a wet rapid thermal oxidation process to perform reoxidation. Accordingly, the reoxidation process can be performed for a shorter time than the thermal oxidation process by the conventional furnace, thereby minimizing the thermal burden applied to the titanium silicide film. In addition, by adopting the wet method, it is possible to obtain a reoxidized film uniformly. Therefore, the conduction characteristics of the gate electrode can be improved.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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