KR20000065393A - Chip size package and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A chip size package and a method for manufacturing the same are provided to form an out lead by using a sputtering method without a manufactured lead frame. CONSTITUTION: A chip size package and a method for manufacturing the same comprise a bare chip, a bonding pad(33), a first metal layer(34), a second metal layer(37) and a solder lead layer(38). The bonding pad is formed on a predetermined portion of the bare chip. The first metal layer is formed on the bare chip including the bonding pad except for both edge portions of the bare chip. The second metal layer is connected with both edge portions of the first metal later. The solder lead layer is connected electrically with the second metal layer. The second metal layer and the solder lead layer form a first a second out lead. Any one of the first and the second out leads is projected to an outside.

Description

Chip size package and manufacturing method {CHIP SIZE PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package. In particular, an external protruding lead is attached to a rearranged bonding pad layer to enable vertical mounting of a package even in a surface mounting technology (SMT) process and a narrow mounting area. The present invention relates to a chip size package (hereinafter, abbreviated as "CSP") and a method for manufacturing the same, which are easy to cope with changes in size.

Hereinafter, a chip size package according to the related art will be described with reference to the accompanying drawings.

1 is a structural cross-sectional view of a CSP according to the prior art.

As shown in FIG. 1, a bare chip 11, a bonding pad 12 disposed on the chip 11, a wire bond with the bonding pad 12, and a portion thereof are externally connected. It comprises a lead frame 13 which protrudes and an epoxy molding compound (EMC) 14 which is molded in its entirety including the bare chip 11 except for the protruding portion of the lead frame 13.

The conventional CSP bonds the bonding pads 12 onto the bare chips 11, bonds the bare chips 11 to the lead frames 13, and then the lead frames 13 and the bonding pads 12. Is bonded with a wire (15).

Thereafter, a molding process is performed to expose a part of the lead frame 13 to the outside.

All.

However, the conventional CSP as described above has the following problems.

First, to cope with the chip size change, equipment according to a separate package manufacturing process is required.

Second, a separate interconnection process is required for contact between the chip and the leadframe.

Third, the height of the lead frame is low, the adhesion reliability with the solder ball is low.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a chip size package and a method of manufacturing the same, which are easy to respond to a change in size and have excellent package reliability.

1 is a structural cross-sectional view of a chip size package according to the prior art

2 is a cross-sectional view of a chip size package of the present invention;

3A to 3G are cross-sectional views illustrating a method of manufacturing a chip size package of the present invention.

Explanation of symbols for main parts of the drawings

31a, 31b: Bare Chip 32: Glass Film

33: bonding pad 34: first metal layer

35,39 second photoresist 36 sacrificial film

37: second metal layer 38: solder lead layer

40, 40a: 1st, 2nd outlead 41: coating layer

The chip size package of the present invention for achieving the above object is a chip size package, the bonding pad except for the bare chip, a bonding pad formed on a predetermined portion on the bare chip, and both edge portions on the bare chip, A first metal layer formed on the bare chip, and a second metal layer is electrically connected to both edge portions of the first metal layer, and a solder lead layer is electrically connected to the second metal layer, thereby forming the second metal. And a first and second outlead formed of a layer and the solder lead layer, wherein at least one of the outleads protrudes outwardly from the bare chip.

In the chip size package manufacturing method of the present invention, a glass film is adhered to a back surface of a wafer, and a bonding pad is selectively formed on an upper surface of the wafer, and the wafer is sawed to have a one-to-one correspondence with the bonding pad. Forming a first metal layer on the bare chip including the bonding pads except the edges on both sides of the bare chip, and exposing both edge portions on the first metal layer; Forming a photoresist pattern on the first metal layer, and filling a sacrificial layer between and between the bare chip and the bare chip; forming a second metal layer on the entire surface including the photoresist pattern; A process of forming a solder lead layer on the layer, and an etching process using the photoresist pattern as a mask And selectively removing the solder lead layer and the second metal layer to form first and second out leads formed of the solder lead layer and the second metal layer, wherein at least one of the out leads is formed. The solder lead layer and the second metal may be removed so that a part thereof protrudes outward from the bare chip.

Hereinafter, a CSP of the present invention and a method of manufacturing the same will be described with reference to the accompanying drawings.

2 is a structural cross-sectional view of a CSP according to the present invention.

As shown in FIG. 2, in a chip size package, a bare chip 31a, a bonding pad 33 formed at a predetermined portion on the bare chip 31a, and both edge portions on the bare chip 31a are formed. Except for the first metal layer 34 formed to be electrically connected to the bonding pad 33 and the coating layer formed on the front surface including the bare chip 31a except for both edge portions of the first metal layer 34 ( 41 and a second metal layer 37 electrically connected to both edge portions of the first metal layer 34, and a solder lead layer 38 electrically connected thereon.

In this case, the second metal layer 37 and the solder lead layer 38 serve as an outlead for signal transmission between the bare chip 31a and the outside.

The material of the coating layer 41 uses PIQ (Polyimide Isoindro Quindzoline).

Thus, the manufacturing method of the chip size package of this invention comprised is demonstrated with reference to FIGS. 3A-3K.

3A to 3I are process cross-sectional views for explaining the CSP manufacturing method of the present invention.

As shown in FIG. 3A, after the glass film 32 is adhered to the rear surface of the wafer 31, the bonding pad 33 is formed on the upper surface of the wafer 31 at a predetermined interval.

In this case, the bonding pads 33 are formed one by one so as to correspond to one bare chip which is separated by sawing 31.

Subsequently, as illustrated in FIG. 3B, a sawing process of cutting the wafer 31 at predetermined intervals is performed to form bare chips 31a and 31b separated from each other.

A first metal layer 34 is formed on portions of the bare chips 31a and 31b except for both edge portions and the bonding pads 33.

Here, in the process of forming the first metal layer 34, the first metal layer 34 is formed on the entire surface including the bare chips 31a and 31b and the bonding pad 33, and then the first photoresist ( (Not shown) and the first photoresist is exposed to expose the edges between the bare chip 31a and the bare chip 31b and both edge portions of the bare chips 31a and 31b by using an application process and an exposure and development process. Patterning, and selectively etching the first metal layer 34 using the patterned first photoresist as a mask.

As shown in FIG. 3C, the second photoresist 35 is coated on the first metal layer 34, and the second photoresist 35 is patterned by an exposure and development process.

Thereafter, a sacrificial layer 36 is formed between the bare chip 31a and the bare chip 31b and between the second photoresist 35 thereon.

The sacrificial film 36 is removed in a subsequent process by supporting the second metal layer and the solder lead layer to be later formed so as to be flush with the tops of the bare chips 31a and 31b.

As the material of the sacrificial film 36, a material that is easily removed in a later process may be used. In view of this, a material including a photoresist and an insulating film system may be used, and the thickness of the second photoresist 35 may be adjusted. It is possible to adjust the height of a said 2nd metal layer and a solder lead layer by this.

On the other hand, the second photoresist is formed such that the bare chip 31a and the bare chip 31b are buried to a sufficient height in the process of patterning the second photoresist 35 without separately forming the sacrificial film 36. It is possible to apply the process of patterning (35).

As such, after the sacrificial layer 36 is formed, the second metal layer 37 is formed on the entire surface including the exposed first metal layer 34 as illustrated in FIG. 3D.

Thereafter, the solder lead layer 38 is formed on the second metal layer 37 by using an electroplating or sputtering process.

Here, the second metal layer 37 and the solder lead layer 38 later serve as signal transmission between the bare chips 31a and 31b and the outside, and are patterned in an outlead form.

3E, a third photoresist 39 is applied onto the solder lead layer 38.

After the third photoresist 39 is patterned by using an exposure and development process, an etching process using the patterned third photoresist 39 as a mask is performed. The second photoresist is formed on the first metal layer 34. The solder lead layer 38 and the second metal layer 37 are selectively removed to expose 35.

Accordingly, the first outlead 40 and the second outlead 40a each including the second metal layer 37 and the solder lead layer 38 and electrically connected to both upper surfaces of the first metal layer 34, respectively. Is formed.

Here, at the time of etching the solder lead layer 38 and the second metal layer 37, at least one of the first and second outleads 40 and 40a may be partially formed than the bare chips 31a and 31b. Etch to protrude to the outside.

As such, when the outlead is formed to protrude to the outside, mounting is possible perpendicular to the board.

Subsequently, as shown in FIG. 3F, after the third photoresist 39 and the second photoresist 35 and the sacrificial layer 36 between the bare chip 31a and the bare chip 31b are removed, When the exposed bare chips 31a and 31b and the upper part of the first metal layer 34 are coated with PIQ (Polyimide Isoindro Quindzoline) to form a coating layer 41, the chip size package manufacturing process according to the present invention is completed. .

As described above, the chip size package of the present invention and the manufacturing method thereof have the following effects.

First, it is easy to apply the fine pitch because the outlead is formed using the sputtering method applied in the FAB (FABRICATION) process without using the already produced lead frame.

Second, since it is a lead type, board mounting is easy.

Third, some of the leads are projected outward so that they can be mounted perpendicular to the board.

Fourth, since the height of the lead can be adjusted, the bonding force with the solder lead can be improved.

Claims (7)

In a chip size package, With bare chips, Bonding pads formed on predetermined portions on the bare chip; A first metal layer formed on the bare chip including the bonding pads, except for both edge portions of the bare chip; Second and second metal layers are electrically connected to both edge portions of the first metal layer, and a solder lead layer is electrically connected to the second metal layer, thereby forming the first and second solder layers. Including outleads, And at least one of the outleads protrudes outwardly relative to the bare chip. The chip size package of claim 1, further comprising a coating layer on an exposed portion of the first metal layer including an upper portion of the bare chip. Attaching a glass film to the back surface of the wafer, and optionally forming a bonding pad on the top surface of the wafer, Sawing the wafer so as to correspond one-to-one with the bonding pad and separating the wafer into bare chips; Forming a first metal layer on the bare chip, including the bonding pads excluding both edges of the bare chip; Forming a photoresist pattern on the first metal layer to expose both edge portions of the first metal layer, and filling a sacrificial layer between and between the bare chip and the bare chip; Forming a second metal layer on the entire surface including the photoresist pattern and forming a solder lead layer on the second metal layer; An etching process using the photoresist pattern as a mask to selectively remove the solder lead layer and the second metal layer to form first and second out leads formed of the solder lead layer and the second metal layer , And at least one of the outleads removes the solder lead layer and the second metal so that a portion thereof protrudes outwardly from the bare chip. The method of claim 3, further comprising removing the photoresist pattern and the sacrificial layer after forming the first and second outleads. The method of claim 4, wherein the sacrificial layer is made of an easily removable material. The method of claim 3, wherein the solder lead layer is formed using an electroplating or sputtering method. 5. The method of claim 4, further comprising coating the exposed surfaces of the bare chip and the first metal layer after removing the photoresist pattern and the sacrificial layer. 6.