KR20000065389A - Enable timing controller for sense amplifier - Google Patents

Abstract

PURPOSE: An apparatus for controlling a sense amp enable timing is provided to adjust set/reset delay timing with an output assembling a signal of fuse cutting. CONSTITUTION: An apparatus for controlling a sense amp enable timing includes: a predecoder(20) outputting a sense amp control signal; set/reset fuse parts(40a,40b) generating a set/reset fuse assembly signal selectively by a user definition; a programmable delay part(30) which outputs a set/reset delay timing signal by being selected by an output for a first delay block(31a) and a second delay block(31b) to decode the set/reset fuse assembly signal by receiving the sense amp control signal; and a sense amp driving part(50) driving the sense amp by the set/reset delay timing signal. According to the apparatus, the refresh characteristics can be improved and optimized sense amp set/reset timing can be selected because the apparatus can vary the set/reset delay-timing signal of the sense amp.

Description

Sense amplifier enable timing controller {ENABLE TIMING CONTROLLER FOR SENSE AMPLIFIER}

The present invention relates to a sense amplifier, and more particularly, to a sense amplifier enable timing controller suitable for selectively adjusting the set / reset delay timing for enabling the sense amplifier.

In general, a row address signal is input so that the X_decoder decodes the X_address and selects and activates a word line corresponding to the row address.

Then, when the word line is driven, a series of cells are connected to the bit line to share charges, causing a potential change in the bit line.

Subsequently, a potential change that can be sensed by the bit line sense amplifier occurs, and a sense amplifier enable (SAE) signal is generated after a predetermined time delay to drive the bit line sense amplifier.

In this case, since the data of the cell is transmitted to the bit line, the sense amplifier must be activated. For this purpose, the sense amplifier enable signal is generated.

Hereinafter, a sense amplifier enable timing control apparatus according to the related art will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a conventional sense amplifier enable timing control device. An X_predecoder 10 for outputting a sense amplifier control signal and a set / reset delay timing of a sense amplifier in response to the control signal are shown in FIG. RC delay unit 13 for adjusting a signal, a sense amplifier driver 14 for outputting a sense amplifier enable signal for driving a sense amplifier based on the delay timing signal, and an output of the X_predecoder An X_decoder 11 and a word line driver 12 for activating the word line.

Referring to the operation of the conventional sense amplifier enable timing control device configured as described above is as follows.

First, the row address (Row_addr) signal is pre-decoded in the X_predecoder 10, and then the X_decoder 11 decodes the X_ address signal, and the decoded X_ address drives the word line driver 12. The word line corresponding to the row address is enabled.

Then, when the word line is enabled, a series of cells are connected to the bit line to share charges, and a potential variation that can be detected by the bit line sense amplifier occurs. Then, the X_predecoder 10 performs a bit line sense amplifier. A sense amplifier control signal for driving (not shown) is sent out.

As shown in FIG. 2, the sense amplifier control signal SA_ctrl is connected in parallel with a first input X, a resistor R, and a capacitor C, in which a delay timing is not generated at the two input NAND gate 15. Set delay delayed by a predetermined time delay with respect to the first input (X) and delayed by a logical combination of the first and second inputs (X, Y). Generate a timing signal Z.

Then, the set delay timing signal Z is input to the sense amplifier driver 14, and the sense amplifier driver 15 outputs a sense amplifier enable signal SAE for enabling the sense amplifier.

The prior art sense amplifier enable timing control apparatus uses a resistor (R) and a capacitor (C) delay model to determine a fixed set / reset delay timing signal, and thus, a set / reset delay timing signal of an appropriate sense amplifier. It is difficult to occur.

Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a sense amplifier enable timing control device capable of selectively adjusting the set / reset delay timing as an output combining a signal in which a fuse is cut. .

1 is a block diagram showing a conventional sense amplifier enable timing control device

2 is a circuit diagram showing a conventional RC delay unit;

3 is a prior art sense amplifier enable timing diagram.

4 is a block diagram showing a sense amplifier enable timing control apparatus according to the present invention;

5 is a block diagram illustrating a programmable delay unit according to the present invention.

6 is a sense amplifier enable timing diagram according to the present invention.

* Description of the symbols for the main parts of the drawings *

30: programmable delay unit 31a, 31b: first, second delay block

32a, 32b: first set / reset delay unit 33a, 33b: second set / reset delay unit

34a, 34b: set / reset switching unit 35: NAND gate

36a, 36b: set / reset decoder 40a, 40b: set / reset fuse

According to an aspect of the present invention, a sense amplifier enable timing controller includes an X_predecoder for receiving a row address signal and outputting a sense amplifier control signal, and optionally a set / reset fuse combination signal by user definition. A set / reset fuse unit for generating a signal and a sense amplifier control signal and a first delay block and a second delay block are selected as outputs of decoding the set / reset fuse combination signal to adjust the set / reset delay timing signal. And a sense amplifier driver for driving the sense amplifier by the set / reset delay timing signal.

Hereinafter, the sense amplifier enable timing control apparatus according to the present invention will be described with reference to the accompanying drawings.

4 is a block diagram illustrating a sense amplifier enable timing control apparatus according to the present invention, and FIG. 5 is a block diagram illustrating a programmable delay unit according to the present invention.

6 is a sense amplifier enable timing diagram according to the present invention.

That is, the sense amplifier enable timing control apparatus according to the present invention receives the row address (Row_Addr) signal and outputs the sense amplifier control signal SA_ctrl and the X_predecoder 20, and optionally set / reset by user definition. The set / reset fuse receives a fuse unit 40 that generates a fuse combination signal, and a first delay block 31a and a second delay block 31b that receive a sense amplifier control signal of the X_predecoder 20. A programmable delay unit 30 that is selected as an output of decoding the combined signal and adjusts the set / reset delay timing signal, and a sense amplifier enable signal SAE for driving the sense amplifier by the set / reset delay timing signal. It is composed of the sense amplifier driver 50 generated.

Here, the fuse part 40 includes a set fuse part 40a and a reset fuse part 40b.

The first delay block 31a may include a first set delay unit 32a for generating a first set delay timing signal and a second set for generating a second set delay timing signal in addition to the first set delay timing signal. The delay unit 33a and the set switching unit 34a for inputting the second set delay timing signal to the NAND gate 35 are included.

In addition, the first delay block 31a further includes a set decoder 36a for decoding the set fuse combination signal of the set fuse unit 40a and selectively connecting the switches of the set switching unit 34a. .

The second delay block 31b may include a first reset delay unit 32b for generating a first reset delay timing signal and a second reset for generating a second reset delay timing signal in addition to the first reset delay timing signal. A delay unit 33b and a reset switching unit 34b for inputting the second reset delay timing signal to the NAND gate 35.

In addition, the second delay block 31b further includes a reset decoder 36b for decoding the reset fuse combination signal of the reset fuse unit 40b and selectively connecting the switch of the reset switching unit 34b. .

Referring to the operation of the sense amplifier enable timing control apparatus according to the present invention configured as described above is as follows.

First, the row address signal Row_addr is predecoded by the X_predecoder 20, and then the X_decoder 60 decodes the X_ address signal, and the decoded X_ address drives the word line driver 70. A word line enable signal is output to activate a word line corresponding to the row address.

Then, when the word line is activated, a series of cells are connected to the bit line to share charges, thereby causing a potential variation that the bit line sense amplifier can detect, and then driving the bit line sense amplifier (not shown). The X_predecoder 20 emits a sense amplifier control signal SA_ctrl.

Subsequently, the sense amplifier control signal output from the X_predecoder 20 is always delayed for a predetermined time by the first set / reset delay units 32a and 32b, and the first delayed signal is the second set / reset delay unit. Delay timing is optionally adjusted at 33a and 33b.

Based on the refresh test of the W-gum and P-gum, the default fuse settings were cut with a laser to adjust the appropriate sense amplifier set / reset delay timings.

First, the sense amplifier set delay timing will be described. Even if the sense amplifier control signal rises from low to high for the set timing, the first set delay unit 32a delays a predetermined time and then the second set delay unit. A high signal is input to 33a.

If the fuse fn of the set fuse part 40a is not cut at all, an initial set delay timing signal A is generated.

Subsequently, the set decoder 36a which cuts the fuse f1 and receives the input of the remaining uncut fuse decodes the uncut n-1 fuses.

Subsequently, when the switch s1 is connected to the output terminal of the set decoder 36a, the 1 ns set delay timing signal generated by the second set delay unit and the signal (logical value 1) of the second delay block 31b are NAND gates 35. ) Is logically combined to drive the sense amplifier driver 50.

In this case, when the switch s1 is selected, the set delay timing signal, which maintains the first delay state, is further delayed by 1 ns and then transitions from low to high, so that the high signal, which is delayed by 1 ns, further drives the sense amplifier driver 50. Set.

As such, if the fuse is not cut at all, an initial set delay timing signal A is generated and the fuse fn is cut during the high signal of the sense amplifier control signal, and the switch is decoded by decoding the remaining uncut n-1 fuses. By connecting (Sn) to select the N ns delay timing signal, the set delay timing signal is adjusted from the initial set delay timing signal A to the front and rear (B).

Next, the reset delay timing will be described. When the sense amplifier control signal transitions from high to low, the first delay delay unit 32b may be delayed for a predetermined time and the low signal may be input to the second reset delay unit 33b.

Subsequently, if the reset fuse fn 'is not cut at all, a reset initial delay timing signal C is generated, and the reset decoder 36b which cuts the fuse f1' and receives the input of the remaining uncut fuse receives the uncut fuse. (n-1) 'fuses are combined and decoded.

Subsequently, the output of the reset decoder 36b is selectively connected to the switch s1 'so that a 1 ns reset delay timing signal and a delay timing signal of the first delay block 31a are input to the NAND gate 35.

Here, the reset delay timing signal, which maintained the first delay state, transitions from high to low after being delayed by 1 ns more.

The low signal further delayed by 1 ns stops the sense amplifier driver 40.

As described above, when the sense amplifier control signal transitions to a low signal, if the reset fuse is not cut at all, an initial reset delay timing signal C is generated, and the fuse fn 'is cut and the remaining uncut (n−) is cut. 1) A switch Sn 'is connected to the decoding of the' n 'fuses so that the Nns delay timing signal is selected to adjust the reset delay timing signal before and after the initial reset delay timing signal C (D).

The sense amplifier enable timing controller according to the present invention described above can selectively change the set / reset delay timing signal of the sense amplifier, thereby improving refresh characteristics and selecting an optimized sense amplifier set / reset timing. have.

Claims (6)

A predecoder for outputting a sense amplifier control signal; A set / reset fuse unit for selectively generating a set / reset fuse combination signal by user definition; A programmable delay unit which receives the sense amplifier control signal and selects a first delay block and a second delay block as outputs of decoding the set / reset fuse combination signal to adjust a set / reset delay timing signal; And a sense amplifier driver configured to drive the sense amplifier by the set / reset delay timing signal. The method of claim 1, The first delay block may include a first set delay unit generating a first set delay timing signal; A second set delay unit generating a second set delay timing signal in addition to the first set delay timing signal; And a set switching unit for transmitting the second set delay timing signal to the sense amplifier driver. The method of claim 1, The second delay block may include: a first reset delay unit generating a first reset delay timing signal; A second reset delay unit generating a second reset delay timing signal in addition to the first reset delay timing signal; And a reset switching unit configured to transfer the second reset delay timing signal to the sense amplifier driver. The method of claim 2, And the first delay block further comprises a set decoder for decoding a set fuse combination signal of the fuse unit and selectively connecting a switch of the set switching unit. The method of claim 3, wherein And the second delay block further comprises a reset decoder for decoding a reset fuse combination signal of the fuse unit and selectively connecting a switch of the reset switching unit. The method of claim 1, And said programmable delay unit outputs an initial set / reset delay timing signal according to a decoding signal in which no fuse is cut at all.