KR100596774B1 - A method of controlling the timing to over drive sense amplifiers of a memory device - Google Patents

Abstract

The present invention relates to a method for adjusting an overdriving timing of a sense amplifier of a memory device, and in particular, when the sense amplifier of a memory device is enabled, it is possible to adjust the rise time of the driving voltage applied to the sense amplifier, thereby stably operating the memory device. An overdriving timing adjustment method of a sense amplifier of a memory device is described.

In the method for adjusting an overdriving timing of a sense amplifier of a memory device according to an exemplary embodiment of the present invention, when a sense amplifier enable signal is applied, a path unit having a plurality of delay times may be used to adjust a timing for raising a driving voltage of the sense amplifier. A predetermined control signal is applied to a delay unit including the delay unit to select one or two or more of the plurality of path units to determine a predetermined delay time, and a time point for increasing the driving voltage of the sense amplifier by using the delay time. Adjust

The present invention uses a test mode signal to control the time of applying the high voltage to the sense amplifier, that is, by adjusting the delay time of the delay unit by software, it is more efficient than the conventional case when applying the driving voltage of the sense amplifier Can be adjusted.

Description

A method of controlling the timing to over drive sense amplifiers of a memory device}

1 is a conventional circuit diagram of sensing an enable time of a sense amplifier and raising a driving voltage of the sense amplifier.

2 is an example of a delay unit illustrated in FIG. 1.

3 is a timing diagram of signals of the circuit shown in FIG. 1;

4 is a circuit diagram for controlling an overdriving timing point of a sense amplifier of a memory device according to the present invention.

5 is an example of a delay unit according to the present invention.

6 is an example of a circuit for generating an input signal of the delay unit circuit of FIG.

7 is a timing diagram of signals associated with FIGS. 4 to 6;

The present invention relates to a method and a device for adjusting an overdriving timing of a sense amplifier of a memory device. In particular, when the sense amplifier of a memory device is enabled, it is possible to adjust a rise time of a driving voltage applied to the sense amplifier. A method and apparatus for adjusting an overdriving timing of a sense amplifier of a memory device to enable stable operation.

In general, a sense amplifier of a memory device is positioned between a bit line connected to a memory cell storing data and senses and amplifies a voltage on the bit line during read operation, write operation, or precharge operation. It transfers to a line or stores in a memory cell. Such sense amplifiers are typically driven by being connected between the core voltage (set to the same voltage level as the high voltage stored in the memory cell data) and the ground voltage.

However, when the sense amplifier is enabled to perform the above operation, since a large number of sense amplifiers operate at the same time, the consumption of the driving voltage (core voltage) increases rapidly, which causes the driving voltage to shake. In order to prevent this, in general, when a sense amplifier is enabled, a method of detecting a point in time and applying a voltage Vdd higher than the core voltage as a driving voltage of the sense amplifier in advance is used.

Hereinafter, the prior art will be described with reference to the drawings.

1 illustrates a conventional circuit that senses an enable time of a sense amplifier and raises a drive voltage of the sense amplifier.

As shown in FIG. 1, the circuit of FIG. 1 receives a signal output from the delay unit 10 and the delay unit 10 that receive and delay a sense amplifier over driving (saovd) generated when the sense amplifier is enabled. The NAND gate 14 is provided. The NAND gate 14 receives a delay signal saovd_dly and another delay signal saovdb which delays the delay signal through the inverter chains 11, 12, 13, and outputs the signal saovb of the NAND gate 14. ) Turns on the PMOS transistor 15 to apply a high voltage Vdd to the sense amplifier (as noted, the drain of the PMOS transistor 15 is connected to the drive residual line of the sense amplifier).

2 is an example of the delay unit 10 shown in FIG. 1.

As shown, the conventional delay unit 10 delays the input signal saovd using RC means, and the delay time is adjusted by cutting the fuse.

3 is a timing diagram of signals of the circuit shown in FIG.

As can be seen from the figure, in the conventional case, the timing of applying the high voltage to the sense amplifier by turning on the PMOS transistor 15 is determined by the delay unit shown in FIG. There was a need to change the circuit, which was a problem that requires a lot of physical and cost.

The present invention has been proposed to solve the above-described problem, and an object of the present invention is to provide a method for controlling a software point of time when a high voltage is applied to a sense amplifier.

The overdriving timing adjustment method of the sense amplifier of the memory device according to the present invention includes a code signal input for adjusting a delay time, a test mode enter signal for entering a test mode, and the test mode escape signal for leaving the test mode. Receiving step; If the test mode enter signal is not activated, an input signal of a first state is generated, and if the code signal is inactivated while the test mode enter signal is activated, an input signal of a second state is generated, and the test mode enter is generated. Generating an input signal of a third state if both a signal and the code signal are activated; And a delay time corresponding to the number of paths in which at least one path including the first path is selected from among the first path, the second path, and the third path connected in series as the input signal and the enable signal. Outputting said delay signal having;
The overdriving timing adjustment device of the sense amplifier of the memory device according to the present invention includes a code signal input for adjusting a delay time, a test mode enter signal for entering a test mode, and an exit of the test mode for exiting a test mode. When the test mode enter signal is not activated, the input signal of the first state is generated, and if the code signal is deactivated while the test mode enter signal is activated, the input signal of the second state is generated. A first circuit configured to generate an input signal of a third state when both the test mode enter signal and the code signal are activated; And each of the paths is connected in series while the input signal and the enable signal provided by the first circuit are respectively input to the first path, the second path, and the third path, thereby providing at least one or more signals in the first path. And a delay unit including a second circuit for outputting the enable signal having a delay time determined through the path as the delay signal.

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(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit for controlling an overdriving timing of a sense amplifier of a memory device according to the present invention.

As shown in FIG. 4, the circuit of FIG. And a delay unit 40 for receiving and delaying the signal, and a NAND gate 44 for receiving a signal output from the delay unit 40. The NAND gate 44 receives a delay signal saovd_dly and another delay signal saovdb which delays the delay signal through the inverter chains 41, 42, and 43, and outputs the signal saovb of the NAND gate 44. ) Turns on the PMOS transistor 45 to apply a high voltage (Vdd) to the sense amplifier.

Since the basic operation of the circuit shown in FIG. 4 is the same as in the case of FIG. 1, further description is omitted, and since the feature of the present invention is to control the delay time of the delay unit 40 in software, FIG. This is described with reference to 6.

5 is an example of a delay unit according to the present invention. For reference, the signals time_over <0> and time_over <1> used in FIG. 5 are described in FIG. 6.

As shown in FIG. 5, the delay unit includes a NOR gate 50, a first path unit, a second path unit, and a third path unit.

The NOR gate 50 receives signals time_over <0> and time_over <1> and its output signal is applied to the first path portion.

The first path portion is composed of NAND gates 57 and 58, and the NAND gate 57 receives an output signal and a signal saovd of the NOR gate 50, and the NAND gate 58 is formed of the NAND gate 57. An output signal and an output signal of the second path portion are received. The output signal saovd_dly of the first path portion is the same as the signal shown in FIG.                     

 The second path portion is composed of NAND gates 54 and 55 and an inverter 56. The NAND gate 54 receives a signal time_over <0> and a signal saovd, and the NAND gate 55 is a NAND gate. An output signal of 54 and an output signal of the third path portion are received. The inverter 56 receives and inverts the output signal of the NAND gate 55, and the output signal of the inverter 56 is applied to the first path portion as the output of the second path portion.

The third path portion includes NAND gates 51 and 52 and an inverter 53. The NAND gate 51 receives a signal time_over <1> and a signal saovd, and the NAND gate 52 is a NAND gate. An output signal of 51 and a high level voltage are received. The inverter 53 receives and inverts the output signal of the NAND gate 52, and the output signal of the inverter 53 is applied to the second path portion as the output of the third path portion.

FIG. 6 is an example of a circuit for generating input signals time_over <0> and time_over <1> of the delay unit circuit of FIG. 5.

The circuit shown in FIG. 6 receives a code signal code, a test mode enter signal tm_enter, and a test mode exit signal tm_exit, and outputs signals time_over <0> and time_over <1>. Here, the code signal is any signal selectable to a high level or a low level. In addition, the test mode is a test mode for setting a delay time, the test mode enter signal tm_enter indicates entering the test mode, and the test mode exit signal tm_exit literally indicates leaving the test mode.

In operation (in Fig. 6), in the normal operation mode (the test mode is not executed), the signals time_over <0> and time_over <1> are all at the low level. The delay in the second and third path portions that are made is not caused. Therefore, the delay time is determined only by the first path portion.

Next, when a pulse signal indicating entering the test mode is generated, that is, when the test mode enter signal tm_enter becomes high level, when the low level code signal code is applied, the output signal tm_over <0> becomes high. When the high level code signal code is applied, the output signal tm_over <1> becomes a high level.

Next, when the signal tm_over <0> is high level, the delay time of the delay unit of FIG. 5 is determined by the second path unit and the first path unit, and when the signal tm_over <1> is high level, The delay time of the delay unit in Fig. 5 is determined by the third, second and first path portions.

Accordingly, it can be seen that the delay time of the delay unit shown in FIG. 4 can be selected by selecting the voltage levels of the signals tm_over <0> and tm_over <1>.

7 is a timing diagram of signals associated with FIGS. 4 to 6.

As shown, when the test mog enter signal tm_enter is applied while the code signal code is at the low level, the signal tm_over <0> is at the high level. Thus, the first and second path portions of the delay portion shown in FIG. 5 operate. As a result, it will be appreciated that the signal saovb applied to the PMOS transistor 45 shown in FIG. 4 is delayed for a predetermined time (delay1 in FIG. 7) than when the second path portion does not operate. That is, the delay time delay 1 is substantially the same as the delay time of the second path portion shown in FIG. 5. For reference, in FIG. 7, the dotted line in the waveform diagram of the signal saovb shows a case where there is no delay, that is, only a delay caused by the first delay unit of FIG. 5 is caused.

Next, when the test mock enter signal tm_enter is applied while the code signal code is at the low level, the signal tm_over <1> is at the high level. Thus, the first, second and third path portions of the delay portion shown in FIG. 5 operate. As a result, it will be understood that the signal saovb applied to the PMOS transistor 45 shown in FIG. 4 is delayed by a predetermined time (delay2 in FIG. 7) than when the second and third path parts do not operate. That is, the delay time delay2 is substantially the same as the delay time of the second and third path portions shown in FIG. 5. For reference, in FIG. 7, the dotted line in the waveform diagram of the signal saovb shows a state in which there is no delay, that is, only a delay caused by the first delay unit of FIG. 5 is caused.

As can be seen from the above, the present invention is more efficient than the conventional case by using the test mode signal, that is, to control the delay time of the delay unit by software in order to control the point of time when the high voltage is applied to the sense amplifier. The timing of applying the driving voltage of the sense amplifier can be adjusted.

Claims (3)

delete In the method of adjusting the overdriving timing of the sense amplifier of the memory device for adjusting the timing for increasing the driving voltage of the sense amplifier by using a delay signal, Receiving a code signal input for adjusting a delay time, a test mode enter signal for entering a test mode, and the test mode exit signal for leaving the test mode; If the test mode enter signal is not activated, an input signal of a first state is generated, and if the code signal is inactivated while the test mode enter signal is activated, an input signal of a second state is generated, and the test mode enter is generated. Generating an input signal of a third state if both a signal and the code signal are activated; And At least one path including the first path among the first path, the second path, and the third path connected in series as the input signal and the enable signal is selected to have a delay time corresponding to the number of included paths. Outputting the delay signal; adjusting the overdriving timing of the sense amplifier of the memory device. In the over-driving timing adjustment apparatus of the sense amplifier of the memory device for adjusting the timing for raising the driving voltage of the sense amplifier by using a delay signal, A code signal input for adjusting the delay time, a test mode enter signal for entering a test mode, and the test mode exit signal for leaving the test mode are provided, and the first state is input when the test mode enter signal is not activated. Generating a signal, and generating an input signal in a second state when the code signal is in an inactive state while the test mode enter signal is in an activated state; and in a third state when both the test mode enter signal and the code signal are in an activated state A first circuit for generating an input signal; And Each of these paths is connected in series while the input signal and the enable signal provided by the first circuit are respectively input to the first path, the second path, and the third path, thereby providing at least one path in the first path. And a second circuit configured to output the enable signal having a delay time determined therethrough as the delayed signal. The delay unit includes a delay unit.

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