KR101022667B1 - Semiconductor memory device with structure of over-driving - Google Patents

Abstract

The present invention relates to a semiconductor memory device capable of controlling and testing an overdriving driving time without limiting a physical implementation. The present invention provides a first memory for synchronizing an overdriving start signal with a clock applied in a test mode. First pulse signal generating means for outputting a pulse signal; Second pulse signal generating means for outputting the overdriving starting signal as a second pulse signal having an activation pulse width adjusted according to the increase / delay delay control signal and the attenuation delay delay control signal; Selecting means for selectively outputting the first and second pulse signals as an overdriving signal in response to a test-control signal; A bit line sense amplifier block for sensing and amplifying a voltage difference between the bit line pairs of the memory cell array block; A first driver for driving the first power line of the bit line sense amplifier block to a voltage applied to a core voltage supply terminal in response to a first driving control signal; An overdriver for driving the supply terminal of the core voltage to an external voltage higher than the core voltage in response to the overdriving signal; And a second driver for driving the second power line of the bit line sense amplifier block to the first power voltage in response to a second driving control signal.

Overdriving Time, Clock, Test, Flip-Flop, Divider

Description

Semiconductor memory device with overdriving structure {SEMICONDUCTOR MEMORY DEVICE WITH STRUCTURE OF OVER-DRIVING}

1 is a block diagram of a semiconductor memory device having a general overdriving structure.

2 is an internal circuit diagram of a delay increase controller of FIG. 1.

3 is a view showing a change in activation period of an overdriving signal in a semiconductor memory device according to the prior art;

4 is a block diagram illustrating a semiconductor memory device in accordance with a first embodiment of the present invention.

5 is a diagram illustrating a change in activation width of an overdriving signal according to a change in a clock cycle applied in a test mode.

6 is a block diagram illustrating a semiconductor memory device in accordance with a second embodiment of the present invention.

FIG. 7 is a view illustrating a change in activation period of an overdry signal according to the test mode of the semiconductor memory device shown in FIG. 6;

* Explanation of symbols for the main parts of the drawings

100: first pulse signal generation unit

200: second pulse signal generation unit

300: selection unit

400: bit line sense amplifier block

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and more particularly, to a semiconductor memory device for testing an appropriate overdriving time.

As low driving voltages are used to reduce the power of memory devices, there have been various technical supplements for assisting the operation of the sensing amplifier in memory devices including DRAM, and one of them is the overdriving structure of the sensing amplifier.

Typically, data of a plurality of memory cells connected to a word line activated by a row address is transferred to a bit line, and the bit line sense amplifier senses and amplifies the voltage difference between the pair of bit lines.

During the above process, since the thousands of bit line sense amplifiers start to operate at the same time, the bit line sense amplifier driving time is determined depending on whether it is possible to supply a sufficient amount of current to drive it. However, it is difficult to supply a sufficient amount of current at a moment due to the decrease in the operating voltage according to the trend of lowering the power consumption of the memory device. To solve this problem, a voltage higher than the normal voltage (typically, an internal core voltage) is momentarily applied to the power line rto of the bit line sense amplifier at the initial stage of operation of the bit line sense amplifier (just after the charge sharing between the cell and the bit line). The bit-line sense amplifiers overdriving structure has been adopted.

1 is a block diagram illustrating a semiconductor memory device having an overdriving structure according to the related art.

Referring to FIG. 1, a semiconductor memory device includes a bit line detection amplifier block 40 for sensing and amplifying a voltage difference between bit line pairs of a memory cell array block, and a bit line detection amplifier block in response to a driving control signal SAP. The driver PM2 for driving the power line RTO of the power supply 40 to the voltage applied to the core voltage terminal VCORE and the supply terminal of the core voltage terminal in response to the overdriving signal SAOVB are connected to the internal core voltage VCORE. To generate an overdriving signal SAOVB in response to an overdriver PM1 for driving to a higher external voltage VDD and an overdriving start signal SAOV_EN and a test-delay amount control signal TM_SA_INC and TM_SA_DEC. An overdriving signal generator 30 is provided. And a driver NM1 for driving the power line SB of the bit line sense amplifier to the power supply voltage VSS in response to the driving control signal SAN.

The overdriving signal generator 30 generates a pulse signal in response to the overdriving start signal SAOV_EN, but the increase / delay amount control signal TM_SA_INC and the attenuation-delay amount control signal TM_SA_DEC applied in the test mode. The output signal of the pulse signal generator 10 in response to the increase and decrease and attenuation-delay amount control signals (TM_SA_INC, TM_SA_DEC) for controlling and outputting the activation period of the pulse signal according to An output control unit 20 for controlling to output the over-driving signal SAOVB is provided.

The pulse signal generating unit 10 delays and outputs the overdriving start signal SAOV_EN, and adjusts the delay amount according to the increase / delay amount control signal TM_SA_INC and outputs the delay increase adjusting unit 12. The first delay unit 14 for delaying the output signal of the delay increase control unit 12 for a predetermined time and the output signal of the first delay unit 14 are delayed and outputted, but the attenuation delay control signal ( NAND gate ND2 having a delay amount attenuation adjusting unit 16 for adjusting and outputting the delay degree according to TM_SA_DEC, and an output signal and an overdriving start signal SAOV_EN of the delay amount attenuation adjusting unit 16 as inputs. Is implemented as

The delay amount attenuation control unit 16 includes a second delay unit 18 for delaying the output signal of the first delay unit 14 for a predetermined time, an output signal of the first delay unit 14, and an attenuation delay control signal. NAND gate ND1 having 18 as an input, inverter I1 for inverting and outputting the output signal of NAND gate ND1, output signal of inverter I1, and second delay unit 16 It is implemented by the NOR gate NR1 having an output signal as an input.

The output control unit 20 includes a NAND gate ND3 having an increase / delay amount control signal TM_SA_INC and an attenuation-delay amount control signal TM_SA_DEC as inputs, and an inverter for inverting an output signal of the NAND gate ND3 ( I2) and a NOR gate NR2 for outputting the overdriving signal SAOVB by taking the output signal of the inverter I2 and the output signal of the pulse signal generator 10 as inputs.

FIG. 2 is an internal circuit diagram of the delay increase increase controller 12 of FIG. 1.

Referring to FIG. 2, the delay amount increasing control unit 12 includes an inverting / delaying unit 12a for delaying and inverting the overdriving start signal SAOV_EN, and an output signal of the inverting / delaying unit 12a and increase and decrease. NAND gate ND4 having delay amount control signal TM_SA_INC as input, NAND gate ND5 having output signals of overdriving start signal SAOV_EN and NAND gate ND4 as input, and NAND gate ND5 An inverter I3 for inverting and outputting the output signal.

The process of performing the test mode to find an appropriate overdriving section in the semiconductor memory device as described above will be briefly described.

First, when a large consumption of the core voltage VCORE is expected, such as an active command, the overdriving start signal SAOV_EN is activated.

Accordingly, the pulse signal generator 10 may be configured to delay the overdriving start signal SAOV_EN through the delay increase control unit 12, the first delay unit 14, and the delay amount attenuation control unit 16. And a pulse signal having a delay amount of the delay amount increasing control unit 12, the first delay unit 14, and the delay amount damping control unit 16 as an activation pulse width through a logical combination with the overdriving start signal SAOV_EN. Create

Here, the delay increase increase control unit 12 delays the overdriving start signal SAOV_EN by the delay of the inversion / delay unit 12a when the increase / delay delay control signal TM_SA_INC is activated at the logic level 'H'. When the deceleration-delay amount control signal TM_SA_INC is inactivated, the overdriving start signal SAOV_EN is output with only a predetermined delay. That is, the delay increase control unit 12 adjusts and outputs the delay amount of the overdriving start signal SAOV_EN input according to the increase / delay delay control signal TM_SA_INC.

In addition, the delay amount attenuation control unit 16 outputs the output signal of the first delay unit 14 to the second delay unit 18 in response to the activation of the attenuation-delay amount control signal TM_SA_DEC to the logic level 'H'. When the decay-delay amount control signal TM_SA_DEC is deactivated, the output signal of the first delay unit 14 is output without additional delay.

Subsequently, the output controller 20 overdrives the output signal of the pulse signal generator 10 when the increase / delay amount control signal TM_SA_INC and the attenuation-delay amount control signal TM_SA_DEC have a logic level 'H'. The signal SAOVB is output, and otherwise, the overdriving signal SAOVB is deactivated to a logic level 'H' regardless of the output signal of the pulse signal generator 10.

3 is a view illustrating a change in activation period of an overdriving signal SAOVB in a semiconductor memory device according to the related art. In the case of 'a', an increase / delay amount control signal TM_SA_INC and attenuation-delay amount control signal TM_SA_DEC are shown. This is the case when both are activated. In case of 'b', only the attenuation-delay amount control signal TM_SA_DEC is activated, 'c' is in case of normal mode, not in test mode, and 'd' is case of increase / delay amount control signal TM_SA_INC. Only when is activated.

Comparing each of these cases, it can be seen that it has a relation of 'a <b <c <d' activation pulse width and is adjusted.

The reason why the semiconductor memory device according to the related art performs the test process to find an appropriate overdriving driving time as described above is that if the driving time is not appropriate, the cell data may be failed to decrease reliability or the cell transistor. Because it is physically damaged.

That is, if the driving force of the overdriver is small, the memory cell data may fail because the level of the core voltage VCORE decreases. On the other hand, if the driving force of the overdriver is large, the level of the core voltage VCORE is higher than the desired level. This is because the cell transistor is stressed to cause physical damage or noise.

Therefore, in order to find an appropriate driving time of the overdriver, in the prior art, the appropriate driving time was found by applying the increase / delay amount control signal and the attenuation-delay amount control signal in the test mode.

By the way, the delay amount controlled by the increase / delay amount control signal is fixed by the inversion / delay part, and the delay amount adjustable by the attenuation-delay amount control signal is fixed by the second delay part. Therefore, the activation pulse width of the overdriving signal cannot be variously adjusted, and can only be changed within a fixed range by the delay unit as described above, so that an optimum driving time cannot be found.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of testing by adjusting an overdriving driving time without limiting physical implementation.

According to an aspect of the present invention, there is provided a semiconductor memory device, comprising: first pulse signal generation means for outputting an overdriving start signal as a first pulse signal in synchronization with a clock applied in a test mode; Second pulse signal generating means for outputting the overdriving starting signal as a second pulse signal having an activation pulse width adjusted according to the increase / delay delay control signal and the attenuation delay delay control signal; Selecting means for selectively outputting the first and second pulse signals as an overdriving signal in response to a test-control signal; A bit line sense amplifier block for sensing and amplifying a voltage difference between the bit line pairs of the memory cell array block; A first driver for driving the first power line of the bit line sense amplifier block to a voltage applied to a core voltage supply terminal in response to a first driving control signal; An overdriver for driving the supply terminal of the core voltage to an external voltage higher than the core voltage in response to the overdriving signal; And a second driver for driving the second power line of the bit line sense amplifier block to the first power voltage in response to a second driving control signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram illustrating a semiconductor memory device having an overdriving structure according to a first embodiment of the present invention.

Referring to FIG. 4, the semiconductor memory device according to the first embodiment of the present invention is configured to output the overriding start signal SAOV_EN as a first pulse signal in synchronization with a clock CK applied in a test mode. The second pulse signal having the activation pulse width adjusted according to the first pulse signal generation unit 100 and the overdriving start signal SAOV_EN according to the increase / delay delay control signal TM_SA_INC and the attenuation delay delay control signal TM_SA_DEC. A second pulse signal generator 200 for outputting a signal and a selector 300 for selectively outputting the first and second pulse signals as an overdriving signal SAOVB in response to the test-control signal SAOV_CTR. And a bit line detection amplifier block 400 for detecting and amplifying the voltage difference between the bit line pairs of the memory cell array block, and a power line RTO of the bit line detection amplifier block 400 in response to the driving control signal SAP. To the core voltage (VCORE) supply The driver PM2 for driving with a voltage and the overdriver PM1 for driving the supply terminal of the core voltage VCORE with an external voltage VDD higher than the internal core voltage VCORE in response to the overdriving signal SAOVB. ). And a driver NM1 for driving the power line SB of the bit line sense amplifier to the power supply voltage VSS in response to the driving control signal SAN.

The first pulse signal generator 100 responds to the flip-flop 120 and the overdriving start signal SAOV_EN to output the overdriving start signal SAOV_EN in synchronization with a falling edge of the clock CK applied thereto. And an output control unit 140 for controlling the output signal of the flip-flop 120 to be output as the first pulse signal.

The output control unit 140 inverts the NAND gate ND6 having the output signal of the flip-flop 120 and the overdriving start signal SAOV_EN as an input, and inverts the output signal of the NAND gate ND6 as a first pulse signal. Inverter I4 is provided.

In addition, the selector 300 may deactivate the inverter I4 for outputting the first pulse signal as the overdriving signal SAOVB and the test-control signal SAOV_CTR in response to the activation of the test-control signal SAOV_CTR. In response, an inverter I5 for outputting the second pulse signal as the overdriving signal SAOVB is provided.

For reference, since the second pulse signal generator 200 has the same circuit implementation and operation as the conventional pulse signal generator 10, a detailed description thereof will be omitted. The second pulse signal generator 200 may be configured to generate the overdriving signal SAOVB in the normal mode and to replace the overdrive when the malfunction of the first pulse signal generator 100 occurs in the test mode. It is not an essential block for testing to find the proper driving time of the signal SAOVB. Therefore, when the second pulse signal generator 200 is not provided, the first pulse signal is directly output as the overdriving signal SAOVB without the selector 300.

Next, an operation of the semiconductor memory device according to the first embodiment of the present invention will be briefly described.

First, when a large consumption of the core voltage VCORE is expected, such as an active command, the overdriving start signal SAOV_EN is activated.

Subsequently, the first pulse signal generation unit 100 outputs the overdriving start signal SAOV_EN as a first pulse signal in synchronization with a polling edge of a clock CK applied from the outside. Here, since the activation width of the first pulse signal is determined by the period of the clock CK, an appropriate driving time can be found by adjusting the period of the clock CK applied from the outside. At this time, since the period of the clock CK is adjusted, the range of activation of the overdriving signal is not limited by the physical implementation element, and various variations are possible.

The second pulse signal generator 200 outputs a second pulse signal whose activation width is adjusted according to the increase / delay amount control signal TM_SA_INC and the attenuation-delay amount control signal TM_SA_DEC in the test mode, and normal mode. The overdriving start signal SAOV_EN is output as a second pulse signal with a predetermined delay at.

Next, when the test-control signal SAOV_CTR has a logic level 'H', the selector 300 outputs the first pulse signal as an overdriving signal SAOVB, and the test-control signal SAOV_CTR is a logic level. In case of having 'L', the second pulse signal is output as the overdriving signal SAOVB.

Therefore, when the semiconductor memory device enters the test mode and the test-control signal SAOV_CTR is activated, the first pulse signal is outputted with the overdriving signal SAOVB. As described above, in the test mode, an appropriate driving time of overdriving can be found by adjusting the clock CK period.

In the normal mode, the test-control signal SAOV_CTR is inactivated, so that an overdriving signal SAOVB having a predetermined delay as an activation pulse width is generated when the circuit is implemented, thereby overdriving the bit line detection amplifier.

FIG. 5 illustrates a change in the activation width of the overdriving signal SAOVB according to a change in the clock CK period applied in the test mode. As described above, FIG. 5 illustrates a flip-flop in the first pulse signal generator 100. 120 outputs the applied overdriving start signal SAOV_EN in synchronization with the falling edge of the clock CK. Since this is output as the overdriving signal SAOVB through the selector 300, the activation pulse width of the overdriving signal SAOVB is the time between the activation time of the overdriving start signal SAOV_EN and the falling edge of the clock CK. Becomes

Therefore, as shown in the figure, when the falling edge of the clock CK has a change of 'α', the activation period of the overdriving signal SAOVB also has a change of 'α'.

FIG. 6 is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention. In comparison with the semiconductor memory device according to the first embodiment, it can be seen that a clock divider 500 is further provided.

That is, the semiconductor memory device according to the second embodiment divides the clock CK applied from the outside through the clock divider 500 and uses the flip-flop 120.

Therefore, in the semiconductor memory device to which a high frequency operation is required and a clock having a short frequency is applied as in the present, the period is increased by using the clock divider 500, so that the test mode for adjusting the activation period of the overdriving signal SAOVB is controlled. Will be able to perform.

For reference, blocks in the semiconductor memory device according to the second exemplary embodiment except for the clock divider 500 are the same as those of the first exemplary embodiment, and therefore, the same reference numerals are used and detailed description thereof will be omitted.

FIG. 7 illustrates a change in activation period of the overdry signal SAOVB according to the test mode of the semiconductor memory device shown in FIG. 6.

As shown in the drawing, when the clock divider 500 divides and outputs the clock CK applied from the outside, the flip-flop 120 in the first pulse signal generator 100 divides the divided clock CK2B. The overdriving signal SAOVB is output in synchronization with the rising edge of?

When the period of the clock CK varies in the 'β' range, the overdriving signal SAOVB also has a change in the 'β' range.

Therefore, the above-described semiconductor memory device according to the present invention adjusts the overdriving period through a clock cycle, and thus can not measure the driving time more precisely because it is not limited only within a predetermined range according to the circuit implementation as in the prior art. have.

In addition, when the applied clock is a high frequency, a clock divider is further provided, so that an appropriate driving time of the overdriving signal can be measured even in a high frequency environment.

On the other hand, the semiconductor memory device according to the second embodiment of the present invention has a clock divider for dividing an applied clock by two, but this embodiment is not limited by the division ratio of the clock.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The above-described present invention synchronizes the time for performing the overdriving with the flip-flop to the edge of the clock, so that the range of adjustment for measuring the driving time is not limited by the physical elements according to the implementation, so that more accurate measurement This is possible. In addition, since the clock divider is provided, the same effect can be obtained even in a semiconductor memory device driven at a high frequency.

Claims (8)

First pulse signal generating means for outputting the overdriving start signal as a first pulse signal in synchronization with a clock applied in a test mode; Second pulse signal generating means for outputting the overdriving starting signal as a second pulse signal having an activation pulse width adjusted according to the increase / delay delay control signal and the attenuation delay delay control signal; Selecting means for selectively outputting the first and second pulse signals as an overdriving signal in response to a test-control signal; A bit line sense amplifier block for sensing and amplifying a voltage difference between the bit line pairs of the memory cell array block; A first driver for driving the first power line of the bit line sense amplifier block to a voltage applied to a core voltage supply terminal in response to a first driving control signal; An overdriver for driving the supply terminal of the core voltage to an external voltage higher than the core voltage in response to the overdriving signal; And A second driver for driving the second power line of the bit line sense amplifier block to the first power voltage in response to a second driving control signal; A semiconductor memory device having a. The method of claim 1, The first pulse signal generating means, A flip-flop for outputting the overdriving start signal in synchronization with a falling edge of an applied clock; An output controller for controlling the output signal of the flip-flop to be output as the first pulse signal in response to the overdriving start signal A semiconductor memory device comprising: a. The method of claim 2, The output control unit, A NAND gate having an output signal of the flip flop and the overdriving start signal as an input; A first inverter for inverting the output signal of the NAND gate to output the first pulse signal A semiconductor memory device comprising: a. The method of claim 2, The selection means, A second inverter for outputting the first pulse signal as the overdriving signal in response to activation of the test-control signal; And a third inverter for outputting the second pulse signal as the overdriving signal in response to deactivation of the test-control signal. Pulse signal generating means for outputting the overdriving start signal as an overdriving signal in synchronization with a clock applied in a test mode; A bit line sense amplifier block for sensing and amplifying a voltage difference between the bit line pairs of the memory cell array block; A first driver for driving the first power line of the bit line sense amplifier block to a voltage applied to a core voltage supply terminal in response to a first driving control signal; An overdriver for driving the supply terminal of the core voltage to an external voltage higher than the core voltage in response to the overdriving signal; And A second driver for driving the second power line of the bit line sense amplifier block to the first power voltage in response to a second driving control signal; A semiconductor memory device having a. The method of claim 5, The pulse signal generating means, A flip-flop for outputting the overdriving start signal in synchronization with a falling edge of the applied clock; An output controller for controlling the output signal of the flip-flop to be output as the overdriving signal in response to the overdriving start signal A semiconductor memory device, characterized in that provided. Clock dividing means for dividing and outputting an applied clock; First pulse signal generation means for outputting an overdriving start signal as a first pulse signal in synchronization with an output clock of the clock division means; Second pulse signal generating means for outputting the overdriving starting signal as a second pulse signal having an activation pulse width adjusted according to the increase / delay delay control signal and the attenuation delay delay control signal; Selecting means for selectively outputting the first and second pulse signals as an overdriving signal in response to a test-control signal; A bit line sense amplifier block for sensing and amplifying a voltage difference between the bit line pairs of the memory cell array block; A first driver for driving the first power line of the bit line sense amplifier block to a voltage applied to a core voltage supply terminal in response to a first driving control signal; An overdriver for driving the supply terminal of the core voltage to an external voltage higher than the core voltage in response to the overdriving signal; And A second driver for driving the second power line of the bit line sense amplifier block to the first power voltage in response to a second driving control signal; A semiconductor memory device having a. The method of claim 7, wherein The first pulse signal generating means, A flip-flop for outputting the overdriving start signal in synchronization with a rising edge of an output clock of the clock division means; An output controller for controlling the output signal of the flip-flop to be output as the first pulse signal in response to the overdriving start signal A semiconductor memory device comprising: a.

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